CA3420_05 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 2V Supply at 300 µA Supply Current
  • 1pA Input Current (Typ) (Essentially Constant to 85°C)
  • Rail-to-Rail Output Swing (Drive ±2mA into 1kΩ Load)
  • Pin Compatible with 741 Operational Amplifiers
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • pH Probe Amplifiers
  • Picoammeters
  • Electrometer (High Z) Instruments
  • Portable Equipment
  • Inaccessible Field Equipment
  • Battery-Dependent Equipment (Medical and Military) Functional Diagram Pinout CA3420 (PDIP) TOP VIEW

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA3420E CA3420E -55 to 125 8 Ld PDIP E8.3 CA3420EZ (Note) CA3420EZ -55 to 125 8 Ld PDIP* (Pb-free) E8.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. MOS BIPOLAR MOS BIPOLAR OTA BUFFER (X2) HIGH GAIN (50K) BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK OFFSET NULL INV. INPUT NON-INV. INPUT STROBE OUTPUT OFFSET NULL Data Sheet October 4, 2005 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN1320.9 October 4, 2005 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±10V, TA = 25°C PARAMETER SYMBOL TEST CONDITIONS TYP UNITS Input Resistance R I 150 T Ω Input Capacitance C I 4.9 pF Output Resistance R O 300 Ω Equivalent Input Noise Voltage e N f = 1kHz R S = 100Ω 62 nV/ √Hz f = 10kHz 38 nV/ √Hz Short-Circuit Current Source I OM+2 . 6 m A To Opposite Supply Sink I OM-2 . 4 m A Gain Bandwidth Product f T 0.5 MHz Slew Rate SR 0.5 V/ µs Transient Response Rise Time t R RL = 2kΩ, CL = 100pF 0.7 µs Overshoot OS 15 % Current from Terminal 8 To V- I 8+2 0 µA To V+ I 8-2 m A Electrical Specifications For Equipment Design, At VSUPPLY = ±1V, TA = 25°C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |V IO| - 5 10 mV Input Offset Current (Note 3) |I IO| - 0.01 4 pA Input Current (Note 3) |I I|- 1 5 p A Large Signal Voltage Gain A OL RL = 10kΩ 10 100 - kV/V 80 100 - dB Common Mode Rejection Ratio CMRR - 560 1800 µV/V 55 65 - dB Common Mode Input Voltage Range V lCR+0 . 2 0 . 5 - V VlCR-- - 1 . 3 - V Power Supply Rejection Ratio PSRR ∆VIO/∆V - 100 1000 µV/V 60 80 - dB Max Output Voltage V OM+R L = ∞ 0.90 0.95 - V Supply Current I+ - 350 650 µA Device Dissipation P D -0 . 7 1 . 1 m W Input Offset Voltage Temperature Drift ∆VlO/∆T- 4 - µV/°C NOTE: 3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. CA3420

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1320.9 October 4, 2005 CA3420 Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusi ons shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A- 0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 -5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93