CA3338 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 7
Technical content
Features
- CMOS/SOS Low Power
- R2R Output, Segmented for Low “Glitch”
- CMOS/TTL Compatible Inputs
- Fast Settling: (Typ) to
- Feedthrough Latch for Clocked or Unclocked Use
- Data Complement Control
- Unipolar or Bipolar Operation
Applications
- TV/Video Display
- High Speed Oscilloscope Display
- Digital Waveform Generator
- Direct Digital Synthesis
Description
The CA3338 family are CMOS/SOS high speed R2R voltage output digital-to-analog converters. They can operate from a single +5V supply, at video speeds, and can produce “rail-to-rail” output swings. Internal level shifters and a pin for an optional second supply provide for an output range below digital ground. The data complement control allows the inver- sion of input data while the latch enable control provides either feedthrough or latched operation. Both ends of the R2R ladder network are available externally and may be modulated for gain or offset adjustments. In addition, “glitch” energy has been kept very low by segmenting and thermom- eter encoding of the upper 3 bits. The CA3338 is manufactured on a sapphire substrate to give low dynamic power dissipation, low output capacitance, and inherent latch-up resistance. Pinout CA3338, CA3338A (PDIP, SBDIP, SOIC) TOP VIEW
Ordering Information
V SS VDD COMP VREF + VOUT VREF - VEE LE PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE ( oC) PACKAGE PKG. NO. CA3338E ±1.0 LSB -40 to 85 16 Ld PDIP E16.3 CA3338AE ±0.75 LSB -40 to 85 16 Ld PDIP E16.3 CA3338D ±1.0 LSB -55 to 125 16 Ld SBDIP D16.3 CA3338AD ±0.75 LSB -55 to 125 16 Ld SBDIP D16.3 CA3338M ±1.0 LSB -40 to 85 16 Ld SOIC M16.3 CA3338AM ±0.75 LSB -40 to 85 16 Ld SOIC M16.3 File Number 1850.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999
V EE VREF - VOUT VREF + R R R LE R ≅ 160Ω R R R R CA3338, CA3338A
Absolute Maximum Ratings Thermal Information (VDD - VSS or VDD - VEE , Whichever is Greater) Input Voltage Range DC Input Current Operating Conditions Temperature Range (TA) Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, VDD = 5V, VREF + = 4.608V, VSS = VEE = VREF - = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ , Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution 8 - - Bits Integral Linearity Error See Figure 4 CA3338 - - ±1 LSB CA3338A - - ±0.75 LSB Differential Linearity Error See Figure 4 CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB Gain Error Input Code = FF HEX , See Figure 3 CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB Offset Error Input Code = 00 HEX ; See Figure 3 - - ±0.25 LSB DIGITAL INPUT TIMING Update Rate To Maintain 1/2 LSB Settling DC 50 - MHz Update Rate V REF - = VEE = -2.5V, VREF + = +2.5V DC 20 - MHz Set Up Time tSU1 For Low Glitch - -2 - ns Set Up Time tSU2 For Data Store - 8 - ns Hold Time tH For Data Store - 5 - ns Latch Pulse Width tW For Data Store - 5 - ns Latch Pulse Width tW VREF - = VEE = -2.5V, VREF + = +2.5V - 25 - ns OUTPUT PARAMETERS R L Adjusted for 1VP-P Output Output Delay tD1 From LE Edge - 25 - ns Output Delay tD2 From Data Changing - 22 - ns Rise Time tr 10% to 90% of Output - 4 - ns Settling Time tS 10% to Settling to1/2 LSB - 20 - ns Output Impedance V REF + = 6V, VDD = 6V 120 160 200 Ω Glitch Area - 150 - pV/s Glitch Area V REF - = VEE = -2.5V,VREF + = +2.5V - 250 - pV/s CA3338, CA3338A
The digital inputs (LE, COMP , and D0 - D7) are of TTL compatible HCT High Speed CMOS design: the loading is essentially capacitive and the logic threshold is typically 1.5V. The 8 data bits, D0 (weighted 2 0) through D7 (weighted 27), are applied to Exclusive OR gates (see Functional Diagram). The COMP (data complement) control provides the second input to the gates: if COMP is high, the data bits will be inverted as they pass through. The input data and the LE (latch enable) signals are next applied to a level shifter. The inputs, operating between the levels of V DD and VSS , are shifted to operate between VDD and VEE . VEE optionally at ground or at a negative voltage, will be discussed under bipolar operation. All further logic elements except the output drivers operate from the V DD and VEE supplies. The upper 3 bits of data, D5 through D7, are input to a 3-to-7 line bar graph encoder. The encoder outputs and D0 through D4 are applied to a feedthrough latch, which is controlled by LE (latch enable). REFERENCE VOLTAGE VREF + Range (+) Full Scale, Note 1 V REF - + 3 - V DD V VREF - Range (-) Full Scale, Note 1 V EE -V REF + - 3 V VREF + Input Current V REF + = 6V, VDD = 6V - 40 50 mA SUPPLY VOLTAGE Static I DD or IEE LE = Low, D0 - D7 = High - 100 220 µA LE = Low, D0 - D7 = Low - - 100 µA Dynamic IDD or IEE VOUT = 10MHz, 0V to 5V Square Wave - 20 - mA Dynamic IDD or IEE VOUT = 10MHz,±2.5V Square Wave - 25 - mA VDD Rejection 50kHz Sine Wave Applied - 3 - mV/V VEE Rejection 50kHz Sine Wave Applied - 1 - mV/V DIGITAL INPUTS D0 - D7, LE, COMP High Level Input Voltage Note 1 2 - - V Low Level Input Voltage Note 1 - - 0.8 V Leakage Current - ±1 ±5 µA Capacitance - 5 - pF TEMPERATURE COEFFICIENTS Output Impedance - 200 - ppm/ oC NOTE: 1. Parameter not tested. but guaranteed by design or characterization. Electrical SpecificationsTA = 25oC, VDD = 5V, VREF + = 4.608V, VSS = VEE = VREF - = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ , Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Pin Descriptions PIN NAME DESCRIPTION
1 D7 Most Significant Bit
2 D6 Input
3 D5 Data
4 D4 Bits
5 D3 (High = True)
9D 0 Least Significant Bit. Input Data Bit
10 V EE Analog Ground
11 VREF - Reference Voltage Negative Input
12 V OUT Analog Output
13 VREF + Reference Voltage Positive Input
14 COMP Data Complement Control input. Active High 15 LE Latch Enable Input. Active Low 16 V DD Digital Power Supply, +5V CA3338, CA3338A
well bypassed as near the chip as possible. positive or negative-going step. It is usually expressed in pV/s. typical hook-up for checking “glitch” energy or settling time. as Tektronix part number 131-0258-00 is recommended.
00 OUTPUT VOLTAGE
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
8 DATA BITS
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT
- VOUT(P-P) is approximate, and will vary as ROUT of D/A varies.
- All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.
- Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
The output of the CA3338 can be resistively divided to match a doubly terminated 50Ω or 75Ω line, although peak-to-peak swings of less than 1V may result. The output magnitude will also vary with the converter’s output impedance. Figure 5 shows such an application. Note that because of the HCT input structure, the CA3338 could be operated up to +7.5V V DD and VREF + supplies and still accept 0V to 5V CMOS input voltages. If larger voltage swings or better accuracy is desired, a high speed output buffer, such as the HA-5033, HA-2542, or CA3450, can be employed. Figure 6 shows a typical applica- tion, with the output capable of driving±2V into multiple 50Ω terminated lines. Operating and Handling Considerations HANDLING All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recom- mended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” OPERATING Operating Voltage During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause the absolute maximum ratings to be exceeded. Input Signals To prevent damage to the input protection circuit, input signals should never be greater than V DD nor less than VSS . Input currents must not exceed 20mA even when the power supply is off. Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either V CC or GND, whichever is appropriate. NOTES: 1. Both VREF + pin and 392Ω resistor should be bypassed within1/4 inch. 2. Keep nodal capacitance at CA3450 pin 3 as low as possible. 3. VOUT Range =±3V at CA3450. CLOCK
8 DATA
+5V 1-7, 9 LE D0 - D7 VDD COMP VSS CA3338 VOUT VREF + VEE R VREF - R UP TO 5 OUTPUT LINES FOR R = 75Ω , 3 LINES FOR R = 50Ω VOUT 1 VOUT N +3.00V AT 25mA 4.7µF TAN 4.7µF TAN 4.7µF TAN 4.7µF TAN 0.1µF CER. 0.1µF CER. 0.1µF CER. 0.1µF CER. +6V -6V 392Ω 392Ω 10kΩ 1kΩ 4, 5, 12, 13 R R VOUT =±1.5VPEAK 7, 8 CA3450 ADJUST OFFSET 5pF BITS FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND V REF