CA3338_04 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
CMOS/SOS Low Power R2R Output, Segmented for Low “Glitch” CMOS/TTL Compatible Inputs Fast Settling: (Typ) to Feedthrough Latch for Clocked or Unclocked Use Data Complement Control Unipolar or Bipolar Operation Pb-free Available
Applications
TV/Video Display High Speed Oscilloscope Display Digital Waveform Generator Direct Digital Synthesis Pinout CA3338, CA3338A (PDIP, SOIC) TOP VIEW PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA3338E ±1.0 LSB -40 to 85 16 Ld PDIP E16.3 CA3338EZ (Note) ±1.0 LSB -40 to 85 16 Ld PDIP (Pb-free) E16.3 CA3338AE ±0.75 LSB -40 to 85 16 Ld PDIP E16.3 CA3338AEZ (Note) ±0.75 LSB -40 to 85 16 Ld PDIP (Pb-free) E16.3 CA3338M ±1.0 LSB -40 to 85 16 Ld SOIC M16.3 CA3338MZ (Note) ±1.0 LSB -40 to 85 16 Ld SOIC (Pb-free) M16.3 CA3338AM ±0.75 LSB -40 to 85 16 Ld SOIC M16.3 CA3338AMZ (Note) ±0.75 LSB -40 to 85 16 Ld SOIC (Pb-free) M16.3 Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. V SS VDD COMP VREF + VOUT VREF - VEE LE FN1850.4 CA3338, CA3338A Data Sheet July 2004
V SS THERMOMETER ENCODER 3-BIT LEVEL SHIFTERS FEEDTHROUGH LATCHES V EE VREF - VOUT VREF + R R R LE R ≅ 160Ω R R R R CA3338, CA3338ACA3338, CA3338A
CA3338, CA3338A Absolute Maximum Ratings Thermal Information (VDD - VSS or VDD - VEE , Whichever is Greater) Input Voltage Range DC Input Current Operating Conditions Temperature Range (TA) Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, VDD = 5V, VREF + = 4.608V, VSS = VEE = VREF - = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution 8 - - Bits Integral Linearity Error See Figure 4 CA3338 - - ±1L S B CA3338A - - ±0.75 LSB Differential Linearity Error See Figure 4 CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB Gain Error Input Code = FF HEX , See Figure 3 CA3338 - - ±0.75 LSB CA3338A - - ±0.5 LSB Offset Error Input Code = 00 HEX ; See Figure 3 - - ±0.25 LSB DIGITAL INPUT TIMING Update Rate To Maintain 1/2 LSB Settling DC 50 - MHz Update Rate V REF - = VEE = -2.5V, VREF + = +2.5V DC 20 - MHz Set Up Time tSU1 For Low Glitch - -2 - ns Set Up Time tSU2 For Data Store - 8 - ns Hold Time tH For Data Store - 5 - ns Latch Pulse Width tW For Data Store - 5 - ns Latch Pulse Width tW VREF - = VEE = -2.5V, VREF + = +2.5V - 25 - ns OUTPUT PARAMETERS R L Adjusted for 1VP-P Output Output Delay tD1 From LE Edge - 25 - ns Output Delay tD2 From Data Changing - 22 - ns Rise Time tr 10% to 90% of Output - 4 - ns Settling Time tS 10% to Settling to 1/2 LSB - 20 - ns Output Impedance V REF + = 6V, VDD = 6V 120 160 200 Ω Glitch Area - 150 - pV/s Glitch Area V REF - = VEE = -2.5V,VREF + = +2.5V - 250 - pV/s
CA3338, CA3338A REFERENCE VOLTAGE VREF + Range (+) Full Scale, Note 2 V REF - + 3 - V DD V VREF - Range (-) Full Scale, Note 2 V EE -V REF + - 3 V VREF + Input Current V REF + = 6V, VDD = 6V - 40 50 mA SUPPLY VOLTAGE Static I DD or IEE LE = Low, D0 - D7 = High - 100 220 µA LE = Low, D0 - D7 = Low - - 100 µA Dynamic IDD or IEE VOUT = 10MHz, 0V to 5V Square Wave - 20 - mA Dynamic IDD or IEE VOUT = 10MHz, ±2.5V Square Wave - 25 - mA VDD Rejection 50kHz Sine Wave Applied - 3 - mV/V VEE Rejection 50kHz Sine Wave Applied - 1 - mV/V DIGITAL INPUTS D0 - D7, LE, COMP High Level Input Voltage Note 2 2 - - V Low Level Input Voltage Note 2 - - 0.8 V Leakage Current - ±1 ±5 µA Capacitance - 5 - pF TEMPERATURE COEFFICIENTS Output Impedance - 200 - ppm/× oC NOTE: 2. Parameter not tested. but guaranteed by design or characterization. Electrical SpecificationsTA = 25oC, VDD = 5V, VREF + = 4.608V, VSS = VEE = VREF - = GND, LE Clocked at 20MHz, RL ≥ 1 MΩ, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
are applied to Exclusive OR gates (see Functional Diagram). inverted as they pass through. tied low for non-clocked operation. settling) sets the upper limit of usable clock frequency. which in turn feed a modified R2R ladder network. REF +, the (+) full-scale reference.
1 D7 Most Significant Bit
2 D6 Input
5 D3 (High = True)
10 V EE Analog Ground
11 VREF - Reference Voltage Negative Input
12 V OUT Analog Output
13 VREF + Reference Voltage Positive Input
FIGURE 1. DATA TO LATCH ENABLE TIMING FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
decreases when the bipolar mode is used. OFFSET and GAIN errors, respectively; see Figure 3. Figure 4. Note that the error is expressed in fractions of the for increasing code or decrease for decreasing code). linearity error, usually expressed in LSBs. See Figure 4. also take these errors into account. well bypassed as near the chip as possible. positive or negative-going step. It is usually expressed in pV/s. typical hook-up for checking “glitch” energy or settling time. as Tektronix part number 131-0258-00 is recommended. FIGURE 3. D/A OFFSET AND GAIN ERROR
00 OUTPUT VOLTAGE
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
8 DATA BITS
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT
- VOUT(P-P) is approximate, and will vary as ROUT of D/A varies.
- All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.
- Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
- Both VREF + pin and 392Ω resistor should be
- Keep nodal capacitance at CA3450 pin 3 as
- VOUT Range = ±3V at CA3450.
8 DATA
FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
CA3338, CA3338A The output of the CA3338 can be resistively divided to match a doubly terminated 50Ω or 75Ω line, although peak-to-peak swings of less than 1V may result. The output magnitude will also vary with the converter’s output impedance. Figure 5 shows such an application. Note that because of the HCT input structure, the CA3338 could be operated up to +7.5V V DD and VREF + supplies and still accept 0V to 5V CMOS input voltages. If larger voltage swings or better accuracy is desired, a high speed output buffer, such as the HA-5033, HA-2542, or CA3450, can be employed. Figure 6 shows a typical application, with the output capable of driving ±2V into multiple 50Ω terminated lines. Operating and Handling Considerations HANDLING All inputs and outputs of CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” OPERATING OPERATING VOLTAGE During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause the absolute maximum ratings to be exceeded. INPUT SIGNALS To prevent damage to the input protection circuit, input signals should never be greater than V DD nor less than VSS . Input currents must not exceed 20mA even when the power supply is off. UNUSED INPUTS A connection must be provided at every input terminal. All unused input terminals must be connected to either VCC or GND, whichever is appropriate. TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND V REF
CA3338, CA3338A Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com CA3338, CA3338A Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H µ 0.25(0.010) BM M α M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0o 8o 0o 8o - Rev. 0 12/93