CA3318 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- Parallel Conversion Technique
- 8-Bit Latched Three-State Output with Overflow Bit
- 2 Units in Series Allow 9-Bit Output
- 2 Units in Parallel Allow 30MHz Sampling Rate
Applications
- TV Video Digitizing (Industrial/Security/Broadcast)
- High Speed A/D Conversion
- Ultrasound Signature Analysis
- Transient Signal Analysis
- High Energy Physics Research
- General-Purpose Hybrid ADCs
- Optical Character Recognition
- Radar Pulse Analysis
- Motion Signature Analysis
- µP Data Acquisition Systems
Description
The CA3318 is a CMOS parallel (FLASH) analog-to-digital converter designed for applications demanding both low power consumption and high speed digitization. The CA3318 operates over a wide full scale input voltage range of 4V up to 7.5V with maximum power consumption depending upon the clock frequency selected. When operated from a 5V supply at a clock frequency of 15MHz, the typical power consumption of the CA3318 is 150mW. The intrinsic high conversion rate makes the CA3318 ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3318s in series to increase the resolution of the conversion system. A series connection of two CA3318s may be used to produce a 9-bit high speed converter. Operation of two CA3318s in parallel doubles the conversion speed (i.e., increases the sampling rate from 15MHz to 30MHz). 256 paralleled auto balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the CA3318. 255 comparators are required to quantize all input voltage levels in this 8-bit converter, and the additional comparator is required for the overflow bit.
Ordering Information
(PDIP, SBDIP, SOIC) TOP VIEW PART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE ( oC) PACKAGE PKG. NO. CA3318CE ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld PDIP E24.6 CA3318CM ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld SOIC M24.3 CA3318CD ±1.5 LSB 15MHz (67ns) -40 to 85 24 Ld SBDIP D24.6 (LSB) B1 (MSB) B8 OVERFLOW 1/4R (DIG. GND) VSS (DIG. SUP.) VDD VAA + (ANA. SUP.) VREF + VIN p PHASE VAA - (ANA. GND) VREF - CE1 CE2 3/4R CLK VIN CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999
# 256 # 193 # 129 # 65 3/4 REF 1/2 REF 1/4 REF VREF + VIN VAA + VIN VREF - (NOTE 1) COMPARATOR #1 LATCH LATCH LATCH OVER- FLOW THREE- STATE DRIVERS OUTPUT REGISTER DIGITAL SUPPLY 12 VDD φ2 φ1 φ1 φ1 φ1 φ2 φ1 BIT 8 (MSB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB) CE1 CE2 DIGITAL GND 11 VSS CLOCK PHASE VAA - ANALOG GND φ1 (AUTO BALANCE) φ2 (SAMPLE UNKNOWN) NOTE: ≅ 50K 1/2 R = 4Ω = 30Ω = 7Ω R = 2Ω R R R R R R ≅2K ANALOG SUPPLY 1/2 R R LATCH 256 COUNT 256 DQ 1. Cascaded Auto Balance (CAB). CA3318
Absolute Maximum Ratings Thermal Information (Referenced to VSS or VAA - Terminal, Whichever is More Negative) Input Voltage Range Bits 1-8, Overflow (Outputs Off) Clock, Phase,CE1, CE2, VIN, Bits 1-8, Overflow Operating Conditions Operating Voltage Range (VDD or VAA +) . . . 4V (Min) to 7.5V (Max) Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsAt 25oC, VAA + = VDD = 5V, VREF + = 6.4V, VREF - = VAA - = VSS , CLK = 15MHz, All Reference Points Adjusted, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution 8 - - Bits Integral Linearity Error - - ± 1.5 LSB Differential Linearity Error - - +1, -0.8 LSB Offset Error, Unadjusted V IN = VREF - +1/2 LSB -0.5 4.5 6.4 LSB Gain Error Unadjusted VIN = VREF + -1/2 LSB -1.5 0 1.5 LSB DYNAMIC CHARACTERISTICS Maximum Input Bandwidth (Note 1) CA3318 2.5 5.0 - MHz Maximum Conversion Speed CLK = Square Wave 15 17 - MSPS Signal to Noise Ratio (SNR) f S = 15MHz, fIN = 100kHz - 47 - dB fS = 15MHz, fIN = 4MHz - 43 - dB Signal to Noise Ratio (SINAD) f S = 15MHz, fIN = 100kHz - 45 - dB fS = 15MHz, fIN = 4MHz - 35 - dB Total Harmonic Distortion, THD f S = 15MHz, fIN = 100kHz - -46 - dBc fS = 15MHz, fIN = 4MHz - -36 - dBc Effective Number of Bits (ENOB) f S = 15MHz, fIN = 100kHz - 7.2 - Bits fS = 15MHz, fIN = 4MHz - 5.5 - Bits Differential Gain Error Unadjusted - 2 - % Differential Phase Error Unadjusted - 1 - % ANALOG INPUTS Full Scale Range, V IN and (VREF +) - (VREF -) Notes 2, 4 4 - 7 V Input Capacitance, VIN -3 0- p F Input Current, VIN, (See Text) V IN = 5V, VREF + = 5V - - 3.5 mA REFERENCE INPUTS Ladder Impedance 270 500 800 Ω =RMSSignal = RMSSignal CA3318
- A full scale sine wave input of greater than fCLOCK /2 or the specified input bandwidth (whichever is less) may cause an erroneous code.
The -3dB bandwidth for frequency response purposes is greater than 30MHz.
- VIN (Full Scale) or VREF + should not exceed VAA + + 1.5V for accuracy.
- The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1VP-P minimum source.
- Parameter not tested, but guaranteed by design or characterization.
FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM
(φ2) occurs during the low period of the clock cycle. ofφ1 andφ2 refers to the high and low periods of the same clock. N = tap number (1 through 256). of capacitors now charges to their associated tap voltages. FIGURE 10. ENOB vs INPUT FREQUENCY
1 B1 Bit 1 (LSB) Output Data Bits
3 B3 Bit 3
4 B4 Bit 4
5 B5 Bit 5
6 B6 Bit 6
7 B7 Bit 7
8 B8 Bit 8 (MSB)
9 OF Overflow
11 V SS Digital Ground
12 V DD Digital Power Supply, +5V
13 CE2 Three-State Output Enable Input,
Active Low, See Truth Table.
14 CE1 Three-State Output Enable Input
Active High. See Truth Table.
15 V REF - Reference Voltage Negative Input
16 V IN Analog Signal Input
17 V AA - Analog Ground
18 CLK Clock Input
19 PHASE Sample clock phase control input. the clock is high (see text).
21 V IN Analog Signal Input
22 V REF + Reference Voltage Positive Input
24 V AA + Analog Power Supply, +5V
At the same time a second set of commutating capacitors and amplifiers is also auto-balanced. The balancing of the second-stage amplifier at its intrinsic trip point removes any tracking differences between the first and second amplifier stages. The cascaded auto-balance (CAB) technique, used here, increases comparator sensitivity and temperature tracking. In the “Sample Unknown” phase, all ladder tap switches and comparator shorting switches are opened. At the same time V lN is switched to the first set of commutating capacitors. Since the other end of the capacitors are now looking into an effectively open circuit, any input voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators that had tap voltages greater than V lN will go to a “high” state at their outputs. All comparators that had tap voltages lower than VlN will go to a “low” state. The status of all these comparator amplifiers is AC coupled through the second-stage comparator and stored at the end of this phase (φ2) by a latching amplifier stage. The latch feeds a second latching stage, triggered at the end ofφ1. This delay allows comparators extra settling time. The status of the comparators is decoded by a 256 to 9-bit decoder array, and the results are clocked into a storage register at the end of the nextφ2. A 3-stage buffer is used at the output of the 9 storage regis- ters which are controlled by two chip-enable signals. CE1 will independently disable B1 through B6 when it is in a high state. CE2 will independently disable B1 through B8 and the OF buffers when it is in the low state. To facilitate usage of this device, a phase control input is pro- vided which can effectively complement the clock as it enters the chip. Continuous-Clock Operation One complete conversion cycle can be traced through the CA3318 via the following steps. (Refer to timing diagram.) With the phase control in a “low” state, the rising edge of the clock input will start a “sample” phase. During this entire “high” state of the clock, the comparators will track the input voltage and the first-stage latches will track the comparator outputs. At the falling edge of the clock, all 256 comparator outputs are captured by the 256 latches. This ends the “sam- ple” phase and starts the “auto-balance” phase for the com- parators. During this “low” state of the clock, the output of the latches settles and is captured by a second row of latches when the clock returns high. The second-stage latch output propagates through the decode array, and a 9-bit code appears at the D inputs of the output registers. On the next falling edge of the clock, this 9-bit code is shifted into the out- put registers and appears with time delay t D as valid data at the output of the three-state drivers. This also marks the end of the next “sample” phase, thereby repeating the conversion process for this next cycle. Pulse-Mode Operation The CA3318 needs two of the same polarity clock edges to complete a conversion cycle: If, for instance, a negative going clock edge ends sample “N”, then data “N” will appear after the next negative going edge. Because of this require- ment, and because there is a maximum sample time of 500ns (due to capacitor droop), most pulse or intermittent sample applications will require double clock pulsing. If an indefinite standby state is desired, standby should be in auto-balance, and the operation would be as in Figure 3A. If the standby state is known to last less than 500ns and lowest average power is desired, then operation could be as in Figure 3B. Increased Accuracy In most cases the accuracy of the CA3318 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, five adjustments can be made to obtain better accuracy, i.e., offset trim; gain trim; and 1/4,1/2 and3/4 point trim. Offset Trim In general, offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the op amp. When this is not possible the VREF - input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equa- tion is as follows: VlN (0 to 1 transition) =1/2 LSB =1/2 (VREF /256) = VREF /512. If VlN for the first transition is less than the theoretical, then a single-turn 50Ω pot connected between VREF - and ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0-to-1 transition occurs. If VlN for the first transition is greater than the theoretical, then the 50Ω pot should be connected between VREF - and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim In general, the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the op amp. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, V lN should be set to the 255 to overflow transition. That voltage is1/3 LSB less than VREF + and is calculated as follows: VlN (255 to 256 transition) = VREF - VREF /512 = VREF (511/512). To perform the gain trim, first do the offset trim and then apply the required VlN for the 255 to overflow transition. Now adjust VREF + until that transition occurs on the outputs. CA3318
spectral components below the Nyquist frequency excluding DC. components to the RMS value of the measured input signal. FIGURE 13. USING TWO CA3318s FOR 9-BIT RESOLUTION
Most power is consumed while in the auto-balance state. When operating at lower than 15MHz clock speed, power can be reduced by stretching the sample (φ2) time. The con- straints are a minimum balance time (φ1) of 33ns, and a maximum sample time of 500ns. Longer sample times cause droop in the auto-balance capacitors. Power can also be reduced in the reference string by switching the reference on only during auto-balance. Clock Input The Clock and Phase inputs feed buffers referenced to V AA + and VAA -. Phase should be tied to one of these two poten- tials, while the clock (if DC coupled) should be driven at least from 0.2 to 0.7 x (V AA + - VAA -). The clock may also be AC coupled with at least a 1VP-P swing. This allows TTL drive levels or 5V QMOS levels when VAA + is greater than 5V. TABLE 1. OUTPUT CODE TABLE (NOTE 1) INPUT VOLTAGE BINARY OUTPUT CODE DECIMAL COUNT VREF 6.40V (V) VREF 5.12V (V) OF MSB B8 B7 B6 B5 B4 B3 B2 LSB Zero 0.00 0.00 000000000 0 1 LSB 0.025 0.02 000000001 1 2 LSB 0.05 0.04 000000010 2 1/4 Full Scale 1.60 1.28 001000000 6 4 1/2 Full Scale - 1 LSB 3.175 2.54 001111111 1 2 7 1/2 Full Scale 3.20 2.56 010000000 1 2 8 1/2 Full Scale + 1 LSB 3.225 2.58 010000001 1 2 9 3/4 Full Scale 4.80 3.84 011000000 1 9 2 Full Scale - 1 LSB 6.35 5.08 011111110 2 5 4 Full Scale 6.375 5.10 011111111 2 5 5 Over Flow 6.40 5.12 111111111 5 1 1 NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. CA3318 All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com