CA3310 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 15

Technical content

Features

  • Built-In Track and Hold
  • Rail-to-Rail Input Range
  • Latched Three-state Output Drivers
  • Microprocessor-Compatible Control Lines
  • Internal or External Clock

Applications

  • Fast, No-Droop, Sample and Hold
  • Voice Grade Digital Audio
  • DSP Modems
  • Remote Low Power Data Acquisition Systems
  • µP Controlled Systems

Description

The Intersil CA3310 is a fast, low power, 10-bit successive approximation analog-to-digital converter, with microprocessor- compatible outputs. It uses only a single 3V to 6V supply and typically draws just 3mA when operating at 5V. It can accept full rail-to-rail input signals, and features a built-in track and hold. The track and hold will follow high bandwidth input signals, as it has only a 100ns (typical) input time constant. The ten data outputs feature full high-speed CMOS three- state bus driver capability, and are latched and held through a full conversion cycle. Separate 8 MSB and 2 LSB enables, a data ready flag, and conversion start and ready reset inputs complete the microprocessor interface. An internal, adjustable clock is provided and is available as an output. The clock may also be driven from an external source. Pinout CA3310, CA3310A (PDIP, SBDIP, SOIC) TOP VIEW

Ordering Information

(INL, DNL) TEMP. RANGE (oC) PACKAGE PKG. NO. CA3310E ±0.75 LSB -40 to 85 24 Ld PDIP E24.6 CA3310AE ±0.5 LSB -40 to 85 24 Ld PDIP E24.6 CA3310M ±0.75 LSB -40 to 85 24 Ld SOIC M24.3 CA3310AM ±0.5 LSB -40 to 85 24 Ld SOIC M24.3 CA3310D ±0.75 LSB -55 to 125 24 Ld SBDIP D24.6 CA3310AD ±0.5 LSB -55 to 125 24 Ld SBDIP D24.6 D0 (LSB) D9 (MSB) DRDY VSS (GND) VDD VREF + R EXT CLK STRT VAA + OEL OEM DRST VIN VREF - VAA - File Number 3095.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

C 16C C C 31 C VDD VSS VIN VREF + VAA + VAA - VREF - ALL LOGIC 50Ω SUBSTRATE RESISTANCE 10-BIT SUCCESSIVE APPROXIMATION REGISTER 10-BIT EDGE TRIGGERED “D” LATCH CONTROL AND TIMING CLOCK CLK CLR Q STRT R EXT CLK DRDY DRST OEM D9 (MSB) D0 (LSB) OEL CA3310, CA3310A

Typical Application Schematics INPUT RANGE R1 R2 R3 R4 R5 0V TO 5V 4.99K 4.53K OPEN 4.99K 4.53K 0V TO 10V 10K 4.53K OPEN 10K 4.53K -5V TO +5V 10K 9.09K 9.09K 10K 4.53K +5V SUPPLY 0.1µF CER D STAR T CONVERSA TION RESET FLA G HIGH BYTE ENABLE LO W BYTE ENABLE OUTPUT DATA DATA READY FLAG 2MHz CLOCK NC AD D ADJUST 100-1V A 0.1 VDD STRT DRST OEM OEL D0 - D9 DRDY CLK R EXT VSS VAA + VREF + CA3310/A VREF - VAA - VIN 47pFR510K CA3140 ICL7663S 4 5 A A R2 R3 ADJUST GAIN 100Ω ±10% 4.5V 75V 28.7K A 100 +8V OPTIONAL VDD VIN TO +15V CLAMP A A0.1 A +4.7µF TAN A A 4.7µF TAN UNLESS NOTED, ALL RESISTORS = 1% METAL FILM, POTS = 10 TURN, CERMET D = DIGITAL GROUND A = ANALOG GROUND TO -15V OFF SET CA3310, CA3310A

Absolute Maximum Ratings Thermal Information DC Input Current or Output (Protection Diode) Operating Conditions Temperature Range (TA) Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, VDD = VAA + = 5V, VREF + = 4.608V, VSS = VAA - = VREF - = GND, CLK = External 1MHz, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ACCURACY (See Text For Definitions) Resolution 10 - - Bits Differential Linearity Error CA3310 - ±0.5 ±0.75 LSB CA3310A - ±0.25 ±0.5 LSB Integral Linearity Error CA3310 - ±0.5 ±0.75 LSB CA3310A - ±0.25 ±0.5 LSB Gain Error CA3310 - ±0.25 ±0.5 LSB CA3310A - - ±0.25 LSB Offset Error CA3310 - ±0.25 ±0.5 LSB CA3310A - - ±0.25 LSB ANALOG OUTPUT Input Resistance In Series with Input Sample Capacitors - 330 - Ω Input Capacitance During Sample State - 300 - pF Input Capacitance During Hold State - 20 - pF Input Current At V IN = VREF + = 5V - - +300 µA At VIN = VREF - = 0V - - -100 µA Static Input Current STRT = V+, CLK = V+ At VIN = VREF + = 5V --1 µA At VIN = VREF - = 0V - - -1 µA Input + Full-Scale Range (Note 2) V REF - +1 - V DD +0.3 V Input - Full-Scale Range (Note 2) V SS -0.3 - V REF + -1 V Input Bandwidth From Input RC Time Constant - 1.5 - MHz DIGITAL INPUTS DRST, OEL, OEM, STRT, CLK High-Level Input Voltage Over V DD = 3V to 6V (Note 2) 70 - - % of VDD Low-Level Input Voltage Over V DD = 3V to 6V (Note 2) - - 30 % of VDD Input Leakage Current Except CLK - - ±1 µA Input Capacitance (Note 2) - - 10 pF Input Current CLK Only (Note 2) - - ±400 µA CA3310, CA3310A

DIGITAL OUTPUTS D0 - D9, DRDY High-Level Output Voltage I SOURCE = -4mA 4.6 - - V Low-Level Output Voltage I SINK = 6mA - - 0.4 V Three-State Leakage Except DRDY - - ±1 µA Output Capacitance Except DRDY (Note 2) - - 20 pF CLK OUTPUT High-Level Output Voltage I SOURCE = 100µA (Note 2) 4 - - V Low-Level Output Voltage I SlNK = 100µA (Note 2) - - 1 V TIMING Clock Frequency Internal, CLK and R EXT Open 200 300 400 kHz Internal, CLK Shorted to REXT 600 800 1000 kHz External, Applied to CLK (Note 2)(Max) - 4 2 MHz (Min) 100 10 - kHz Clock Pulse Width, tLOW , tHIGH External, Applied to CLK: See Figure 1 (Note 2) 100 - - ns Conversion Time Internal, CLK Shorted to R EXT 13 - - µs Aperture Delay, tD APR See Figure 1 - 100 - ns Clock to Data Ready Delay, tD1 DRDY See Figure 1 - 150 - ns Clock to Data Ready Delay, tD2 DRDY See Figure 1 - 250 - ns Clock to Data Delay, tD Data See Figure 1 - 200 - ns Start Removal Time, tR STRT See Figures 3 and 4 (Note 1) - -120 - ns Start Setup Time, tSU STRT See Figure 4 - 160 - ns Start Pulse Width, tW STRT See Figures 3 and 4 - 10 - ns Start to Data Ready Delay, tD3 DRDY See Figures 3 and 4 - 170 - ns Clock Delay from Start, tD CLK See Figure 3 - 200 - ns Ready Reset Removal Time, tR DRST See Figure 50 (Note 1) - -80 - ns Ready Reset Pulse Width, tW DRST See Figure 5 - 10 - ns Ready Reset to Data Ready Delay, tD4 DRDY See Figure 5 - 35 - ns Output Enable Delay, tEN See Figure 2 - 40 - ns Output Disable Delay, tDIS See Figure 2 - 50 - ns SUPPLIES Supply Operating Range, V DD or VAA (Note 2) 3 - 6 V Supply Current, IDD + IAA See Figures 14, 15 - 3 8 mA Supply Standby Current Clock Stopped During Cycle 1 - 3.5 - mA Analog Supply Rejection At 120Hz, See Figure 13 - 25 - mV/V Reference Input Current See Figure 10 - 160 - µA TEMPERATURE DEPENDENCY Offset Drift At 0 to 1 Code Transition - -4 - µV/ oC Gain Drift At 1022 to 1023 Code Transition - -6 - µV/oC Internal Clock Speed See Figure 7 - -0.5 - %/ oC NOTES: 1. A (-) removal time means the signal can be removed after the reference signal. 2. Parameter not tested, but guaranteed by design or characterization. Electrical SpecificationsTA = 25oC, VDD = VAA + = 5V, VREF + = 4.608V, VSS = VAA - = VREF - = GND, CLK = External 1MHz, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CA3310, CA3310A

FIGURE 14. SUPPLY CURRENT vs CLOCK FREQUENCY FIGURE 15. SUPPLY CURRENT vs TEMPERATURE TABLE 1. PIN DESCRIPTIONS 1-10 D0 - D9 Three-State outputs for data bits representing 20 (LSB) through 29 (MSB). conversion started. Also reset asynchronously by DRST. 13 DRST Active low input, resets DRDY. 14 OEM Active low input, three-state enable of D2 - D9. 15 OEL Active low input, three-state enable of D0, D1. 18 V REF - Reference input voltage, sets 0 code (-) end of input range. 19 STRT Active Low Start Conversion Input. Recognized after end of clock period 13. 20 CLK Clock input or output. Conversion functions are synchronous to high-going edge. EXT Clock adjust input when using internal clock. 22 V REF + Reference input voltage, set 1023 code (+) end of input range. TABLE 2. OUTPUT CODES

  1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.

AND R EXT = OPEN OR SHORTED.

operational amplifier isolates digital and analog grounds. the conversion cycle. Figure 21 illustrates this application. be complete, and DRDY will go active. DD -V SS to exceed the absolute maximum rating. when the power supply is off. VSS , whichever is appropriate. devices by exceeding the maximum device dissipation. FIGURE 20. DIGITAL TRACK-AND-HOLD BLOCK DIAGRAM

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CA3310, CA3310A