CA3304

CA3304 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• CMOS/SOS Low Power with Video Speed (Typ) . . 25mW
• Parallel Conversion Technique
• 25MHz Sampling Rate (40ns Conversion Time) at 5V Supply
• 4-Bit Latched Three-State Output with Overflow and Data Change Outputs 1/8 LSB Maximum Nonlinearity (A Version)
• Inherent Resistance to Latch-Up Due to SOS Process
• Bipolar Input Range with Optional Second Supply

Applications

• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
• RSSI Circuits

Description

The Intersil CA3304 is a CMOS parallel (FLASH) analog-to- digital converter designed for applications demanding both low-power consumption and high speed digitization. Digitiz- ing at 25MHz, for example, requires only about 35mW. The CA3304 operates over a wide, full-scale signal input voltage range of 0.5V up to the supply voltage. Power consumption is as low as 10mW, depending upon the clock frequency selected. The intrinsic high conversion rate makes the CA3304 types ideally suited for digitizing high speed signals. The overflow bit makes possible the connection of two or more CA3304s in series to increase the resolution of the conversion system. A series connection of two CA3304s may be used to pro- duce a 5-bit, 25MHz converter. Operation of two CA3304s in parallel doubles the conversion speed (i.e., increases the sampling rate from 25MHz to 50MHz). A data change pin indicates when the present output differs from the previous, thus allowing compaction of data storage. Sixteen paralleled auto-balanced voltage comparators mea- sure the input voltage with respect to a known reference to produce the parallel-bit outputs in the CA3304. Fifteen com- parators are required to quantize all input voltage levels in this 4-bit converter, and the additional comparator is required for the overflow bit.

Ordering Information

CA3304 (SBDIP, PDIP, SOIC) TOP VIEW PART NUMBER LINEARITY (INL, DNL) SAMPLING RATE TEMP. RANGE ( oC) PACKAGE PKG. NO. CA3304E ±0.25 LSB 25MHz (40ns) -40 to 85 16 Ld PDIP E16.3 CA3304AE ±0.125 LSB 25MHz (40ns) -40 to 85 16 Ld PDIP E16.3 CA3304M ±0.25 LSB 25MHz (40ns) -40 to 85 16 Ld SOIC (W) M16.3 CA3304AM ±0.125 LSB 25MHZ (40ns) -40 to 85 16 Ld SOIC (W) M16.3 CA3304D ±0.25 LSB 25MHz (40ns) -55 to 125 16 Ld SBDIP D16.3 CA3304AD ±0.125 LSB 25MHz (40ns) -55 to 125 16 Ld SBDIP D16.3 BIT 1 (LSB) BIT 2 BIT 3 BIT 4 DATA CHANGE (DC) OVERFLOW (OF) V SS CE2 VDD VAA - VREF - VREF + VIN VAA + CE1 CLK File Number 1790.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD or VAA +) (Voltage Referenced to VSS or VAA - Terminal, Input Voltage Range Operating Conditions Operating Temperature Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC Maximum Storage Temperature Range (TSTG ) . . . -65oC to 150oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, VREF + = 2V, VDD = VAA + = 5V, VAA - = VREF - = VSS = GND, fCLK = 25MHz Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution 4 - - Bits Input Errors Integral Linearity Error CA3304A - ±0.1 ±0.125 LSB CA3304 - ±0.125 ±0.25 LSB Differential Linearity Error CA3304A - ±0.1 ±0.125 LSB CA3304 - ±0.125 ±0.25 LSB Offset Error (Unadjusted) CA3304A - - ±0.75 LSB CA3304 - - ±1.0 LSB Gain Error (Unadjusted) CA3304A - - ±0.75 LSB CA3304 - - ±1.0 LSB DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB Below Full Scale) Conversion Timing Aperture Delay - 3 - ns Signal to Noise Ratio, SNR RMS Signal RMS Noise f S = 25MHz, fIN = 100kHz - 23.7 - dB fS = 25MHz, fIN = 5MHz - 23.6 - dB Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion fS = 25MHz, fIN = 100kHz - 23.4 - dB fS = 25MHz, fIN = 5MHz - 22.8 - dB Total Harmonic Distortion, THD f S = 25MHz, fIN = 100kHz - -34.5 - dBc fS = 25MHz, fIN = 5MHz - -31.0 - dBc Effective Number of Bits, ENOB f S = 25MHz, fIN = 100kHz - 3.67 - Bits fS = 25MHz, fIN = 5MHz - 3.57 - Bits ANALOG INPUTS Input Range Full Scale Input Range (Notes 1, 4) 0.5 - V AA V Input Loading Input Capacitance - 10 - pF Input Current V IN = 2V (Note 2) - 150 200 µA CA3304, CA3304A

Allowable Input Bandwidth (Note 4) - 25 f CLK /2 MHz -3dB Input Bandwidth - 40 - MHz REFERENCE INPUTS Input Range V REF + Range (Note 4) V AA - +0.5 - V AA +V VREF - Range (Note 4) V AA -- V AA + -0.5 V Input Loading Resistor Ladder Impedance V IN = 5V, CLK = Low 640 - 960 Ω DIGITAL INPUTS Digital Input Maximum V IN, Low CLOCK (Notes 3, 4) - - 0.3 x V AA V CE1, CE2 (Note 4) - - 0.3 x V DD V Minimum VIN, High CLOCK (Notes 3, 4) 0.7 x V AA -- V CE1, CE2 (Note 4) 0.7 x V DD -- V Input Leakage, Except CLK V = 0V, 5V - - ±1 µA Input Leakage, CLK (Note 3) - ±100 ±150 µA DIGITAL OUTPUTS Digital Outputs Output Low (Sink) Current V O = 0.4V 6 - - mA Output High (Source) Current V O = 4.6V -3 - - mA Three-State Leakage Current V O = 0V, 5V - ±0.2 ±5 µA TIMING CHARACTERISTICS Conversion Timing Maximum Conversion Speed CLK = Square Wave 25 35 - MSPS Auto-Balance Time ( φ1) 20 - - ns Sample Time (φ2) 20 - 5000 ns Output Timing Data Valid Delay (Note 4) - 30 40 ns Data Hold Time (Note 4) 15 25 - ns Output Enable Time - 15 - ns Output Disable Time - 10 - ns POWER SUPPLY CHARACTERISTICS Device Current, I AA Continuous Clock - 5.5 - mA Continuous φ2 - 0.4 - mA Continuousφ1- 2 - m A Device Current, IDD Continuous Clock - 1.5 - mA VAA + = 5V, VSS =CE1 = VAA - = CLK = GND Continuousφ2- 5 1 0 m A VAA + = 7V Continuous φ1- 5 2 0 m A NOTES: 1. Full scale input range, VREF + - VREF -, may be in the range of 0.5V to VAA + -VAA - volts. Linearity errors increase at lower full scale ranges, however. 2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD voltage. 3. The CLK input is a CMOS inverter with a 50kΩ feedback resistor. It operates from the VAA + and VAA - supplies. It may be AC-coupled with a 1VP-P minimum source. 4. Parameter not tested, but guaranteed by design or characterization. Electrical SpecificationsTA = 25oC, VREF + = 2V, VDD = VAA + = 5V, VAA - = VREF - = VSS = GND, fCLK = 25MHz Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CA3304, CA3304A

PIN NUMBER NAME DESCRIPTION 1 Bit 1 Bit 1 (LSB). Output Data Bits (High = True) 2 Bit 2 Bit 2. 3 Bit 3 Bit 3. 4 Bit 4 Bit 4 (MSB). 5 DC Data Change. 6 OF Overflow. 7 CE2 Three-State Output Enable Input, active low. See the Chip Enable Truth Table. SS Digital Ground. 9 CE1 Three-State Output Enable Input, active high. See the Chip Enable Truth Table. 10 V AA + Analog Power Supply, +5V. 11 V IN Analog Signal Input. 12 V REF + Reference Voltage Positive Input. 13 V REF - Reference Voltage Negative Input. 14 V AA - Analog Ground. 15 CLK Clock Input. 16 V DD Digital Power Supply, +5V. CHIP ENABLE TRUTH TABLE CE1 CE2 BIT 1 - BIT 4 DC, OF 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State X = Don't Care TABLE 1. OUTPUT CODE TABLE INPUT VOLTAGE (V) OUTPUT CODE DECIMAL COUNT V REF + = 1V VREF - = -1V 1.6V 3.2V 4.8V 0V OF B4 B3 B2 B1 Zero -1.000 0 0 0 0 00000 0 1/2 Full Scale 0 0.8 1.000 1.6 2.4 01000 8 NOTE: 1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer Curve Figure 6. The output code should exist for an input equal to the ideal center voltage± 1/2 of the step size. CA3304, CA3304A

A sequential parallel technique is used by the CA3304 converter to obtain its high speed operation. The sequence consists of the “Auto Balance” phase and the “Sample Unknown” phase (Refer to the circuit diagram). Each conversion takes one clock cycle (see Note). The “Auto Balance” (φ1) occurs during the Low period of the clock cycle, and the “Sample Unknown” (φ2) occurs during the High period of the clock cycle. NOTE: This device requires only a single-phase clock. The terminology ofφ1 andφ2 refers to the High and Low periods of the same clock. During the “Auto Balance” phase, a transmission-gate switch is used to connect each of 16 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: V TAP (N) = [(VREF /16) x N] - [VREF /(2 x 16)] Where: VTAP (N) = Reference ladder tap voltage at point N, VREF = Voltage across VREF - to VREF +, and N = Tap number (1 through 16). The other side of the capacitor is connected to a single- stage inverting amplifier whose output is shorted to its input by a switch. This biases the amplifier at its intrinsic trip point, which is approximately (V DD - VSS )/2. The capacitors now charge to their associated tap voltages, priming the circuit for the next phase. In the “Sample Unknown” phase, all ladder tap switches are opened, the comparator amplifiers are no longer shorted, and V IN is switched to all 16 capacitors. Since the other end of the capacitor is now looking into an effectively open cir- cuit, any voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators whose tap voltages were lower than V IN will drive the comparator outputs to a “low” state. All compara- tors whose tap voltages were higher than V IN will drive the comparator outputs to a “high” state. A second, capacitor- coupled, auto-zeroed amplifier further amplifies the outputs. The status of all these comparator amplifiers are stored at the end of this phase (φ2), by a secondary latching amplifier stage. Once latched, the status of the 16 comparators is decoded by a 16 to 5 bit decode array and the results are clocked into a storage register at the rising edge of the nextφ2. If the input is greater than 31/32 x V REF , the overflow output will go “high”. (The bit outputs will remain high). If the output differs from that of the previous conversion, the data change output will go “high”. A three-state buffer is used at the output of the 7 storage registers which are controlled by two chip-enable signals. CE1 will independently disable B1 through B4 when it is in a high state. CE2 will independently disable B1 through B4 and the OF and DC buffers when it is in the low state. Continuous Clock Operation One complete conversion cycle can be traced through the CA3304 via the following steps. (Refer to timing diagram Figure 3). The rising edge of the clock input will start a “sample” phase. During this entire “High” state of the clock, the 16 comparators will track the input voltage and the 16 latches will track the comparator outputs. At the falling edge of the clock, all 16 comparator outputs are captured by the 16 latches. This ends the “sample” phase and starts the “auto balance” phase for the comparators. During this “Low” state of the clock the output of the latches propagates through the decode array and a 6-bit code appears at the D inputs of the output registers. On the next rising edge of the clock, this 6-bit code is shifted into the output registers and appears with time delay t D as valid data at the output of the three-state drivers. This also marks the start of a new “sample” phase, thereby repeating the conversion process for this next cycle. Pulse Mode Operation For sampling high speed nonrecurrent or transient data, the converter may be operated in a pulse mode in one of three ways. The fastest method is to keep the converter in the Sample Unknown phase,φ2, during the standby state. The device can now be pulsed through the Auto Balance phase with as little as 20ns. The analog value is captured on the leading edge ofφ1 and is transferred into the output registers on the trailing edge ofφ1. We are now back in the standby state,φ2, and another conversion can be started within 20ns, but not later than 5µs due to the eventual droop of the commutating capacitors. Another advantage of this method is that it has the potential of having the lowest power drain. The larger the time ratio betweenφ2 and φ1, the lower the power consumption. (See Timing Diagram Figure 3A). The second method uses the Auto Balance phase,φ1, as the standby state. In this state the converter can stay indefinitely waiting to start a conversion. A conversion is performed by strobing the clock input with twoφ2 pulses. The first pulse starts a Sample Unknown phase and captures the analog value in the comparator latches on the trailing edge. A secondφ2 pulse is needed to transfer the date into the output registers. This occurs on the leading edge of the second pulse. The conversion now takes place in 40ns, but the repetition rate may be as slow as desired. The disadvantage to this method is the slightly higher device dissipation due to the low ratio ofφ2 to φ1. (See Timing Diagram Figure 3B). For applications requiring both indefinite standby and lowest power, standby can be in theφ2 (Sample Unknown) state with twoφ1 pulses to generate valid data (see Figure 3C). The conversion process now takes 60ns. [Note that the above numbers do not include the t D (Output Delay) time.] Increased Accuracy In most case the accuracy of the CA3304 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, two adjustments can be made to obtain better accuracy; i.e., offset trim and gain trim. CA3304, CA3304A

In general offset correction can be done in the preamp circuitry by introducing a DC shift to VIN or by the offset trim of the op amp. When this is not possible the VREF - input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equation is as follows: VIN (0 to 1 transition) =1/2 LSB =1/2(VREF /16) = VREF /32. Adjust offset by applying this input voltage and adjusting the VREF - voltage or input amplifier offset until an output code alternating between 0 and 1 occurs. Gain Trim In general the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the op amp. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, V IN should be set to the 15 to overflow transition. That voltage is1/2 LSB less than VREF + and is calculated as follows: VlN (15 to 16 transition) = VREF - VREF /32 = VREF (31/32). To perform the gain trim, first do the offset trim and then apply the required VIN for the 15 to overflow transition. Now adjust VREF + until that transition occurs on the outputs. Layout, Input And Supply Considerations The CA3304 should be mounted on a ground-planed, printed-circuit board, with good high-frequency decoupling capacitors mounted as close as possible. If the supply is noisy, decouple V AA + with a resistor as shown in Figure 12A. The CA3304 outputs current spikes to its input at the start of the auto-balance and sample clock phases. A low impedance source, such as a locally-terminated 50Ω coax cable, should be used to drive the input terminal. A fast- settling buffer such as the HA-5033, HA-5242, or CA3450 should be used if the source is high impedance. The V REF terminals also have current spikes, and should be well bypassed. Care should be taken to keep digital signals away from the analog input, and to keep digital ground currents away from the analog ground. If possible, the analog ground should be connected to digital ground only at the CA3304. Bipolar Operation The CA3304, with separate analog (V AA +, VAA -) and digital (VDD , VSS ) supply pins, allows true bipolar or negative input operation. The VAA - pin may be returned to a negative supply (observing maximum voltage ratings to VAA + or VDD and recommended rating to VSS ), thus allowing the VREF - potential also to be negative. Figure 12B shows operation with an input range of -1V to +1V. Similarly, V AA + and VREF + could be maintained at a higher voltage than VDD , for an input range above the digital supply. Digital Input And Output Levels The clock input is a CMOS inverter operating from and with logic input levels determined by the VAA supplies. If VAA + or VAA - are outside the range of the digital supplies, it may be necessary to level shift the clock input to meet the required 30% to 70% of V AA input swing. Figure 12B shows an exam- ple for a negative VAA -. An alternate way of driving the clock is to capacitively couple the pin from a source of at least 1VP-P. An internal 50kΩ feedback resistor will keep the DC level at the intrinsic trip point. Extremely non-symmetrical clock waveforms should be avoided, however. The remaining digital inputs and outputs are referenced to V DD and VSS . If TTL or other lower voltage sources are to drive the CA3304, either pull-up resistors or CD74HCT series “QMOS” buffers are recommended. 5-Bit Resolution To obtain 5-bit resolution, two CA3304s can be wired together. Necessary ingredients include an open-ended ladder net- work, an overflow indicator, three-state outputs, and chip- enable controls - all of which are available on the CA3304. The first step for connecting a 5-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 13. Since the absolute-resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. The overflow output of the lower device now becomes the fifth bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overflow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D converter. The three-state outputs of the two devices (bits 1 through 4) are now connected in parallel to complete the circuitry. Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the CA3304. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the fre- quency domain with a 4096 point FFT and analyzed to evalu- ate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. Signal-to-Noise (SNR) SNR is the measured RMS signal to RMS noise at a speci- fied input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamen- tal and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. CA3304, CA3304A