CA3290 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • MOSFET Input Stage - Wide Common Mode Input Voltage Range (V ICR) Can Be Swung 1.5V (Typ) Below Negative Supply Voltage Rail - Virtually Eliminates Errors Due to Flow of Input Currents
  • Output Voltage Compatible with TTL, DTL, ECL, MOS, and CMOS Logic Systems in Most Applications

Applications

  • High Source Impedance Voltage Comparators
  • Long Time Delay Circuits
  • Square Wave Generators
  • A/D Converters
  • Window Comparators Schematic Diagram (ONLY ONE IS SHOWN) OUTPUT (A 1) INV. INPUT (A1) NON-INV. INPUT (A1) OUTPUT (A 2) INV. INPUT (A2) NON-INV. INPUT (A2) A 1 A 2

Ordering Information

RANGE ( oC) PACKAGE PKG. NO. CA3290AE -55 to 125 8 Ld PDIP E8.3 CA3290E -55 to 125 8 Ld PDIP E8.3 D 1 +V I -VI D 2 Q 9 Q 10 Q 11 Q 12 Q 2 Q 3 Q 5 Q 6 D 3 D 4 Q 4 COMPARATOR NO. 1 Q 7 VO Q 1 BIASING CIRCUIT FOR CURRENT SOURCES TO COMP. NO. 2 R 1 100kΩ Q 8 Q 15 Q 13 Q 14 Q 16 Q 17 Q 18 R 2 1kΩ R 3 5kΩ C 1 5pF 50µA 100 µA5 0 µA 100µA Data Sheet September 1998 File Number 1049.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Copyright © Intersil Corporation 1999

Absolute Maximum Ratings Thermal Information Supply Voltage (whichever is less) Operating Conditions Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuits from the output to V+ can cause excessive heating and eventual destruction of the device. 2. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsV- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TEMP (oC) CA3290A CA3290 UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO VCM = VO = 1.4V, V+ = 5V Full - 4.5 - - 8.5 - mV VCM = VO = 0V, V+ =+15V, V- = -15V Full - 8.5 - - 8.5 - mV VCM = VO = 1.4V, V+ = 5V 25 - 4.0 10 - 7.5 20 mV VCM = VO = 0V, V+ = +15V, V- = -15V 25 - 4.0 10 - 7.5 20 mV Temperature Coefficient of Input Offset Voltage ∆VIO/∆T- 8 - - 8 - µV/oC Input Offset Current I IO VCM = 1.4V, V+ = 5V Full - 2 28 - 2 32 nA VCM = 0V, V+ = +15V, V- = -15VFull - 7 28 - 7 32 nA VCM = 1.4V, V+ = 5V 25 - 2 25 - 2 30 pA VCM = 0V, 25 - 7 25 - 7 30 pA Input Current I I VCM = 1.4V, V+ = 5V 125 - 2.8 45 - 2.8 55 nA VCM = 0V, V+ = +15V, V- = -15V 125 - 13 45 - 13 55 nA VCM = 1.4V, V+ = 5V 25 - 3.5 40 - 3.5 50 pA VCM = 0V, V+ = +15V, V- = -15V 25 - 12 40 - 12 50 pA Supply Current I+ R L =∞ , V+ = 5V -55 - 0.85 1.0 - 0.85 1.6 mA R L =∞ , V+ = 30V 25 - 1.35 3.0 - 1.35 3.0 mA Voltage Gain A OL R L = 15kΩ , V+ =+15V, V- = -15V Full - 150 - - 150 - V/mV - 103 - - 103 - dB R L = 15kΩ , V+ = +15V, V- = -15V 25 25 800 - 25 800 - V/mV 88 118 - 88 118 - dB CA3290, CA3290A

FIGURE 1. PARASITIC OSCILLATIONS TEST CIRCUIT AND WAVEFORMS

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Metallization Mask Layout The photographs and dimensions of each chip represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57 o instead of 90o with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10 -3 inch) NOTE: Numbers in pads are for 8 lead DIP and TO-5 Can and numbers outside of chip are for 14 lead DIP . 0 1 02 03 0 4 05 0 5 3 4 - 10 (0.102 - 0.254) 50 - 58 (1.270 - 1.473) 87 - 95 (2.210 - 2.403) CA3290, CA3290A