CA3280 RENESAS | Alldatasheet
Document overview
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- PDF pages: 10
Technical content
Features
- Low Initial Input Offset Voltage: 500V (Max) (CA3280A)
- Low Offset Voltage Change vs IABC: <500V (Typ) for All Types
- Low Offset Voltage Drift: 5V/oC (Max) (CA3280A)
- Excellent Matching of the Two Amplifiers for All Characteristics
- Internal Current-Driven Linearizing Diodes Reduce the External Input Current to an Offset Component
Applications
- Voltage Controlled Amplifiers
- Voltage Controlled Oscillators
- Multipliers
- Demodulators
- Sample and Hold
- Instrumentation Amplifiers
- Function Generators
- Triangle Wave-to-Sine Wave Converters
- Comparators
- Audio Preamplifier Functional Diagram PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CA3280AE -55 to 125 16 Ld PDIP E16.3 CA3280E 0 to 70 16 Ld PDIP E16.3 ID, A1 EMITTER, A1 IABC, A1 NC IABC, A2 ID, A2 EMITTER, A2 +IN, A1 V+, A1 OUT, A1 OUT, A2 V+, A2 -IN, A2 +IN, A2 -IN, A1 +A1 2K 2K 1/2 CA3280
CA3280, CA3280A FN1174 Rev 6.00 Page 2 of 10 May 2002 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. Short circuit may be applied to ground or to either supply. Electrical Specifications For Equipment Design, at TA = 25oC, VSUPPLY= 15V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA3280 CA3280A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO IABC = 1mA - - 3 - - 0.5 mV IABC = 100A - 0.7 3 - 0.25 0.5 mV IABC = 10A- - 3 - - 0 . 5 m V IABC = 1mA to 10A, TA = Full Temp. Range - 0.8 4 - 0.8 1.5 mV Input Offset Voltage Drift | VIO|I ABC = 1A to 1mA - 0.5 1 - 0.5 1 mV IABC = 100A, TA = Full Temperature Range -5- - 3 5 V/oC Amplifier Bias Voltage V ABC IABC = 100A- 1 . 2 - - 1 . 2 - V Peak Output Voltage V OM+I ABC = 500A 12 13.7 - 12.5 13.7 - V VOM+I ABC = 5A 12 13.9 - 12.5 13.9 - V Common Mode Input Voltage Range VICR IABC = 100A- 1 3 - 1 3 - 1 3 - 1 3 V Noise Voltage e N IABC = 500A 10Hz - 20 - - 20 - nV/ Hz 1kHz - 8 - - 8 - nV/ Hz 10kHz - 7 - - 7 - nV/ Hz Input Offset Current I IO IABC = 500A -Z 0.3 0.7 - 0.3 0.7 A Input Bias Current I IB IABC = 500A- 1 . 8 5 - 1 . 8 5 A IABC = 500A, TA = Full Temperature Range -38 - 3 8 A
CA3280, CA3280A FN1174 Rev 6.00 Page 3 of 10 May 2002 Peak Output Current I OM+I ABC = 500A Source 350 410 650 350 410 650 A IOM- Sink -350 -410 -650 -350 -410 -650 A IOM+I ABC = 5A Source 3 4.1 7 3 4.1 7 A Peak Output Current Sink and Source IOM-, IOM+ IABC = 500A, TA = Full Temperature Range 350 450 550 350 450 550 A Linearization Diodes I D = 100A - 10 - - 10 - A Offset Current I D = 10A- 0 . 5 1 - 0 . 5 1 A Dynamic Impedance I D = 100A - 700 - - 700 - Diode Network Supply Current I ABC = 100A 250 400 800 250 400 800 A Amplifier Supply Current (Per Amplifier) I+ I ABC = 500A- 2 2 . 4 - 2 2 . 4 m A Amplifier Output Leakage Current I OL IABC = 0, VO = 0V - 0.015 0.1 - 0.015 0.1 nA IABC = 0, VO = 30V - 0.15 1 - 0.15 1 nA Common Mode Rejection Ratio CMRR I ABC = 100A 80 100 - 94 100 - dB Power Supply Rejection Ratio PSRR I ABC = 100A 86 105 - 94 105 - dB Open Loop Voltage Gain A OL IABC = 100A, RL = VO = 20VP-P 94 100 - 94 100 - dB 50 100 - 50 100 - kV/V Forward Transconductance G M IABC = 50A, Large Signal - 0.8 1.2 - 0.8 1.2 mS gM IABC = 1mA, Small Signal - 16 22 - 16 22 mS Input Resistance R I IABC = 10A0 . 5 - - 0 . 5 - - M Channel Separation f = 1kHz - 94 - - 94 - dB Open Loop Total Harmonic Distortion THD f = 1kHz, I ABC = 1.5mA, RL = 15k, VO = 20VP-P Bandwidth f T IABC = 1mA, RL = 100 -9- - 9 - M H z Slew Rate, Open Loop SR I ABC = 1mA - 125 - - 125 - V/ s Capacitance C I IABC = 100A Input - 4.5 - - 4.5 - pF CO Output - 7.5 - - 7.5 - pF Output Resistance R O IABC = 100A - 63 - - 63 - M Electrical Specifications For Equipment Design, at TA = 25oC, VSUPPLY= 15V, Unless Otherwise Specified (Continued) (Continued) PARAMETER SYMBOL TEST CONDITIONS CA3280 CA3280A UNITSMIN TYP MAX MIN TYP MAX
FIGURE 23. SUPPLY CURRENT vs AMPLIFIER BIAS CURRENT FIGURE 24. INP UT BIAS CURRENT vs AMPLIFIER BIAS
FN1174 Rev 6.00 Page 10 of 10 May 2002 CA3280, CA3280A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93