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Document overview

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Technical content

Features

  • MOSFET Input Stage provides - Very High ZI = 1.5T (1.5 x 1012) (Typ)
  • Ideal for Single Supply Applications
  • Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail
  • CMOS Output Stage Permits Signal Swing to Either (Or Both) Supply Rails
  • Pb-Free Available (RoHS Compliant)

Applications

  • Ground Referenced Single Supply Amplifiers
  • Fast Sample-Hold Amplifiers
  • Long Duration Timers/Monostables
  • Ideal Interface with Digital CMOS
  • High Input Impedance Wideband Amplifiers
  • Voltage Followers (e.g. Follower for Single Supply D/A Converter)
  • Voltage Regulators (Permits Control of Output Voltage Down to 0V)
  • Wien Bridge Oscillators
  • Voltage Controlled Oscillators
  • Photo Diode Sensor Amplifiers Pinout CA3260, CA3260A (8 LD PDIP) TOP VIEW

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA3260E CA3260E -55 to +125 8 Ld PDIP E8.3 CA3260EZ (Note) CA3260EZ -55 to +125 8 Ld PDIP* (Pb-free) E8.3 CA3260AE CA3260AE -55 to +125 8 Ld PDIP E8.3 CA3260AEZ (Note) 3260AEZ -55 to +125 8 Ld PDIP* (Pb-free) E8.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. NON INV. INPUT (A) OUTPUT (B) INV. INPUT (B) NON INV. INPUT (B) OUTPUT (A) A B + - +-INV. INPUT (A)

CA3260, CA3260A FN1266 Rev.7.00 Page 2 of 4 Dec 10, 2009 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) JA (°C/W) JC (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = +25°C, Typical Values Intended Only for Design Guidance. PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITSCA3260A CA3260 Input Resistance R I VS = 7.5V 1.5 1.5 T  Input Capacitance C I f = 1MHz, VS = 7.5V 4.3 4.3 pF Unity Gain Crossover Frequency f T VS = 7.5V 4 4 MHz Slew Rate SR V S = 7.5V 10 10 V/ s Transient Response Rise Time t r CL = 25pF, RL = 2k AV = +1, VS = 7.5V 0.09 0.09 µs Overshoot OS 10 10 % Settling Time (to <0.1, VIN = 4VP-P)t S CL = 25pF, RL = 2k AV = +1, VS = 7.5V 1.8 1.8 s Input Offset Voltage V IO V+ = 5V, V- = 0V 2 6 mV Input Offset Current I IO V+ = 5V, V- = 0V 0.1 0.1 pA Input Current I I V+ = 5V, V- = 0V 2 2 pA Common Mode Rejection Ratio CMRR V+ = 5V, V- = 0V 70 60 dB Large Signal Voltage Gain A OL VO = 4VP-P, RL = 20k V+ = 5V, V- = 0V 100 100 kV/V 100 100 dB Common Mode Input Voltage Range V ICR V+ = 5V, V- = 0V 0 to 2.5 0 to 2.5 V Supply Current I+ V O = 5V, RL = V+ = 5V, V- = 0V 1 1 mA Power Supply Rejection Ratio PSRR VIO/V+, V+ = 5V, V- = 0V 200 200 µV/V Electrical Specifications For Each Amplifier at TA = +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage |V IO|V S = 7.5V - 2 5 - 6 15 mV Input Offset Current |I IO|V S = 7.5V - 0.5 20 - 0.5 30 pA Input Current I I VS = 7.5V - 5 30 - 5 50 pA Large Signal Voltage Gain A OL VO = 10VP-P, RL = 10k 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB Common Mode Rejection Ratio CMRR 80 95 - 70 90 - dB

CA3260, CA3260A FN1266 Rev.7.00 Page 3 of 4 Dec 10, 2009 Schematic Diagram Common Mode Input Voltage Range VlCR 0 -0.5 to 10 0 -0.5 to 10 V Power Supply Rejection Ratio PSRR VIO/V+ V+ = 17.5V - 32 150 - 32 320 µV/V Maximum Output Voltage V OM+R L = 10k 11 13.3 - 11 13.3 - V VOM- - 0.002 0.01 - 0.002 0.01 V VOM+R L =  14.99 15 - 14.99 15 - V VOM- - 00 . 0 1- 00 . 0 1V Maximum Output Current I OM+ Source V O = 0 V 1 22 24 51 22 24 5 m A IOM- Sink V O = 15V 12 20 45 12 20 45 mA Total Supply Current I+ R L =  VO (Amplifier A) = 7.5V VO (Amplifier B) = 7.5V - 9 15.5 - 9 15.5 mA VO (Amplifier A) = 0V VO (Amplifier B) = 0V -1 . 23 -1 . 23 m A VO (Amplifier A) = 0V VO (Amplifier B) = 7.5V -5 8 . 5 -5 8 . 5 m A Input Offset Voltage Temperature Drift VIO/T- 6 - - 8 - µ V / ° C Crosstalk f = 1kHz - 120 - - 120 - dB Electrical Specifications For Each Amplifier at TA = +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 UNITSMIN TYP MAX MIN TYP MAX 200k 300k Q12 Q11 Q10 D2 D3 D4D1 Q1 Q2 Q13Q14 Q3 Q4 30pF 3 2 1 AMPLIFIER A R13 200k R14 300 Q26 Q25 Q24D7D6 D5 D8 Q15 Q16 Q20 R11 R10 Q27 Q28 Q17Q18 30pF R12 Q21 Q23 567 Q19 Q22 AMPLIFIER B 8 V+

FN1266 Rev.7.00 Page 4 of 4 Dec 10, 2009 CA3260, CA3260A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1998-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendicular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93