CA3260_06 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 3

Technical content

Features

  • MOSFET Input Stage provides - Very High Z I = 1.5TΩ (1.5 x 1012Ω) (Typ)
  • Ideal for Single Supply Applications
  • Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail
  • CMOS Output Stage Permit s Signal Swing to Either (Or Both) Supply Rails
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Ground Referenced Single Supply Amplifiers
  • Fast Sample-Hold Amplifiers
  • Long Duration Timers/Monostables
  • Ideal Interface with Digital CMOS
  • High Input Impedance Wideband Amplifiers
  • Voltage Followers (e.g. Follower for Single Supply D/A Converter)
  • Voltage Regulators (Permits Control of Output Voltage Down to 0V)
  • Wien Bridge Oscillators
  • Voltage Controlled Oscillators
  • Photo Diode Sensor Amplifiers Pinout CA3260, CA3260A (PDIP) TOP VIEW

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA3260E CA3260E -55 to 125 8 Ld PDIP E8.3 CA3260EZ (Note) CA3260EZ -55 to 125 8 Ld PDIP* (Pb-free) E8.3 CA3260AE CA3260AE -55 to 125 8 Ld PDIP E8.3 CA3260AEZ (Note) 3260AEZ -55 to 125 8 Ld PDIP* (Pb-free) E8.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. NON INV. INPUT (A) OUTPUT (B) INV. INPUT (B) NON INV. INPUT (B) OUTPUT (A) A B + - +-INV. INPUT (A) Data Sheet February 7, 2006 FN1266.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN1266.6 February 7, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W) *Pb-free PDIPs can be used for through hole wave solder process- ing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25°C, Typical Values Intended Only for Design Guidance PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITSCA3260A CA3260 Input Resistance R I VS = ±7.5V 1.5 1.5 T Ω Input Capacitance C I f = 1MHz, VS = ±7.5V 4.3 4.3 pF Unity Gain Crossover Frequency f T VS = ±7.5V 4 4 MHz Slew Rate SR V S = ±7.5V 10 10 V/ µs Transient Response Rise Time t r CL = 25pF, RL = 2kΩ, AV = +1, VS = ±7.5V 0.09 0.09 µs Overshoot OS 10 10 % Settling Time (to <0.1%, VIN = 4VP-P)t S CL = 25pF, RL = 2kΩ, AV = +1, VS = ±7.5V 1.8 1.8 µs Input Offset Voltage V IO V+ = 5V, V- = 0V 2 6 mV Input Offset Current I IO V+ = 5V, V- = 0V 0.1 0.1 pA Input Current I I V+ = 5V, V- = 0V 2 2 pA Common Mode Rejection Ratio CMRR V+ = 5V, V- = 0V 70 60 dB Large Signal Voltage Gain A OL VO = 4VP-P, RL = 20kΩ, V+ = 5V, V- = 0V 100 100 kV/V 100 100 dB Common Mode Input Voltage Range V ICR V+ = 5V, V- = 0V 0 to 2.5 0 to 2.5 V Supply Current I+ V O = 5V, RL = ∞, V+ = 5V, V- = 0V 1 1 mA Power Supply Rejection Ratio PSRR ∆VIO/∆V+, V+ = 5V, V- = 0V 200 200 µV/V Electrical Specifications For Each Amplifier at TA = 25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage |V IO|V S = ±7.5V - 2 5 - 6 15 mV Input Offset Current |I IO|V S = ±7.5V - 0.5 20 - 0.5 30 pA Input Current I I VS = ±7.5V - 5 30 - 5 50 pA Large Signal Voltage Gain A OL VO = 10VP-P, RL = 10kΩ 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB Common Mode Rejection Ratio CMRR 80 95 - 70 90 - dB Common Mode Input Voltage Range VlCR 0- 0 . 5 t o 10 0 -0.5 to 10 V CA3260, CA3260A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1266.6 February 7, 2006 Schematic Diagram Power Supply Rejection Ratio PSRR ∆VIO/∆V+ V+ = 17.5V - 32 150 - 32 320 µV/V Maximum Output Voltage V OM+R L = 10kΩ 11 13.3 - 11 13.3 - V VOM- - 0.002 0.01 - 0.002 0.01 V VOM+R L = ∞ 14.99 15 - 14.99 15 - V VOM- - 00 . 0 1- 00 . 0 1V Maximum Output Current I OM+ Source V O = 7.5V 12 22 45 12 22 45 mA IOM- Sink 12 20 45 12 20 45 mA Total Supply Current I+ R L = ∞ VO (Amplifier A) = 7.5V VO (Amplifier B) = 7.5V - 9 15.5 - 9 15.5 mA VO (Amplifier A) = 0V VO (Amplifier B) = 0V -1 . 23 -1 . 23 m A VO (Amplifier A) = 0V VO (Amplifier B) = 7.5V -5 8 . 5 -5 8 . 5 m A Input Offset Voltage Temperature Drift ∆VIO/∆T- 6 - - 8 - µV/°C Crosstalk f = 1kHz - 120 - - 120 - dB Electrical Specifications For Each Amplifier at TA = 25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 UNITSMIN TYP MAX MIN TYP MAX 200K 300K Q12 Q11 Q10 D2 D3 D4D1 Q1 Q2 Q13Q14 Q3 Q4 30pF 3 2 1 AMPLIFIER A R13 200K R14 300Ω Q26 Q25 Q24D7D6 D5 D8 Q15 Q16 Q20 R11 R10 Q27 Q28 Q17Q18 30pF R12 Q21 Q23 567 Q19 Q22 AMPLIFIER B 8 V+ CA3260, CA3260A