CA3252 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Four 600mA Non-Inverting Power Output Drivers
  • 50V and 1A Maximum Rated Power Output Drivers
  • Inputs Compatible With TTL or 5V CMOS Logic
  • Suitable For Resistive, Lamp or Inductive Loads
  • Inductive Clamps on Each Output
  • High Dissipation Power-Frame Package oC to 105oC

Applications

  • Solenoids
  • Relays
  • Lamps
  • Steppers
  • Small Motors
  • Displays System Applications
  • Automotive
  • Appliances
  • Industrial Controls
  • Robotics

Description

The CA3252 is used to interface low-level logic to high cur- rent loads. Each Power Driver has four inverting switches consisting of an inverting logic input stage and an inverting low-side driver output stage. All inputs are 5V TTL/CMOS logic compatible and have a common Enable input. On-chip steering diodes are connected from each output (in pairs) to the CLAMP pins (in pairs) which may be used in conjunction with external zener diodes to protect the IC against over-volt- age transients that result from inductive load switching. The CA3252 may be used in a variety of automotive and indus- trial control applications to drive relays, solenoids, lamps and small motors. To allow for maximum heat transfer from the chip, all ground pins on the DIP and SOIC packages are directly connected to the mounting pad of the chip. Integral heat spreading lead frames directly connect the bond pad and ground leads for good heat dissipation. In a typical application, the package is mounted on a copper PC Board. By increasing copper ground area on the PC Board, more heat is conducted away from the ground leads. The junction-to-ambient thermal resistances may be reduced to less than 40 oC/W with approximately two square inches of copper area. Pinouts CA3252E (PDIP) TOP VIEW CA3252M (SOIC) TOP VIEW

Ordering Information

NUMBER TEMP. ( oC) PACKAGE PKG. NO. CA3252E -40 to 105 16 Ld PDIP E16.3 CA3252M -40 to 105 20 Ld SOIC M20.3 OUT A CLAMP AB OUT B GND GND OUT C CLAMP CD OUT D IN A IN B ENABLE GND GND V CC IN C IN D 1CLAMP AB NC NC OUT B GND GND NC OUT C NC CLAMP CD OUT A INB ENABLE GND IN A GND V CC IN C IN D OUT D File Number 1542.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

FIGURE 1. CA3252 QUAD NON-INVERTING POWER DRIVER SHOWN WITH TYPICAL APPLICATION LOADS

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) θJAoC/W (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The Maximum Ambient Temperature is limited for the sustained conditions of the ICC(ON) Supply Current test with all Outputs ON. The total level of sustained current will significantly increase the on-chip temperature due to increased dissipation. Under any condition, the Absolute Maximum Junction Temperature must not exceed150 oC. While any one loaded output may exceed 0.7A, the maximum rating limit is 1A. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = -40oC to 105oC, VCC = VEN = 5V; Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Output Sustaining Voltage V CE(SUS) IC = 100mA, VIN = 2V, VEN = 2V 35 - V Output Leakage Current I CEX VCE = 50V, VIN = 2V, VEN = 0.8V - 100 µA Collector to Emitter Saturation Voltage VCE(SAT) IC = 100mA, VIN = 0.8V - 0.3 V IC = 300mA, VIN = 0.8V - 0.5 V IC = 600mA, VIN = 0.8V - 0.8 V Input Low Voltage V IL - 0.8 V Input Low Current I IL VIN = 0.4V -15 10 µA Input High Voltage V IH IC = 600mA 2 - V Input High Current I IH IC = 600mA, VIN = 4.5V -10 -10 µA Logic Supply Current, All Outputs ON ICC(ON) IC = 600mA, All Outputs ON (Note 1) - 90 mA Logic Supply Current, All Outputs OFF ICC(OFF) All Outputs OFF - 10 mA Clamp Diode Leakage Current I R VR = 50V (Diode Reverse Voltage) - 100 µA Clamp Diode Forward Voltage V F IF = 0.6A - 1.8 V IF = 1.2A - 2.0 V Output Current I OUT VIN = 0.4V, VBATT = +13V, Output Load = 10Ω 0.9 - A Turn-ON Propagation Delay Time t PHL IC = 600mA - 10 µs Turn-OFF Propagation Delay Time t PLH IC = 600mA - 10 µs Low Enable Voltage V ENL - 0.8 V Low Enable Current I ENL VEN = 0.4V -15 10 µA High Enable Voltage V ENH 2.0 - V High Enable Current I ENH VEN ≥ 2V -250 +250 µA CA3252

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM B S eA -C- Dual-In-Line Plastic Packages (PDIP) E16.3(JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CA3252 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM B S e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 0 2 0 7 α 0o 8o 0o 8o - Rev. 0 12/93