CA324E

CA124, CA224, CA324, LM324, LM2902

Document overview

• Manufacturer or author: Intersil Corporation
• PDF pages: 7

Technical content

Features

• Operation from Single or Dual Supplies  Input Offset Current  Replacement for Industry Types 124, 224, 324

Applications

 Summing Amplifiers  Multivibrators  Oscillators  Transducer Amplifiers  DC Gain Blocks Pinout CA124, CA224, CA324, LM2902 (PDIP, SOIC) LM324 (PDIP) TOP VIEW Part Number Information PART NUMBER (BRAND) TEMP. RANGE ( oC) PACKAGE PKG. NO. CA0124E -55 to 125 14 Ld PDIP E14.3 CA0124M (124) -55 to 125 14 Ld SOIC M14.15 CA0124M96 (124) -55 to 125 14 Ld SOIC Tape and Reel M14.15 CA0224E -40 to 85 14 Ld PDIP E14.3 CA0224M (224) - 4 0t o8 5 1 4L dS O I C M 1 4 . 1 5 CA0324E 0 to 70 14 Ld PDIP E14.3 CA0324M (324) 0t o7 0 1 4L dS O I C M 1 4 . 1 5 CA0324M96 (324) 0t o7 0 1 4L dS O I CT a p ea n d Reel M14.15 LM324N 0 to 70 14 Ld PDIP E14.3 LM2902N -40 to 85 14 Ld PDIP E14.3 LM2902M (2902) - 4 0t o8 5 1 4L dS O I C M 1 4 . 1 5 LM2902M96 (2902) - 4 0t o8 5 1 4L dS O I CT a p ea n d Reel M14.15 OUTPUT 1 OUTPUT 2 OUTPUT 4 OUTPUT 3 POS. INPUT 2 POS. INPUT 1 NEG. INPUT 1 NEG. INPUT 3 POS. INPUT 3 POS. INPUT 4 NEG. INPUT 4 NEG. INPUT 2 Data Sheet May 2001 itle 224 324 324 290 ad, Hz, ra- al pli- s us- li- tho ds er- O B SO LETE PR O D U C T N O R EC O M M EN D ED R EPLA C EM EN T

Absolute Maximum Ratings Thermal Information Input Current (V Operating Conditions T emperature Range Thermal Resistance (Typical, Note 3) θJA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. This input current will only exist when the voltage at any of the input leads is driven negative. This current is due to the collector base junction of the input p-n-p transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral n-p-n parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the amplifiers to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This transistor action is not destructive and normal output states will re- establish when the input voltage, which was negative, again returns to a value greater than -0.3V. 2. The maximum output current is approximately 40mA independent of the magnitude of V+. Continuous short circuits at V+ > 15V can cause excessive power dissipation and eventual destruction. Short circuits from the output to V+ can cause overheating and eventual destruction of the device. 3. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsValues Apply for Each Operational Amplifier. Supply Voltage V+ = 5V, V- = 0V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP . (oC) CA124 CA224, CA324, LM324 LM2902 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX Input Offset Voltage (Note 6) 2 5 -2 5 -2 7 --- m V F u l l --7 --9 -- 1 0 m V Average Input Offset Voltage Drift R S =0 Ω F u l l -7--7--7- µV/oC Differential Input Voltage (Note 5) F u l l -- V + -- V + -- V + V Input Common Mode Voltage Range (Note 5) Common Mode Rejection Ratio DC 25 70 85 - 65 70 - - - - dB Power Supply Rejection Ratio DC 25 65 100 - 65 100 - - - - dB Input Bias Current (Note 4) II+o rII- 25 - 45 150 - 45 250 - - - nA II+o rII- Full - - 300 - - 500 - 40 500 nA Input Offset Current II+-II- Full - - 100 - - 150 - 45 200 nA Average Input Offset Current Drift F u l l -1 0- -1 0- -1 0- p A / oC Large Signal Voltage Gain R L ≥ 2kΩ ,V +=1 5 V (For Large VO Swing) 25 94 100 - 88 100 - - - - dB R L ≥ 2kΩ ,V +=1 5 V (For Large VO Swing) Full 88 - - 83 - - 83 - - dB CA124, CA224, CA324, LM324, LM2902

Schematic Diagram (One of Four Operational Amplifiers) Output Voltage Swing R L =2 kΩ 2 5 0- V + - 1 . 5 0- V + - 1 . 5 - - - V High Level R L = 2kΩ , V+ = 30V Full 26 - - 26 - - - - - V R L =1 0 kΩ , V+ = 30V Full 27 28 - 27 28 - 23 28 - V Low Level R L =1 0 kΩ F u l l -5 2 0 -5 2 0 -5 1 0 0 m V Output Current Source V I+=+ 1 V ,VI-=0 V , V+ = 15V 25 20 40 - 20 40 - - - - mA VI+=1 V ,VI-=0 , V+ = 15V Full 10 20 - 10 20 - 10 20 - mA Sink V I+=0 V ,VI-=1 V , V+ = 15V 25 10 20 - 10 20 - - - - mA VI+=0 V ,VI-=1 V , VO =2 0 0 m V 25 12 50 - 12 50 - - - - µA VI-=1 V ,VI+=0 , V+ = 15V F u l l 58 - 58 - 58 - m A Crosstalk f = 1 to 20kHz (Input Referred) Total Supply Current R L = ∞ F u l l -0 . 82 -0 . 82 -0 . 7 1 . 2 m A NOTES: 4. Due to the PNP input stage the direction of the input current is out of the IC. No loading change exists on the input lines because the current is essentially constant, independent of the state of the output. 5. The input signal voltage and the input common mode voltage should not be allowed to go negative by more than 0.3V. The positive limit of the common mode voltage range is V+ - 1.5V, but either or both inputs can go to +32V without damage. 6. VO =1 . 4 V ,RS =0 Ω with V+ from 5V to 30V, and over the full input common mode voltage range (0V to V+ - 1.5V). Electrical SpecificationsValues Apply for Each Operational Amplifier. Supply Voltage V+ = 5V, V- = 0V, Unless Otherwise Specified(Continued) PARAMETER TEST CONDITIONS TEMP . (oC) CA124 CA224, CA324, LM324 LM2902 UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX 5 + 2 7 10 + 3 8 12 + 4 4 TO 2, 3, 4 TO 2, 3, 4 VO R SC Q 6 Q 5 Q 7 Q 12 50µA 100 µA Q 11 Q 10 C COMP 4µA6µA Q 9 Q 4 Q 3Q 2 Q 8 Q 1 INPUTS Q 13 CA124, CA224, CA324, LM324, LM2902

CA124, CA224, CA324, LM324, LM2902 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpen- dicular to datum . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 4 1 4 9 Rev. 0 12/93

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How- ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 1 0 0 ,R u ed el aF u s e e

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 CA124, CA224, CA324, LM324, LM2902 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does notinclude interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) hx4 5o C H µ 0.25(0.010) BM M α M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 0 12/93