CA3224E_02 INTERSIL | Alldatasheet

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Technical content

Features

 Automatic Picture Tube Bias Cutoff Control  Automatic Background Color Balance  Eliminates Grey Scale Adjustments  Compensates for Cathode-to-Heater Leakage  Electrostatic Protection on All Pins  Servo Loop Design  Wide Dynamic Range  Three-Gun Control  Minimal External Components Pinout CA3224E (PDIP) TOP VIEW Part Number Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CA3224E -40 to 85 22 Ld PDIP E22.4 CHANNEL 1 INPUT CHANNEL 1 FREQ COMPENSATION CHANNEL 2 INPUT CHANNEL 2 FREQ COMPENSATION CHANNEL 3 INPUT CHANNEL 3 FREQ COMPENSATION GROUND VERTICAL INPUT HORIZONTAL INPUT GRID PULSE OUTPUT CHANNEL 1 HOLD CAP CHANNEL 2 HOLD CAP CHANNEL 2 OUTPUT CHANNEL 3 HOLD CAP CHANNEL 1 OUTPUT CHANNEL 3 OUTPUT VREF BYPASS AUTO BIAS LEVEL ADJUST AUTO BIAS PULSE OUTPUT PROGRAM PULSE OUTPUT GROUND VCC Data Sheet October 2002O B SO LETE PR O DU C T N O R ECO M M EN DE D R EPLAC EM EN T

Absolute Maximum Ratings TA =2 5oC Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsAt TA = 25oC, VCC = 10V, VBIAS = 3.75V, VV (Pin 8) = VH (Pin 10) = 6.0V, S1 = A, S2 = A, See Test Circuit and Timing Diagrams PARAMETER TEST PIN NO. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Supply Current 22 I CC -- 6 5 m A Reference Voltage 2, 4, 6 V REF Measure at t4 5.6 6.0 6.4 V Input Current 2, 4, 6 I I VIN = 7.2V, S1 = B - - 250 nA Output Current Source 17,19, 21 l OM +V BIAS = 0.5V , Measure at t6, S1 = B - - -0.8 mA Sink l OM -V BIAS = 7.0V , Measure at t6, S1 = B 0.8 - - mA Output Buffer Input Current 17,19, 21 I I VOUT = 6.5V, VIN At pins 16, 18, 20, Measure at t4, S1 = B - - 150 nA Voltage Gain A V 0.97 - 1.07 - Transconductance 17,19, 21 g M Measure at t6, VIN = 8mVP-P at 40kHz, S1 = B 50 - 100 mS Auto Bias Pulse Output Low 13 V OL Measure at t1 -- 0 . 3V High V OH Measure at t4 6.05 - - V Current Sink l OM - Measure at t4, S2 = B 2.5 - - mA Grid Pulse Output Low 11 V OL Measure at t4 -- 0 . 4V High V OH Measure at t1 4.2 - - V Program Pulse Output Low 12 V OL Measure at t6 -- 0 . 4V High V OH Measure at t1 8.2 - - V Vertical Input 8 V V See Figure 3 - 6.0 - V Horizontal Input 10 V H See Figure 3 - 6.0 - V Auto Bias Pulse Timing Start 13 t 0 to t2, Note 2 835 - 842 µs Finish t 0 to t7, Note 2 1270 - 1275 µs Grid Pulse Timing Start 11 t 0 to t3, Note 2 899 - 905 µs Finish t 0 to t5, Note 2 1080 - 1084 µs Program Pulse Timing Start 12 t 0 to t5, Note 2 1080 - 1084 µs Finish t 0 to t7, Note 2 1270 - 1275 µs NOTE: 2. All time measurements are made from 50% point to 50% point. CA3224E

interval lasts for 3 horizontal periods. adjusts the bias on the driver circuit. desired cathode cutoff level.

1 OUT

2 OUT

3 OUT

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com CA3224E Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E22.4 (JEDEC MS-010-AA ISSUE C)

22 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.065 1.15 1.65 8 C 0.009 0.015 0.229 0.381 - D 1.065 1.120 27.06 28.44 5 D1 0.005 - 0.13 - 5 E 0.390 0.425 9.91 10.79 6 E1 0.330 0.390 8.39 9.90 5 e 0.100 BSC 2.54 BSC - e A 0.400 BSC 10.16 BSC 6 eB - 0.500 - 12.70 7 L 0.115 0.160 2.93 4.06 4 N2 2 2 2 9 Rev. 0 12/93