CA3054_05 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Two Differential Amplifiers on a Common Substrate  Independently Accessible Inputs and Outputs  Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

 Dual Sense Amplifiers  Dual Schmitt Triggers  Multifunction Combinations - RF/Mixer/Oscillator; Converter/IF  IF Amplifiers (Differential and/or Cascode)  Product Detectors  Doubly Balanced Modulators and Demodulators  Balanced Quadrature Detectors  Cascade Limiters  Synchronous Detectors  Pairs of Balanced Mixers  Synthesizer Mixers  Balanced (Push-Pull) Cascode Amplifiers Pinout CA3054 (SOIC) TOP VIEW

Ordering Information

(BRAND) TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA3054M96 (3054) 0 to 85 14 Ld SOIC Tape and Reel M14.15 CA3054MZ (CA3054MZ) 0 to 85 14 Ld SOIC (Pb-free) M14.15 CA3054MZ96 (CA3054MZ) 0 to 85 14 Ld SOIC Tape and Reel (Pb-free) M14.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. SUBSTRATE NC Q 4 Q 6Q 5 Q 3 Q 2 Q 1 Data Sheet September 22, 2005 FN388.6 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Harri Corporation 1998. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings TA =2 5 ° C Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) θJA (°C/W) (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Maximum Voltage Ratings Maximum Current Ratings The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the termi- nals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V. (NOTE 4) TERM N O . 1 3 1 4 12346789 1 1 1 25 (NOTE 4) TERM NO. IIN mA IOUT mA 13 0, -20 Note 3 +5, -5 Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 13 50 . 1 14 Note 3 Note 3 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 +20, 0 14 50 0.1 1 +20, 0 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 +20, 0 1 50 0.1 2 Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 2 50 . 1 3 +1, -5 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 3 50 . 1 4 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 4 0.1 50 6 0, -20 Note 3 +5, -5 Note 3 +15, -5 Note 3 6 50 . 1 7 Note 3 Note 3 Note 3 Note 3 +20, 0 7 50 0.1 8 +20, 0 Note 3 Note 3 +20, 0 8 50 0.1 9 Note 3 +15, -5 Note 3 9 50 . 1 11 -1, -5 Note 3 11 50 . 1 12 Note 3 12 0.1 50 5 Ref. Sub- strate NOTES: 3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe if the specified limits between all other terminals are not exceeded. 4. Terminal No. 10 of CA3054 is not used. Electrical SpecificationsTA = 25°C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS For Each Differential Amplifier Input Offset Voltage (Figure 8) V IO VCB = 3V, IE(Q3) = IE(Q4) = 2mA - 0.45 5 mV Input Offset Current (Figure 9) I IO VCB = 3V, IE(Q3) = IE(Q4) = 2mA - 0.3 2 µA Input Bias Current (Figure 5) I I VCB = 3V, IE(Q3) = IE(Q4) = 2mA - 10 24 µA Quiescent Operating Current Ratio (Figure 5) VCB = 3V, IE(Q3) = IE(Q4) = 2mA - 0.98 to 1.02 Temperature Coefficient Magnitude of Input Offset Voltage (Figure 7) VCB = 3V, IE(Q3) = IE(Q4) = 2mA - 1.1 - µV/°C IC(Q1) IC(Q2) IC(Q5) IC(Q6) ∆V IO CA3054

DC Forward Base-to-Emitter Voltage (Figure 8) VBE VCB = 3V I C = 50µA - 0.630 0.700 V IC = 1mA - 0.715 0.800 V IC = 3mA - 0.750 0.850 V IC = 10mA - 0.800 0.900 V Temperature Coefficient of Base-to-Emitter Voltage (Figure 6) VCB = 3V, IC = 1mA - -1.9 - µV/°C Collector Cutoff Current (Figure 4) I CBO VCB = 10V, IE = 0 - 0.002 100 nA Collector-to-Emitter Breakdown Voltage V (BR)CEO IC = 1mA, IB = 0 15 24 - V Collector-to-Base Breakdown Voltage V (BR)CBO IC = 10µA, IE = 0 20 60 - V Collector-to-Substrate Breakdown Voltage V(BR)CIO IC = 10µA, ICI = 0 20 60 - V Emitter-to-Base Breakdown Voltage V (BR)EBO IE = 10µA, IC = 0 5 7 - V DYNAMIC CHARACTERISTICS Common Mode Rejection Ratio for each Amplifier (Figures 1, 10) CMRR V CC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz - 100 - dB AGC Range, One Stage (Figures 2, 11) AGC V CC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz -7 5 -d B Voltage Gain, Single Stage Double-Ended Output (Figures 2, 11) AV CC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz -3 2 -d B AGC Range, Two Stage (Figures 3, 12) AGC V CC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz - 105 - dB Voltage Gain, Two Stage Double-Ended Output (Figures 3, 12) AV CC = 12V, VEE = -6V, VX = -3.3V, f = 1kHz -6 0 -d B Low Frequency, Small Signal Equivalent Circuit Char- acteristics (For Single Transistor) Forward Current Transfer Ratio (Figure 13) h FE f = 1kHz, VCE = 3V, IC = 1mA - 110 - - Short Circuit Input Impedance (Figure 13) h IE f = 1kHz, VCE = 3V, IC = 1mA - 3.5 - k Ω Open Circuit Output Impedance (Figure 13) hOE f = 1kHz, VCE = 3V, IC = 1mA - 15.6 - µS Open Circuit Reverse Voltage Transfer Ratio (Figure 13) hRE f = 1kHz, VCE = 3V, IC = 1mA - 1.8 x 10-4 1/f Noise Figure for Single Transistor NF f = 1kHz, V CE = 3V - 3.25 - dB Gain Bandwidth Product for Single Transistor (Figure 14) fT VCE = 3V, IC = 3mA - 550 - MHz Admittance Characteristics; Differential Circuit Configuration (For Each Amplifier) Forward Transfer Admittance (Figure 15) Y 21 VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA -- 2 0 + j 0 - m S Input Admittance (Figure 16) Y 11 VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA - 0.22 + j0.1 -m S Output Admittance (Figure 17) Y 22 VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA - 0.01 + -m S Reverse Transfer Admittance (Figure 18) Y 12 VCB = 3V, f = 1MHz Each Collector IC ≈ 1.25mA - -0.003 + j0 -m S Electrical SpecificationsTA = 25°C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ∆V BE CA3054

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. FIGURE 22. REVERSE TRANSFER ADMITTANCE (Y 12) vs FREQUENCY