CA3130 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- MOSFET Input Stage Provides: - Very High ZI = 1.5 TΩ (1.5 x 1012Ω ) (Typ)
- Ideal for Single-Supply Applications
- Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.5V Below Negative Supply Rail
- CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails
Applications
- Ground-Referenced Single Supply Amplifiers
- Fast Sample-Hold Amplifiers
- Long-Duration Timers/Monostables
- High-Input-Impedance Comparators (Ideal Interface with Digital CMOS)
- High-Input-Impedance Wideband Amplifiers
- Voltage Followers (e.g. Follower for Single-Supply D/A Converter)
- Voltage Regulators (Permits Control of Output Voltage Down to 0V)
- Peak Detectors
- Single-Supply Full-Wave Precision Rectifiers
- Photo-Diode Sensor Amplifiers OFFSET INV. NON-INV. STROBE OUTPUT OFFSET NULL INPUT INPUT NULL TAB OUTPUTINV. V- AND CASE OFFSET NON-INV. V OFFSET STROBE PHASE COMPENSATION NULLINPUT INPUT NULL
Ordering Information
PART NO. (BRAND) TEMP. RANGE (oC) PACKAGE PKG. NO. CA3130AE -55 to 125 8 Ld PDIP E8.3 CA3130AM (3130A) -55 to 125 8 Ld SOIC M8.15 CA3130AM96 (3130A) -55 to 125 8 Ld SOIC Tape and Reel M8.15 CA3130AT -55 to 125 8 Pin Metal Can T8.C CA3130E -55 to 125 8 Ld PDIP E8.3 CA3130M (3130) -55 to 125 8 Ld SOIC M8.15 CA3130M96 (3130) -55 to 125 8 Ld SOIC Tape and Reel M8.15 CA3130T -55 to 125 8 Pin Metal Can T8.C Data Sheet September 1998 File Number 817.4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Copyright © Intersil Corporation 1999
Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage |V IO|V S =±7.5V - 8 15 - 2 5 mV Input Offset Voltage Temperature Drift ∆VIO/∆T - 10 - - 10 - µV/oC Input Offset Current |I IO|V S =±7.5V - 0.5 30 - 0.5 20 pA Input Current I I VS =±7.5V - 5 50 - 5 30 pA Large-Signal Voltage Gain A OL VO = 10VP-P R L = 2kΩ 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB Common-Mode Rejection Ratio CMRR 70 90 - 80 90 - dB Common-Mode Input Voltage Range VICR 0 -0.5 to 12 10 0 -0.5 to 12 10 V Power-Supply Rejection Ratio ∆VIO/∆VS VS =±7.5V - 32 320 - 32 150 µV/V Maximum Output Voltage V OM +R L = 2kΩ 12 13.3 - 12 13.3 - V VOM -R L = 2kΩ - 0.002 0.01 - 0.002 0.01 V VOM +R L =∞ 14.99 15 - 14.99 15 - V VOM -R L =∞ - 0 0.01 - 0 0.01 V Maximum Output Current I OM + (Source) at VO = 0V 12 22 45 12 22 45 mA IOM - (Sink) at VO = 15V 12 20 45 12 20 45 mA Supply Current I+ V O = 7.5V, RL =∞ - 10 15 - 10 15 mA I+ V O = 0V, RL =∞ -23-23 m A CA3130, CA3130A
Electrical SpecificationsTypical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA3130, CA3130A UNITS Input Offset Voltage Adjustment Range 10k Ω Across Terminals 4 and 5 or 4 and 1 ±22 mV Input Resistance R I 1.5 T Ω Input Capacitance C I f = 1MHz 4.3 pF Equivalent Input Noise Voltage e N BW = 0.2MHz, RS = 1MΩ (Note 3) 23 µV Open Loop Unity Gain Crossover Frequency (For Unity Gain Stability≥47pF Required.) fT C C = 0 15 MHz C C = 47pF 4 MHz Slew Rate: SR C C = 0 30 V/ µsOpen Loop Closed Loop C C = 56pF 10 V/ µs Transient Response: C C = 56pF, C L = 25pF, R L = 2kΩ (Voltage Follower) 0.09 µsRise Time t r Overshoot OS 10 % Settling Time (To <0.1%, VIN = 4VP-P)t S 1.2 µs NOTE: 3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ. Electrical SpecificationsTypical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC Unless Otherwise Specified (Note 4) PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS Input Offset Voltage V IO 82 m V Input Offset Current I IO 0.1 0.1 pA Input Current I I 22 p A Common-Mode Rejection Ratio CMRR 80 90 dB Large-Signal Voltage Gain A OL VO = 4VP-P, RL = 5kΩ 100 100 kV/V 100 100 dB Common-Mode Input Voltage Range V ICR 0 to 2.8 0 to 2.8 V Supply Current I+ V O = 5V, RL =∞ 300 300 µA VO = 2.5V, RL =∞ 500 500 µA Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V NOTE: 4. Operation at 5V is not recommended for temperatures below 25oC. CA3130, CA3130A
Application Information
Figure 1 is a block diagram of the CA3130 Series CMOS Operational Amplifiers. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA3130 Series circuits are ideal for single-supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in Figure 1, provide the total gain of the CA3130. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply-rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g.,when the amplifier output is used to drive CMOS digital circuits in Comparator applications). Input Stage The circuit of the CA3130 is shown in the schematic diagram. It consists of a differential-input stage using PMOS field-effect transistors (Q 6, Q7) working into a mirror-pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror-pair transistors also function as a differential-to-single-ended converter to provide base drive to the second-stage bipolar transistor (Q 11). Offset nulling, when desired, can be effected by connecting a 100,000Ω potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascade-connected PMOS transistors Q 2, Q4 are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described. The small diodes D 1 8 4 Q 1 Q 2 Q 4 D 1 D 2 D 3 D 4 Q 3 Q 5 D 5 D 6 D 7 D 8 Q 9 Q 10 Q 6 Q 7 8.3V INPUT STAGE R 3 1kΩ R 4 1kΩ R 6 1kΩ R 5 1kΩ NON-INV. INPUT INV.-INPUT R 1 40kΩ 5kΩ R 2 BIAS CIRCUIT CURRENT SOURCE FOR “CURRENT SOURCE LOAD” FOR Q 11Q 6 AND Q 7 OUTPUT OUTPUT STAGE Q 8 Q 12 Q 11 SECOND STAGE OFFSET NULL COMPENSATION STROBING (NOTE 5) NOTE: 5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage. CA3130, CA3130A
FIGURE 12. PEAK-DETECTOR CIRCUITS FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)
0 TO 13V
adjustable reference voltage for the error amplifier. functions in the previously described current-limiting circuit. FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)
0.1 TO 50V
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. a CA3130, to provide the triangular-wave output. in generating the linear triangular wave. CA3130 output stage by about 2.5X.
- See file number 619 for technical information.
FIGURE 15. PULSE GENERATOR (ASTABLE MULTIVIBRATOR)