CA1523 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 6

Technical content

Features

  • Operates up to 200kHz
  • Pins ESD Protected
  • Remote ON/OFF
  • Slow Start with Reset
  • Overcurrent Sensing
  • Lower Peak Currents than PWM Regulator - Less Prone to Magnetic Saturation

Ordering Information

CA1523E 0 oC to +70oC 14 Lead Plastic DIP File Number 1785.2 April 1994 Pinout CA1523 (PDIP) TOP VIEW ERROR CURRENT SENSE GND RISE TIME OUTPUT GND OUTPUT VCC TIMING ZENER ON/OFF OVER CURRENT SLOW START LOGIC OUTPUT NC

Specifications CA1523 Absolute Maximum Ratings Thermal Information Supply Current Device Dissipation Thermal Resistance θJA Device Dissipation Ambient Temperature Range Lead Temperature (During Soldering) At distance 1/16± in. (1.59mm±0.79mm) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsTA = +25oC, Refer to condition shown in test circuit; V7 = 13V, V1 = 5.9V Unless Otherwise Specified PARAMETERS PIN TEST CONDITIONS MIN TYP MAX UNITS POWER SUPPLY, V CC (PIN 7) Supply Voltage 7 9.5 13 - V Supply Current 7 V CC = +13V 20 27 34 mA Zener Voltage 13 7.8 8.4 8.9 V OUTPUT PULSE (PIN 6) Maximum Pulse Width 6 Measured at 6V Threshold Level 5.5 6.5 7.5 µs Minimum Pulse Width 6 Measured at 6V Threshold Level 2 3 4 µs Output High Voltage 6 | 6 = 0mA, V4 = 0V 11.1 12 12.6 V Output Low Voltage 6 | 6 = 50mA, V12 = 0V 0.6 1 1.3 V Rise Time 6 Measured at 1.8V and 10V Threshold Levels 250 600 1250 ns Fall Time 6 Measured at 1.8V and 10V Threshold Levels 50 200 350 ns ERROR VOLTAGE RANGE (PIN 1) Error Voltage Reference 1 Adjust R T; Observe Pin 6 Min/Max Frequency Range 5.9 6.8 7.5 V CHARGE CURRENT (PIN 14) Charge Current 14 Adjust R T, V1 = 7.5V; Set V14 = 0V, Then V14 = 2.5V 190 220 250 µA Discharge Current 14 Adjust R T = 5.9V; Set V14 = 5.5V, Then 5V 95 110 125 µA Slow Start Discharge Current 14 Maintain V 14 = 5V, V10 = 5.5V Set V10 = 5.5V, Measure I14 (Hi) Set V10 = 4V, Measure I14 (Lo) Limits = I14 (Hi) - I14 (Lo) 1.5 20 30 40 µA/V LOGIC TESTS Discharge Voltage 10 Pin 12 = 1k Ω to GND 1.7 2.4 3.2 V Output Inhibit Voltage 7 Increase V 7 Until V9 ≥ 2V 7.9 8.4 9.1 V Overcurrent Trip Voltage 11 V 12 = 5V; V10 = 0V; Increase V11 Until V9 ≤ 0.5V 1.1 1.25 1.4 V

Other desirable features along with various circuit block function explanations are listed below.

  • The Oscillator is a sawtooth generator whose charge (rise) cycle determines the output pulse width and dis- charge which is continuously variable from very low to maximum of I CHARGE .
  • Charge ICHARGE = IO -IDISCHARGE giving 2 to 1 pulse-width control
  • Discharge IDISCHARGE = approximately 0 to 1/2 IO to frequency control.
  • Pulse Shaping:Applied to the oscillator output via RS Flip-Flop with parallel inhibit controlled by slow-start over- current sense, supply voltage monitor and ON/OFF func- tions.
  • Pulse Rise Time:Modified to meet RFI requirements by external slow-down capacitor.
  • Slow Start with Reset:Externally programmed against internal 3V reference. Reset is initiated upon Inhibit ensur- ing soft start at power up and restart.
  • Over Current Sense:Internal stable thresholds of 1.2V.
  • Supply Voltage Monitors:Locks out the drive until V SUPPLY has reached 8V-9V.
  • ON/OFF: Activates regulator independent of raw DC.
  • Error Amplifier:Compares output against a stable 6.8V internal reference and controls the discharge current sink on the timing capacitor.
  • Band-Gap: Reference voltage (internal) provides temper- ature compensated 1.2V and 6.8V references.
  • Separate GND: The power GND is separated from circuit ground for improved noise.
  • ESD Protection:Pins are protected against ESD. Block Diagram CURRENT SENSE IC/2 IC +6.8V REF. ERROR VOLTAGE VCC VCC 1.2V REF. ID ~ IC/2 FOR VI << 6.8V ON/OFF Q HIGH CLOSES S 1 CURRENT SETUP Q LOW CLOSES S 3 VCC > 8.4V +VL 2.5V VH LOGIC OUT S R Q F/F S R Q F/F REF. VOLTAGE SOURCES ZENER 6.8V REF. TIMING CAP GND S2 OPEN WHEN V IO > 6.8V (CONTROL CIRCUIT GND) SLOW START REF. REF. RISE TIME PULSE OUTPUT OUTPUT GND OVER CURRENT I D

FIGURE 1. TEST CIRCUIT FOR THE CA1523

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 727-9207 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CA1523