CA1168

SN65C1167_V01 TI | Alldatasheet

Document overview

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Technical content

SN75C1167,SN65C1168,SN75C1168 www.ti.com SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 DUALDIFFERENTIALDRIVERSANDRECEIVERS Check forSamples: SN65C1167 SN75C1167 SN65C1168 SN75C1168 1FEATURES SN65C1167 ...DB OR NS PACKAGE

• Meet or Exceed Standards TIA/EIA-422-Band SN75C1167 ...DB, N, OR NS PACKAGE (TOP VIEW)ITU Recommendation V.11
• BiCMOS Process Technology
• Low Supply-CurrentRequirements:9 mA Max
• Low Pulse Skew
• ReceiverInputImpedance ...17 kΩ Typ
• ReceiverInputSensitivity...±200 mV
• ReceiverCommon-Mode InputVoltageRange of−7 V to7 V
• Operate From Single5-V Power Supply
• Glitch-FreePower-Up/Power-Down Protection forSN65C1167 and SN75C1167 Only (TOP VIEW)
• Improved Replacements fortheMC34050 and MC34051

DESCRIPTION

The SN65C1167, SN75C1167, SN65C1168, and SN75C1168 dualdriversand receiversare integratedcircuits designedforbalancedtransmissionlines.The devicesmeet TIA/EIA-422-Band ITU recommendationV.11. The SN65C1167 and SN75C1167 combine dual 3-statedifferentiallinedriversand 3-statedifferentialline receivers,bothofwhich operatefrom a single5-V power supply.The driverand receiverhave active-highand active-lowenables,respectively,whichcan be connectedtogetherexternallytofunctionas directioncontrol.The SN65C1168 and SN75C1168 drivershave individualactive-highenables. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1993–2009,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SN75C1167,SN65C1168,SN75C1168 SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 www.ti.com

ORDERING INFORMATION

TA PACKAGE (1)(2) ORDERABLE PART NUMBER TOP-SIDE MARKING SN75C1167N SN75C1167N PDIP – N Tube SN75C1168N SN75C1168N SN75C1167NSR 75C1167 SOP – NS Tape and reel SN75C1168NSR 75C1168 0°C to70°C SN75C1167DBR CA1167 SSOP – DB Tape and reel SN75C1168DBR CA1168 Tube SN75C1168PW TSSOP – PW CA1168 Tape and reel SN75C1168PWR PDIP – N Tube SN65C1168N SN65C1168N SN65C1167NSR 65C1167 SOP – NS Tape and reel SN65C1168NSR 65C1168 –40°C to85°C SSOP – DB Tape and reel SN65C1167DBR CB1167 Tube SN65C1168PW TSSOP – PW CB1168 Tape and reel SN65C1168PWR (1) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/sc/packaging. (2) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com.

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SN65C1168, SN75C1168SN65C1 167/SN75C1 167 SN65C1167 SN75C1167,SN65C1168,SN75C1168 www.ti.com SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 FUNCTION TABLES ABC Each Driver(1) INPUT ENABLE OUTPUTS D DE Y Z H H H L L H L H X L Z Z (1) H = highlevel,L = lowlevel,X = irrelevant,Z = highimpedance Each Receiver(1) DIFFERENTIAL INPUTS ENABLE OUTPUT A − B RE R VID ≥ 0.2V L H −0.2V < VID < 0.2V L ? VID ≤ −0.2V L L X H Z Open L H (1) H = highlevel,L = lowlevel,? = indeterminate,X = irrelevant, Z = highimpedance (off),Open = inputdisconnectedorconnected driveroff LOGIC DIAGRAM (POSITIVE LOGIC) Copyright© 1993–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):SN65C1167 SN75C1167 SN65C1168 SN75C1168

EQUIV ALENT OF A OR B INPUTEQUIVALENT OF DRIVER ENABLE INPUT Input VCCVCC Input GND GND 17 kΩ NOM 1.7 kΩ NOM 1.7 kΩ NOM 288 kΩ NOM VCC (A) or GND (B) TYPICAL OF EACH RECEIVER OUTPUTTYPICAL OF EACH DRIVER OUTPUT GND Output VCC GND Output VCC SN65C1167 SN75C1167,SN65C1168,SN75C1168 SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 www.ti.com SCHEMATIC OF INPUTS SCHEMATIC OF OUTPUTS

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SN75C1167,SN65C1168,SN75C1168 www.ti.com SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VCC Supplyvoltagerange(2) –0.5 7 V Driver –0.5 VCC + 0.5 VI Inputvoltagerange V A orB,Receiver –11 14 VID Differentialinputvoltagerange(3) Receiver –14 14 V VO Outputvoltagerange Driver –0.5 7 V IIK orIOK Clamp currentrange Driver ±20 mA Driver ±150 IO Outputcurrentrange mA Receiver ±25 ICC Supplycurrent 200 mA GND current −200 mA TJ Operatingvirtualjunctiontemperature 150 °C DB package 82 N package 67 θJA Package thermalimpedance(4)(5) °C/W NS package 64 PW package 108 Tstg Storagetemperaturerange –65 150 °C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagesvaluesexceptdifferentialinputvoltagearewithrespecttothenetworkGND. (3) Differentialinputvoltageismeasured atthenoninvertingterminalwithrespecttotheinvertingterminal. (4) Maximum power dissipationisa functionofTJ(max),θJA,and TA.The maximum allowablepower dissipationatany allowableambient temperatureisPD = (TJ(max)– TA)/θJA.Operatingattheabsolutemaximum TJ of150°C can affectreliability. (5) The package thermalimpedance iscalculatedinaccordancewithJESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC Supplyvoltage 4.5 5 5.5 V VIC Common-mode inputvoltage(1) Receiver ±7 V VID Differentialinputvoltage Receiver ±7 V VIH High-levelinputvoltage ExceptA,B 2 V VIL Low-levelinputvoltage ExceptA,B 0.8 V Receiver −6 IOH High-leveloutputcurrent mA Driver −20 Receiver 6 IOL Low-leveloutputcurrent mA Driver 20 SN75C1167, SN75C1168 0 70 TA Operatingfree-airtemperature °C SN65C1167, SN65C1168 –40 85 (1) RefertoTIA/EIA-422-Bforexactconditions. Copyright© 1993–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):SN65C1167 SN75C1167 SN65C1168 SN75C1168

SN75C1167,SN65C1168,SN75C1168 SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 www.ti.com DRIVER SECTION ElectricalCharacteristics(1) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT VIK Inputclamp voltage II= −18 mA −1.5 V VIL= 0.8VOH High-leveloutputvoltage VIH = 2 V, IOH = −20 mA 2.4 3.4 VV, VIL= 0.8VOL Low-leveloutputvoltage VIH = 2 V, IOL = 20 mA 0.2 0.4 VV, |VOD1 | Differentialoutputvoltage IO = 0 mA 2 6 V |VOD2 | Differentialoutputvoltage(1) 2 3.1 V Change inmagnitudeofdifferential∆|VOD | ±0.4 Voutputvoltage R L = 100 Ω,See Figure1 VOC Common-mode outputvoltage ±3 V Change inmagnitudeofcommon-mode∆|VOC | ±0.4 Voutputvoltage VO = 6 V 100 IO(OFF) Outputcurrentwithpower off VCC = 0 V µA VO = −0.25V −100 VO = 2.5V 20 IOZ High-impedance-stateoutputcurrent µA VO = 5 V −20 IIH High-levelinputcurrent VI= VCC orVIH 1 µA IIL Low-levelinputcurrent VI= GND orVIL −1 µA IOS Short-circuitoutputcurrent(3) VO = VCC orGND, −30 −150 mA VI= VCC orGND 4 6No load,ICC Supplycurrent(totalpackage)(4) mAEnabled VI= 2.4or0.5V 5 3 C i Inputcapacitance 6 pF (1) RefertoTIA/EIA-422-Bforexactconditions. (2) AlltypicalvaluesareatVCC = 5 V,and TA = 25°C. (3) Not more thanone outputshouldbe shortedata time,and thedurationoftheshortcircuitshouldnotexceed one second. (4) Thisparameterismeasured perinput,whiletheotherinputsareatVCC orGND. SwitchingCharacteristics overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Propagationdelaytime,high-tolow-level R1 = R2 = 50 Ω, R3 = 500 Ω,tPHL 7 12 nsoutput C1 = C2 = C3 = 40 pF, S1 isopen, See Figure2Propagationdelaytime,low-tohigh-leveltPLH 7 12 nsoutput tsk(p) Pulseskew 0.5 4 ns tr Risetime R1 = R2 = 50 Ω, R3 = 500 Ω, 5 10 ns C1 = C2 = C3 = 40 pF, S1 isopen, tf Falltime 5 10 nsSeeFigure3 tPZH Outputenabletimetohighlevel R1 = R2 = 50 Ω, R3 = 500 Ω, 10 19 ns C1 = C2 = C3 = 40 pF, S1 isclosed, tPZL Outputenabletimetolowlevel 10 19 nsSee Figure4 tPHZ Outputdisabletimefromlowlevel R1 = R2 = 50 Ω, R3 = 500 Ω, 7 16 ns C1 = C2 = C3 = 40 pF, S1 isclosed, tPLZ Outputdisabletimefromhighlevel 7 16 nsSee Figure4 (1) AlltypicalvaluesareatVCC = 5 V,and TA = 25°C.

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SN75C1167,SN65C1168,SN75C1168 www.ti.com SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 RECEIVER SECTION ElectricalCharacteristics overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Positive-goinginputthresholdvoltage,differentialVIT+ 0.2 Vinput Negative-goinginputthresholdvoltage,differentialVIT– −0.2(2) Vinput Vhys Inputhysteresis(VIT+ – VIT–) 60 mV VIK Inputclamp voltage,RE SN75C1167 II= −18 mA −1.5 V VOH High-leveloutputvoltage VID = 200 mV, IOH = −6 mA 3.8 4.2 V VOL Low-leveloutputvoltage VID = −200 mV, IOL = 6 mA 0.1 0.3 V High-impedance-stateoutputIOZ SN75C1167 VO = VCC orGND ±0.5 ±5 µAcurrent VI= 10 V 1.5 II Lineinputcurrent Otherinputat0 V mA VI= −10 V −2.5 II Enableinputcurrent,RE SN75C1167 VI= VCC orGND ±1 µA ri Inputresistance VIC = −7 V to7 V, Otherinputat0 V 4 17 kΩ VI= VCC orGND 4 6 ICC Supplycurrent(totalpackage) No load,Enabled mA VIH = 2.4V or0.5V (3) 5 9 (1) AlltypicalvaluesareatVCC = 5 V and TA = 25°C. (2) The algebraicconvention,where thelesspositive(morenegative)limitisdesignatedas minimum, isused inthisdatasheetfor common-mode inputvoltageand thresholdvoltagelevelsonly. (3) RefertoTIA/EIA-422-Bforexactconditions. SwitchingCharacteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT tPLH Propagationdelaytime,low-tohigh-leveloutput 9 17 27 ns See Figure5 tPHL Propagationdelaytime,high-tolow-leveloutput 9 17 27 ns tTLH Transitiontime,low-tohigh-leveloutput 4 9 ns VIC = 0 V,See Figure5 tTHL Transitiontime,high-tolow-leveloutput 4 9 ns tPZH Outputenabletimetohighlevel 13 22 ns tPZL Outputenabletimetolowlevel 13 22 ns R L = 1 kW, See Figure6 tPHZ Outputdisabletimefromhighlevel 13 22 ns tPLZ Outputdisabletimefromlowlevel 13 22 ns (1) Measured perinputwhiletheotherinputsareatVCC orGND (2) AlltypicalvaluesareatVCC = 5 V and TA = 25°C. Copyright© 1993–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):SN65C1167 SN75C1167 SN65C1168 SN75C1168

50% 50% 50%50% tPLHtPHL tPHLtPLH VOLT AGE WAVEFORMS Input (see Note B) 1.3 V1.3 V Input 1.5 V See Note A TEST CIRCUIT 1.3 V1.3 V tsk(p)tsk(p) Y Z 1.3 V1.3 V Y Z VOH VOL 3 V 0 V VOH VOL VOLT AGE WAVEFORMS tr tf 0 V 3 V 10% 90% Input 1.5 V See Note A TEST CIRCUIT 10% 90% Input (see Note B) Differential Output VO D SN65C1167 SN75C1167,SN65C1168,SN75C1168 SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure1.DriverTestCircuit,VOD and VOC A. C1, C2, and C3 includeprobeand jigcapacitance. B. The inputpulseissuppliedby a generatorhavingthefollowingcharacteristics:PRR = 1 MHz, 50% dutycycle,tr = tf ≤ 6 ns. Figure2.DriverTestCircuitand VoltageWaveforms C. C1, C2, and C3 includeprobeand jigcapacitance. D. The inputpulseissuppliedby a generatorhavingthefollowingcharacteristics:PRR = 1 MHz, 50% dutycycle,tr = tf ≤ 6 ns. Figure3.DriverTestCircuitand VoltageWaveforms E. C1, C2, and C3 includeprobeand jigcapacitance. F. The inputpulseissuppliedby a generatorhavingthefollowingcharacteristics:PRR = 1 MHz, 50% dutycycle,tr = tf ≤ 6 ns.

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1.5 V VOH VOL 1.5 V 2 V 0.8 VVOL + 0.3 V tPZHtPHZ tPZLtPLZ VOLT AGE WAVEFORMS Input DE 3 V 0 V1.5 V1.3 V 0 V or 3 V 1.5 V See Note A TEST CIRCUIT VOL − 0.3 V Pulse Generator 50 ΩSee Note B DE Output Output −2.5 V 2.5 V VOL VOH 0 V 10% 90% tPHLtPLH VOLT AGE WAVEFORMS RLA Input CC B Input Device Under T est CL = 50 pF (see Note A) TEST CIRCUIT 90% 10% tTLH 50% tTHL Output (see Note B) B Input A Input = 0 V 50% RL VCC Device Under T est CL = 50 pF (see Note A) TEST CIRCUIT tPZLtPLZ 0 V RE Input 1.3 V 1.3 V GND 0.5 V Output VOH VCC 0.5 V Output VOL 50% 50% tPZHtPHZ VID = −2.5 V or 2.5 V tPZH, tPHZ Measurement: S1 to GND tPZL, tPLZ Measurement: S1 to V CC VOLT AGE WAVEFORMS RE Input SN65C1167 SN75C1167,SN65C1168,SN75C1168 www.ti.com SLLS159F –MARCH 1993–REVISED NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION (continued) Figure4.DriverTestCircuitand VoltageWaveforms G. C L includesprobeand jigcapacitance. H. The inputpulseissuppliedby a generatorhavingthefollowingcharacteristics:PRR = 1 MHz, 50% dutycycle,tr = tf ≤ 6 ns. Figure5.ReceiverTestCircuitand VoltageWaveforms I. C L includesprobeand jigcapacitance. J. The inputpulseissuppliedby a generatorhavingthefollowingcharacteristics:PRR = 1 MHz, 50% dutycycle,tr = tf ≤ 6 ns. Figure6.ReceiverTestCircuitand VoltageWaveforms Copyright© 1993–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):SN65C1167 SN75C1167 SN65C1168 SN75C1168

www.ti.com 17-Jun-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN65C1167NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C1167 Samples SN65C1167NSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C1167 Samples SN65C1168N LIFEBUY PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN65C1168N SN65C1168NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 65C1168 Samples SN65C1168PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB1168 Samples SN65C1168PWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB1168 Samples SN65C1168PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CB1168 Samples SN75C1167DB ACTIVE SSOP DB 16 80 RoHS & Green NIPDAU Level-1-260C-UNLIM CA1167 Samples SN75C1167DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CA1167 Samples SN75C1167N LIFEBUY PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75C1167N SN75C1167NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C1167 Samples SN75C1167NSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C1167 Samples SN75C1167PWR LIFEBUY TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM CA1167 SN75C1168DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CA1168 Samples SN75C1168N LIFEBUY PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75C1168N SN75C1168NE4 LIFEBUY PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75C1168N SN75C1168NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C1168 Samples SN75C1168NSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75C1168 Samples SN75C1168PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CA1168 Samples SN75C1168PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CA1168 Samples SN75C1168PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 CA1168 Samples Addendum-Page 1

www.ti.com 17-Jun-2023 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65C1167NSR SO NS 16 2000 356.0 356.0 35.0 SN65C1168NSR SO NS 16 2000 356.0 356.0 35.0 SN65C1168PWR TSSOP PW 16 2000 356.0 356.0 35.0 SN75C1167DBR SSOP DB 16 2000 356.0 356.0 35.0 SN75C1167NSR SO NS 16 2000 356.0 356.0 35.0 SN75C1168DBR SSOP DB 16 2000 356.0 356.0 35.0 SN75C1168NSR SO NS 16 2000 367.0 367.0 38.0 SN75C1168PWR TSSOP PW 16 2000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) SN65C1168N N PDIP 16 25 506 13.97 11230 4.32 SN65C1168PW PW TSSOP 16 90 530 10.2 3600 3.5 SN65C1168PWG4 PW TSSOP 16 90 530 10.2 3600 3.5 SN75C1167DB DB SSOP 16 80 530 10.5 4000 4.1 SN75C1167N N PDIP 16 25 506 13.97 11230 4.32 SN75C1168N N PDIP 16 25 506 13.97 11230 4.32 SN75C1168NE4 N PDIP 16 25 506 13.97 11230 4.32 SN75C1168PW PW TSSOP 16 90 530 10.2 3600 3.5 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 8.2

7.4 TYP

14X 1.27 16X 0.51 0.35 8.89

0.15 TYP

0.3 0.1

2.00 MAX

(1.25) 0.25 GAGE PLANE 1.05 0.55 A 10.4 10.0 NOTE 3 B 5.4 5.2 NOTE 4 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 1 16

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

14X (1.27) (R0.05) TYP (7) 16X (1.85) 16X (0.6) 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:7X SYMM 8 9 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN (7)(R0.05) TYP 16X (1.85) 16X (0.6) 14X (1.27) 4220735/A 12/2021 SOP - 2.00 mm max heightNS0016A SOP NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.38 0.22 8.2 0.25 GAGE PLANE 0 -8

2 MAX

0.25 0.09 B 5.6 5.0 NOTE 4 A 6.5 5.9 NOTE 3 0.95 0.55 SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT 16X (1.85) 16X (0.45) 14X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.85) 16X (0.45) 14X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0016A SMALL OUTLINE PACKAGE 4220763/A 05/2022 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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