C868

C868 INFINEON | Alldatasheet

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Never stop thinking. Microcontrollers Data Sheet, V 1.0, May 2003 C868 8-Bit Single-Chip Microcontroller

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V 1.0, May 2003 Never stop thinking. C868 8-Bit Single-Chip Microcontroller

Revision History: 2003-05 V 1.0 Previous Version: - Page Subjects (major changes since last revision) Current data updated Description of I2C included We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

Data Sheet 5 V 1.0, 2003-05 C8688-Bit Single-Chip Microcontroller C800 Family C868 Advance Information

• C800 core : –Fully compatible to standard 8051 microcontroller –Superset of the 8051 architecture with 8 datapointers  40 MHz internal CPU clock –external clock of 6.67 - 10.67 MHz at 50% duty cycle –300 ns instruction cycle time (@37.5 MHz CPU clock)  8 Kbyte on-chip Program ROM for C868-1R and 8 KByte on-chip Program RAM for C868-1S  In-system programming support for programming the XRAM(C868-1R) or XRAM/ Program RAM(C868-1S) –This feature is realized through 4KB Boot ROM  256 byte on-chip RAM  256 byte on-chip XRAM (further features are on the next page) Figure 1 C868 Functional Units 8-bit UART I/O XRAM 256 × 8 Timer 2 Watchdog Timer Port 1 5-bit I/O 8-bit Port 3 CPU 8 datapointers 8-Bit ADC 16-bit Capture/ RAM 256 × 8 Boot ROM 4K x 8 Compare Unit Timer 0 Timer 1 Analog/ ROM/RAM 8K × 8 Digital Input 16-bit Compare Unit Input 3-bit

Data Sheet 6 V 1.0, 2003-05  One 8-bit and one 5 bits general purpose push-pull I/O ports – Enhanced sink current of 10 mA on Port 1/3 (total max current of 43 mA @ 100oC)  Three 16-bit timers/counters –Timer 0 / 1 (C501 compatible) –Timer 2 (up/down counter feature) –Timer 1 or 2 can be used for serial baudrate generator  Capture/compare unit for PWM signal generation –3-channel, 16-bit capture/compare unit –1-channel, 16-bit compare unit  Full duplex serial interface (UART)  5 channel 8-bit A/D Converter – Start of conversion can be synchronized to capture/compare timer 12/13.  13 interrupt vectors with four priority levels  Programmable 16-bit Watchdog Timer  Brown out detection  Power Saving Modes –Slow-down mode –Idle mode (can be combined with slow-down mode) –Power-down mode with wake up capability through INT0 or RxD pins.  Single power supply of 3.3V, internal voltage regulator for core voltage of 2.5V.  P-DSO-28-1, P-TSSOP-38-1 packages  Temperature ranges: SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868-1RG BA, SAF-C868-1SG BA , SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868A-1RG BA, SAF-C868A-1SG BA, SAF-C868P-1SR BA, SAF-C868P-1SG BA TA = – 40 to 85 oC SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868-1RG BA, SAK-C868-1SG BA , SAK-C868A-1RR BA, SAK-C868A-1SR BA, SAK-C868A-1RG BA, SAK-C868A-1SG BA, SAK-C868P-1SR BA, SAK-C868P-1SG BA TA = – 40 to 125 oC

Data Sheet 7 V 1.0, 2003-05 Figure 2 Logic Symbol Port 1 5-bit Digital I/O Port 3 8-bit Digital I/O

5 ADC channels

4 External

Data Sheet 9 V 1.0, 2003-05 Table 1 Pin Definitions and Functions Symbol Pin Numbers I/O*) Function DSO- TSSOP- P1.0– P1.4 P1.5- P1.7 12-8 15-17 6,4-1 11-13 I/O I Port 1 is a combination of 5 bits of push-pull bidirectional I/ O ports and 3 bits of input ports. As alternate digital functions, port 1 contains the interrupt 3, timer 2 overflow flag, receive data input and transmit data output of serial interface. The alternate functions are assigned to the pins of port 1 as follows: P1.0/TxD Transmit data of serial interface P1.1/EXF2 Timer 2 overflow flag P1.2 P1.3/INT3 Interrupt 3 P1.4/RxD Receive data of serial interface, Use as wakeup source from powerdown if bit WS of PMCON0 is set. The input ports are also interrupt ports, input to the timer2, CCU6 modules and ADC: 15 11 I P1.5/Input to Counter 2/External Interrupt 0 Input/ Analog Input Channel 0 External interrupt input or Hall input signal, counter 2 input or input channel 0 to the ADC unit. Use as wakeup source from powerdown if bit WS of PMCON0 is cleared. 16 12 I P1.6/Timer 2 Trigger/External Interrupt 1 Input/ Analog Input Channel 1 External interrupt input or Hall input signal, input channel 1 to the ADC unit, trigger to Timer 2. 17 13 I P1.7/External Interrupt 2 Input/ Analog Input Channel 2 External interrupt input or Hall input signal and input channel 2 to the ADC unit. *)I=Input O=Output

Data Sheet 10 V 1.0, 2003-05 P3.0– P3.7 2,3,23, 24,1, 22,5,6 32,33,25, 26,31,24, 36,37 I/O Port 3 is an 8-bit push-pull bidirectional I/O port. This port also serves as alternate functions for the CCU6 functions. The functions are assigned to the pins of port 3 as follows : P3.0/COUT63 16 bit compare channel output P3.1/CTRAP CCU trap input P3.2/COUT62 Output of capture/compare ch 2 P3.3/CC62 Input/output of capture/compare ch 2 P3.4/COUT61 Output of capture/compare ch 1 P3.5/CC61 Input/output of capture/compare ch 1 P3.6/COUT60 Output of capture/compare ch 0 P3.7/CC60 Input/output of capture/compare ch 0 V AREF 19 15 – Reference voltage for the A/D converter. VAGND 18 14 – Reference ground for the A/D converter. AN4 21 17 I Analog Input Channel 4 is input channel 4 to the ADC unit. AN3 20 16 I Analog Input Channel 3 is input channel 3 to the ADC unit. RESET 73 8 I RESET A low level on this pin for two machine cycle while the oscillator is running resets the device. ALE/BSL 4 34 I/O Address Latch Enable/Bootstrap Mode A low level on this pin during reset allows the device to go into the bootstrap mode. After reset, this pin will output the address latch enable signal. The ALE can be disabled by bit EALE in SFR SYSCON0. V SSP 14 10 – IO Ground (0V) VDDP 13 9 – IO Power Supply (+3.3V) *)I=Input O=Output Table 1 Pin Definitions and Functions Symbol Pin Numbers I/O*) Function DSO- TSSOP-

Data Sheet 11 V 1.0, 2003-05 VSSC 25 27 – Core Ground (0V) VDDC 26 28 O Core Internal Reference (+2.5V) Connect 2*68 - 470nF ceramic capacitor across this pin and core ground. NC – 5,7,8,18, 19,20,21, 22,23,35 – Not connected XTAL1 27 29 I XTAL1 Output of the inverting oscillator amplifier. XTAL2 28 30 O XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generation circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. *)I=Input O=Output Table 1 Pin Definitions and Functions Symbol Pin Numbers I/O*) Function DSO- TSSOP-

Data Sheet 12 V 1.0, 2003-05 Figure 5 Block Diagram of the C868 Programmable Watchdog Timer Port 3 5-bit Port 1 OSC CPU Timer 0 Timer 1 Timer 2 UART RESET C868VSSC VDDC A/D Converter 8-Bit 8k x 8 ROM/ 256 x 8 XRAM 256 x 8 RAM Capture/Compare Unit Interrupt Unit 4 external interrupts Port 1 Port 3 digital I/O I/O 8-bit digital RAM Boot/ Self Test ROM 4k x 8 XTAL2 XTAL1 VAREF VAGND VDDP VSSP 5-Bit Analog In PLL 8 datapointers and 3-bit digital input

Data Sheet 13 V 1.0, 2003-05 CPU The C868 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 10.67 MHz external crystal (giving a 40MHz CPU clock), 58% of the instructions execute in 300 ns. PSW Program Status Word Register [Reset value: 00 H ] D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H CY AC F0 RS1 RS0 OV F1 P rwh rwh rw rw rw rwh rw rwh Field Bits Typ Description P 0r w h Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. F1 1r w General Purpose Flag OV 2r w h Overflow Flag Used by arithmetic instructions. RS0 RS1 rw Register Bank select control bits These bits are used to select one of the four register banks. F0 5r w General Purpose Flag AC 6r w h Auxiliary Carry Flag Used by instructions which execute BCD operations. CY 7r w h Carry Flag Used by arithmetic instructions. Table 2 : RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH

Data Sheet 15 V 1.0, 2003-05 The various chip modes supported are shown in Figure 6. Figure 6 Entry and exit of Chip Modes A valid hardware reset would, of course, override any of the above entry or exit procedures. Table 0-1 Hardware and Software Selection of Chipmodes Operating Mode (Chipmode) Hardware Selection Software Selection Normal Mode ALE/BSL pin = high RESET rising edge ALE/BSL = don’t care; setting bits BSLEN, SWAP = 0,0; execute unlocking sequence Normal XRAM Mode Not possible setting bits BSLEN,SWAP = 0,1; execute unlocking sequence Bootstrap XRAM Mode Not possible setting bits BSLEN,SWAP = 1,1; execute unlocking sequence Bootstrap Mode ALE/BSL pin = low RESET rising edge ALE/BSL = don’t care; setting bits BSLEN, SWAP = 1,0; execute unlocking sequence Normal Mode Normal XRAM Bootstrap Mode Hardware Software Bootstrap XRAM Mode Mode

Data Sheet 16 V 1.0, 2003-05 Table 3 Normal Memory Configuration Chip Mode Memory Space Memory Boundary Normal Code Space ROM/RAM: 0000 H to 1FFFH Internal Data Space XRAM: FF00H to FFFFH Bootstrap Code Space Boot ROM: 0000 H to 0FFFH Internal Data Space XRAM: FF00H to FFFFH ROM/RAM: 0000 H to 1FFFH Normal XRAM Code Space XRAM: FF00 H to FFFFH Data Space ROM/RAM: 0000 H to 1FFFH Bootstrap XRAM Code Space Boot ROM: 0000 H to 0FFFH XRAM: FF00 H to FFFFH Data Space ROM/RAM: 0000 H to 1FFFH

Data Sheet 17 V 1.0, 2003-05 Bootstrap loader The C868, includes a bootstrap mode, which is activated by setting the ALE/BSL pin at logic low with a pulldown and TxD pin at logic high with a pullup at the rising edge of the RESET . Or it can be entered by software, that is by setting BSLEN bit and resetting SWAP bit in SFR SYSCON1 accompany by an unlock sequence. In the bootstrap mode, software routines of the bootstrap loader located in the boot ROM will be executed. Its purpose is to allow the easy and quick programming of the internal SRAM (0000 H to 1FFFH ) or XRAM (FF00H to FFFFH ) via serial interface (UART) while the MCU is in-circuit. It also provides a way to program SRAM or XRAM through bootstrapping from an external SPI or I2C EEPROM. The first action of the bootstrap loader is to detect the presence of EEPROM and its type, SPI or I2C, and check the first byte of the serial EEPROM. If the first byte is 0A5H , the MCU would enter Phase A to download from the EEPROM. Otherwise, it will enter Phase B to establish a serial communication with the connected host. Bootstrapping from the serial EEPROM can also be done in phase B if it is invoked by the host. Phase B consists of two functional parts that represent two phases:  Phase I: Establish a serial connection and automatically synchronize to the transfer speed (baud rate) of the serial communication partner (host).  Phase II: Perform the serial communication with the host. The host controls the communication by sending special header information, which select one of the working modes. These modes are: The phases of the bootstrap loader are illustrated in Figure 7. Table 4 Serial Communication Modes of Phase B Modes Description

0 Transfer a customer program from the host to the SRAM (0000

1FFF H ) or XRAM (FF00H -FFFFH ). Then return to the beginning of phase II and wait for the next command from the host. 1 Execute a customer program in the XRAM at start address FF00 H . 2 Execute a customer program in the SRAM at start address 0000 H .

3 Transfer a customer program from the SPI EEPROM to the SRAM

(0000H to 1FFFH ) or XRAM (FF00 H -FFFFH ). Then return to the beginning of phase II and wait for the next command from the host.

4 Transfer a customer program from the I2C EEPROM to the SRAM

(0000H to 1FFFH ) or XRAM (FF00 H -FFFFH ). Then return to the beginning of phase II and wait for the next command from the host. 5-9 reserved

Data Sheet 19 V 1.0, 2003-05 Figure 9 EEPROM connections for a) SPI and b) I2C /CS SCK SI SO /HOLD /WP VCC GN D240R P1.3 P1.1 P1.2 GN D VCC WP SCL SDA P1.1 P1.2 3K3 VCC VCC b) I2C EEPROM c onnectiona) SPI EEPROM connection

Data Sheet 21 V 1.0, 2003-05 Clock system The C868 clock system consist of the on-chip oscillator, PLL and multiplexer stage. The programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a the PLL output to the output from the SDD when slowdown mode is selected. Figure 11 Block Diagram of the Clock Generation On-Chip Osc clkin clkoutfOSC XTAL1 XTAL2 PLL SDD MUX system clock (fSYS ) fPLL

Data Sheet 22 V 1.0, 2003-05 The PLL output frequency is determined by: [1] The range for the VCO frequency is given by:

100 MHz ≤ fVCO ≤ 160 MHz [2]

The relationship between the input frequency and VCO frequency is given by: [3] This gives the range for the input frequency which is given by: 6.67 MHz ≤ fOSC ≤ 10.67 MHz [4] Table 5 Output Frequencies fPLL Derived from Various Output Factors K-Factor fPLL Duty Cycle [%] Jitter Selected Factor KDIV f VCO =

100 MHz

fVCO =

160 MHz

2 000 B 50 80 50 linear depending on f VCO at fVCO =100MHz: +/-300ps at fVCO =160MHz: +/-250ps additional jitter for odd Kdiv factors tbd. 4 010 B 25 40 50 51) 1) These odd factors should not be used (not tested because off the unsymmetrical duty cycle). 2) Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz. 011B 20 32 40 6 100 B 16.67 26.67 50 8 101 B 12.5 20 50 91) 110B 11.11 17.78 44 10 111 B 10 16 50 16 001 B 6.25 10 50 fPLL = fVCO / K = × fOSC K fVCO =1 5× fOSC

Data Sheet 25 V 1.0, 2003-05

0.1 Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. For accessing the mapped special function area, bit RMAP in special function register SYSCON0 must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). As long as bit RMAP is set, the mapped special function register area can be accessed. This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. The 109 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All available SFRs whose there are 128 directly addressable bits within the SFR area. All SFRs are listed in Table 6 and Table 7.In Table 6 they are organized in groups which refer to the functional blocks of the C868-1R, C868-1S. Table 7 illustrates the contents (bits) of the SFRs SYSCON0 System Control Register 0 [Reset value: XX10XXX1 B ] 76543210 -- EALE RMAP - - - XMAP0 r r rw rw r r r rw The functions of the shaded bits are not described here Field Bits Typ Description RMAP 4r w Special Function Register Map Control RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. - [7:2] r reserved; returns ’0’ if read; should be written with ’0’;

Data Sheet 26 V 1.0, 2003-05 Table 6 Special Function Registers - Functional Blocks Block Symbol Name Add- ress

Contents

B DPH DPL DPSEL PSW SP SCON SBUF IEN0 IEN1 IEN2 IP0 IP1 TCON TMOD TL0 TL1 TH0 TH1 PCON Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer Serial Channel Control Register Serial Data Buffer Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 interrupt Priority Register 1 Timer 0/1 Control Register Timer Mode Register Timer 0, Low Byte Timer 1, Low Byte Timer 0, High Byte Timer 1, High Byte Power Control Register H F0H 83H 82H 84H D0 H 81H 98H 99H A8 H A9H AA H B8 H AC H 88H 89H 8AH 8BH 8C H 8D H 87H 00H 00H 00H 00H 00H 00H 07H 00H 00H 0X000000B XXXXX000 B XX0000XX B XX000000 B XX000000 B 00H 00H 00H 00H 00H 00H 0XXX0000 B Sys- tem PMCON0 CMCON EXICON IRCON0 IRCON1 PMCON1 PMCON2 SCUWDT VERSION SYSCON0 SYSCON1 Wake-up Control Register Clock Control Register External Interrupt Control Register External Interrupt Request Register Peripheral Interrupt Request Register Peripheral Management Ctrl Register Peripheral Management Status Register SCU/Watchdog Control Register ROM Version Register System Control Register 0 System Control Register 1 H 8FH 91H 92H 93H E8H F8H C0 H F9H AD H AF H XXX00000 B 10011111B XXXXXX00 B XXXXXX00 B XX0000X0 B XXXXX000 B XXXXX000 B X0X00000 B 00H XX10XXX1 B 00XXX0X0 B 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0

Data Sheet 27 V 1.0, 2003-05 A/D- Con- verter ADCON0 ADCON1 ADDATH A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register D8 H D9 H DB H 00H XX000000 B 00H Ports P1 4) P1DIR 3) P3 4) P3DIR 3) P3ALT P1ALT Port 1 Register Port 1 Direction Register Port 3 Register Port 3 Direction Register Port 3 Alternate Function Register Port 1 Alternate Function Register H 90H B0 H B0 H B1H B4H FFH FFH FFH FFH 00H XXX00X00 B Watch dog WDTCON WDTREL WDTL WDTH Watchdog Timer Control Register Watchdog Timer Reload Register Watchdog Timer, Low Byte Watchdog Timer, High Byte A2H A3H B2H B3H XXXXXX00 B 00H 00H 00H Timer T2CON T2MOD RC2H RC2L T2H T2L Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture, High Byte Timer 2 Reload/Capture, Low Byte Timer 2, High Byte Timer 2, Low Byte H C9 H CB H CA H CD H CC H 00H XXXXXXX0 B 00H 00H 00H 00H 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 Table 6 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Add- ress

Data Sheet 28 V 1.0, 2003-05 Cap- ture/ Com- pare Unit T12L T12H T13L T13H T12PRL T12PRH T13PRL T13PRH CC60RL CC60RH CC61RL CC61RH CC62RL CC62RH CC63RL CC63RH T12DTCL T12DTCH CMPSTATL CMPSTATH CMPMODIFL CMPMODIFH TCTR0L TCTR0H TCTR2L TCTR4L 4) TCTR4H 4) ISL ISH PISELH Timer T12 Counter Register, Low Byte Timer T12 Counter Register, High Byte Timer T13 Counter Register, Low Byte Timer T13 Counter Register, High Byte Timer T12 Period Register, Low Byte Timer T12 Period Register, High Byte Timer T13 Period Register, Low Byte Timer T13 Period Register, High Byte Capture/Compare Ch 0 Reg, Low Byte Capture/Compare Ch 0 Reg, High Byte Capture/Compare Ch 1 Reg, Low Byte Capture/Compare Ch 1 Reg, High Byte Capture/Compare Ch 2 Reg, Low Byte Capture/Compare Ch 2 Reg, High Byte T13 Compare Register, Low Byte T13 Compare Register, High Byte Timer T12 Dead Time Ctrl, Low Byte Timer T12 Dead Time Ctrl, High Byte Compare Timer Status, Low Byte Compare Timer Status, High Byte Compare Timer Modification, Low Byte Compare Timer Modification, High Byte Timer Control Register 0, Low Byte Timer Control Register 0, High Byte Timer Control Register 2, Low Byte Timer Control Register 4, Low Byte Timer Control Register 4, High Byte Cap/Com Interrupt Register, Low Byte Cap/Com Interrupt Register, High Byte Port Input Selector Register, High Byte EC H ED H EE H EF H DE H DF H D2 H D3 H C2 H C3 H C4 H C5 H C6 H C7 H D4 H D5 H E6H E7H F4H F5H EA H EB H E2H E3H F2H F2H F3H E4H E5H BB H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 Table 6 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Add- ress

Data Sheet 29 V 1.0, 2003-05 Cap- ture/ Com- pare Unit ISSL ISSH3) ISRL4) ISRH 4) INPL3) INPH 3) IENL4) IENH 4) CC60SRL CC60SRH CC61SRL CC61SRH CC62SRL CC62SRH CC63SRL CC63SRH MODCTRL MODCTRH 3) TRPCTRL TRPCTRH PSLRL MCMOUTL MCMOUTH 3) MCMOUTSL 4) MCMOUTSH 4) MCMCTRLL 4) T12MSELL T12MSELH Cap/Com Int Status Set Reg, Low Byte Cap/Com Int Status Set Reg, High Byte Cap/Com Int Status Reset Reg, Low Byte Cap/Com Int Status Reset Reg,High Byte Cap/Com Int Node Ptr Reg, Low Byte Cap/Com Int Node Ptr Reg, High Byte Cap/Com Interrupt Register, Low Byte Cap/Com Interrupt Register, High Byte Cap/Com Channel 0 Shadow, Low Byte Cap/Com Channel 0 Shadow, High Byte Cap/Com Channel 1 Shadow, Low Byte Cap/Com Channel 1 Shadow, High Byte Cap/Com Channel 2 Shadow, Low Byte Cap/Com Channel 2 Shadow, High Byte T13 Compare Shadow Reg, Low Byte T13 Compare Shadow Reg, High Byte Modulation Control Register, Low Byte Modulation Control Register, High Byte Trap Control Register, Low Byte Trap Control Register, High Byte Passive State Level Register, Low Byte MCM Output Register, Low Byte MCM Output Register, High Byte MCM Output Shadow Register, Low Byte MCM Output Shadow Register,High Byte MCM Control Register, Low Byte T12 Cap/Com Mode Sel Reg, Low Byte T12 Cap/Com Mode Sel Reg, High Byte BC H BD H BC H BD H BE H BF H BE H BF H FA H FB H FC H FD H FE H FFH B6H B7H D6 H D7 H CE H CF H A6H DC H DD H DC H DD H D6 H F6H F7H 00H 00H 00H 00H 40H 39H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0 Table 6 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Add- ress

Data Sheet 30 V 1.0, 2003-05 Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 84H DPSE L 87H PCON 0XX0 0000B SMOD –– SD GF1 GF0 PDE IDLE 88H TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD 00 H GATE C/NT1 M1(1) M0(1) GATE C/NT0 M1(0) M0(0) 8EH PMCO XXX0 0000B ––– EBO BO SDST AT WS EPWD 8FH CMCO N 1001 1111B KDIV2 KDIV1 KDIV0 REL4 REL3 REL2 REL1 REL0 90H 90H 91H EXICO N XXXX XX00 B 92H IRCO XXXX XX00 B EXINT 93H IRCO XX00 00X0B –– INP3 INP2 INP1 INP0 – IADC 98H SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers

Data Sheet 31 V 1.0, 2003-05 A2H WDTC ON XXXX XX00 B N A3H WDTR EL A6H PSLRL 00 H PSL63 – PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 A8H IEN0 0X00 0000B EA – ET2 ES ET1 EX1 ET0 EX0 A9H IEN1 XXXX X000B AA H IEN2 XX00 00XX B –– EINP3 EINP2 EINP1 EINP0 –– AC H IP1 XX00 0000B AD H SYSC ON0 XX10 XXX1 B AF H SYSC ON1 00XX X0X0 B ESWC SWC _ _ _ BSLE N _S W A P B0H B0H B1H P3ALT 00 H CC60 COUT CC61 COUT CC62 COUT CTRA P COUT B4H P1ALT XXX0 0X00B ___R x D I N T 3 _E X F 2 T x D B6H CC63 SRL B7H CC63 SRH 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Data Sheet 32 V 1.0, 2003-05 B8H IP0 XX00 0000B BB H PISEL H 00H –– ISPOS 2.1 ISPOS 2.0 ISPOS 1.1 ISPOS 1.0 ISPOS 0.1 ISPOS 0.0 BC H 3) ISSL 00 H ST12P M ST12O M SCC62 F SCC62 R SCC61 F SCC61 R SCC60 F SCC60 R BC H 2) ISRL 00 H RT12P M RT12O M RCC6 RCC6 RCC6 RCC6 RCC6 RCC6 BD H 3) ISSH 00 H – SIDLE SWHE SCHE – STRP F ST13P M ST13C M BD H 2) ISRH 00 H – RIDLE RWHE RCHE – RTRP F RT13P M RT13C M BE H 2) IENL 00 H ENT12 PM ENT12 OM ENCC 62F ENCC 62R ENCC 61F ENCC 61R ENCC 60F ENCC 60R BE H 3) INPL 00 H INPCH E.1 INPCH E.0 INPCC 62.1 INPCC 62.0 INPCC 61.1 INPCC 61.0 INPCC 60.1 INPCC 60.0 BF H 2) IENH 00 H – ENIDL E ENWH E ENCH E – ENTR PF ENT13 PM ENT13 CM BF H 3) INPH 00 H –– INPT1 3.1 INPT1 3.0 INPT1 2.1 INPT1 2.0 INPER R.1 INPER R.0 C0 H SCUW DT 00H – PLLR – WDTR WDTE OI WDTD IS WDTR S WDTR E H CC60 RL C3 H CC60 RH C4 H CC61 RL C5 H CC61 RH 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Data Sheet 33 V 1.0, 2003-05 C6 H CC62 RL C7 H CC62 RH C8 H T2CO N 00H TF2 EXF2 RCLK TCLK EXEN TR2 C/T2 CP/ RL2 C9 H T2MO D XXXX XXX0 B CE H TRPC TRL TRPM TRPM CF H TRPC TRH 00H TRPP EN TRPE N13 TRPE TRPE TRPE TRPE TRPE TRPE D0 H PSW 00H CY AC F0 RS1 RS0 OV F1 P D2 H T13PR L D3 H T13PR H D4 H CC63 RL D5 H CC63 RH D6 H 2) MCMC TRLL 00H –– SWSY SWSY – SWSE SWSE SWSE D6 H 3) MODC TRL 00H MCME N – T12M ODEN T12M ODEN T12M ODEN T12M ODEN T12M ODEN T12M ODEN 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Data Sheet 34 V 1.0, 2003-05 D7 H 3) MODC TRH 00H ECT13 O – T13M ODEN T13M ODEN T13M ODEN T13M ODEN T13M ODEN T13M ODEN D8 H ADCO 00H ADST ADBS Y ADM1 ADM0 CCU- ADEX ADCH ADCH ADCH H ADCO XX00 0000B –– ADST ADST ADST ADCT ADCT ADCT DB H ADDA TH DC H 3) MCMO UTL 00H – RM C M P MCMP MCMP MCMP MCMP MCMP DC H 2) MCMO UTSL 00H STRM CM – MCMP MCMP MCMP MCMP MCMP MCMP DD H 3) MCMO UTH 00H –– CURH CURH CURH EXPH EXPH EXPH DD H 2) MCMO UTSH 00H STRH P – CURH CURH CURH EXPH EXPH EXPH DE H T12PR L DF H T12PR H E2H TCTR 00H CTM CDIR STE12 T12R T12PR E T12CL T12CL T12CL E3H TCTR 10H –– STE13 T13R T13PR E T13CL T13CL T13CL E4H ISL 00 H T12PM T12O M ICC62 F ICC62 R ICC61 F ICC61 R ICC60 F ICC60 R E5H ISH 00 H – IDLE WHE CHE TRPS TRPF T13PM T13C M 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Data Sheet 35 V 1.0, 2003-05 E6H T12DT CL 00H – DTM5 DTM4 DTM3 DTM2 DTM1 DTM0 E7H T12DT CH 00H – DTR2 DTR1 DTR0 – DTE2 DTE1 DTE0 E8H PMCO XXXX X000 B S T2DIS ADCDI S EA H CMPM ODIFL 00H – MCC6 ––– MCC6 MCC6 MCC6 EB H CMPM ODIFH 00H – MCC6 ––– MCC6 MCC6 MCC6 F2H 2) TCTR 00H T12ST D T12ST R –– DTRE S T12RE S T12RS T12RR F2H 3) TCTR 00H – T13TE T13TE T13TE T13TE T13TE T13SS C T12SS C F3H 2) TCTR 00H T13ST D T13ST R ––– T13RE S T13RS T13RR F4H CMPS TATL 00H – CC63S T ––– CC62S T CC61S T CC60S T F5H CMPS TATH 00H T13IM COUT 63PS COUT 62PS CC62P S COUT 61PS CC61P S COUT 60PS CC60P S F6H T12M SELL 00H MSEL 613 MSEL 612 MSEL 611 MSEL 610 MSEL 603 MSEL 602 MSEL 601 MSEL 600 F7H T12M SELH 00H –––– MSEL 623 MSEL 622 MSEL 621 MSEL 620 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Data Sheet 36 V 1.0, 2003-05 F8H PMCO XXXX X000 B T T2ST ADCS T H VERSI ON 00H PROT VER6 VER5 VER4 VER3 VER2 VER1 VER0 FA H CC60 RL FB H CC60 RH FC H CC61 RL FD H CC61 RH FE H CC62 RL FFH CC62 RH 1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers Table 7 Contents of the SFRs, SFRs in numeric order of their addresses Addr Reg- ister Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Data Sheet 37 V 1.0, 2003-05 Ports The C868 has two kinds of ports. The first kind is push-pull ports instead of the traditional quasi-bidirectional ports. The ports belonging to this kind are lsb of port 1 which is a 5- bit I/O port and port 3 which is an eight-bit I/O port. When configured as inputs, these ports will be high impedance with Schmitt trigger feature. Port 3 is alternate for capture/ compare functions whereas, port 1 has alternate functions for some of the pins. The second kind is input ports which are shared by msb of port 1 which is a 3-bit input port, the interrupts, timer 2 inputs, capture/compare hall inputs and analog inputs.

Data Sheet 38 V 1.0, 2003-05 Timer 0 and 1 Timer 0 and 1 can be used in four operating modes as listed in Table 8: The register is incremented every machine cycle. Since the machine cycle consist of twelve oscillator periods, the count rate is 1/12th of the system frequency. External inputs INT0 and INT1 can be programmed to function as a gate to facilitate pulse width measurements. Figure 15 illustrates the input clock logic. Figure 15 Timer 0 and 1 Input Clock Logic Table 8 Timer 0 and 1 Operating Modes Mode Description TMOD System Clock M1 M0 0 8-bit timer with a divide-by-32 prescaler 0 0 fSYS /(12*32) 1 16-bit timer 0 1 fSYS /12 2 8-bit timer with 8-bit autoreload 1 0

3 Timer 0 used as one 8-bit timer and one 8-bit

C/T = 0 Timer 0/1 TR0 Control Gate INT0 fSYS ÷ 12 Pin Input Clock

Data Sheet 39 V 1.0, 2003-05 Timer/Counter 2 with Compare/Capture/Capture Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating modes:  16-bit auto-reload mode (up or down counting)  16-bit capture mode  Baudrate generator Note: denotes a falling edge Table 9 Timer/Counter 2 Operating Modes Mode T2CON T2MOD T2CON T2EX Remarks System Clock RCLK or TCLK CP/ RL2 TR2 DCEN EXEN Inte- rnal 16-bit Auto- reload 0010 0 Xr e l o a d u p o n overflow fSYS /12 max fSYS /240 0 X 0 1 reload trigger (falling edge)

0011 X 0d o w n c o u n t i n g

0011 X 1u p c o u n t i n g

011X 0 X1 6 - b i t T i m e r / Counter (only up-counting) fSYS /12 max fSYS /24 011X 1 c a p t u r e T2H,T2L-> RC2H,RC2L Baudrate Generator 1X1X 0 Xn o o v e r f l o w interrupt request(TF2) fSYS 1X1X 1 e x t r a e x t e r n a l interrupt (“Timer 2“) off X X 0 X X X Timer 2 stops - -

Data Sheet 40 V 1.0, 2003-05 Serial Interface (UART) The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. The serial port can operate in 3 modes as illustrated in Table 10. For clarification, some terms regarding the difference between “baudrate clock“ and “baudrate“ should be mentioned. The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization. Therefore, the baudrate generators must provide a “baudrate clock“ to the serial interface which divides it by 16, thereby resulting in the actual “baudrate“. Table 10 UART Operating Modes Mode SCON Description SM1 SM0 0 0 0 Reserved 1 0 1 8-bit UART, variable baudrate 10 bits are transmitted (through TxD) or received (RxD) 2 1 0 9-bit UART, fixed baudrate 11 bits are transmitted (through TxD) or received (RxD) 3 1 1 9-bit UART, variable baudrate Similar to mode 2, except for the variable baudrate.

Data Sheet 41 V 1.0, 2003-05 The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be determined by Timer 1 or by Timer 2 or both (one for transmit, the other for receive. Table 11 Serial Interface - Baud Rate Dependencies Serial Interface Operating Modes Active Control Bits Baud Rate Calculation TCLK/ RCLK SMOD Mode 1 (8-bit UART) Mode 3 (9-bit UART) 0 x Controlled by timer 1 overflow: (2SMOD × Timer 1 overflow rate) / 32 1 x Controlled by baud rate generator (2SMOD × Timer 21) overflow rate) / 32 1) Timer 2 functioning as baudrate generator Mode 2 (9-bit UART)– 0 fSYS / 64 1 fSYS / 32

Data Sheet 42 V 1.0, 2003-05 Capture/Compare Unit (CCU6) The CCU6 provides two independent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features  Three capture/compare channels, each channel can be used either as capture or as compare channel.  Generation of a three-phase PWM supported (six outputs, individual signals for highside and lowside switches)  16 bit resolution, maximum count frequency = system clock  Dead-time control for each channel to avoid short-circuits in the power stage  Concurrent update of the required T12/13 registers  Center-aligned and edge-aligned PWM can be generated  Single-shot mode supported  Many interrupt request sources  Hysteresis-like control mode Timer 13 Features  One independent compare channel with one output  16 bit resolution, maximum count frequency = system clock  Can be synchronized to T12  Interrupt generation at period-match and compare-match  Single-shot mode supported Additional Features  Block commutation for Brushless DC-drives implemented  Position detection via Hall-sensor pattern  Automatic rotational speed measurement for block commutation  Integrated error handling  Fast emergency stop without CPU load via external signal (CTRAP)  Control modes for multi-channel AC-drives  Output levels can be selected and adapted to the power stage  Capture/compare unit can be powerdown in normal, idle and slow-down modes The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. The timer T13 can work in compare mode only. The multi- channel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation.

Data Sheet 44 V 1.0, 2003-05 Dead-time Generation The dead-time generation logic is built in a similar way for all three channels of T12. Each of the three channels works independently with its own dead-time counter and the trigger and enable signals. Figure 18 Dead-time generation for centre and edge aligned modes Capture Mode In capture mode the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x. A rising and/or a falling edge on the pins CC6x can be selected as capture event, that is used to transfer the contents of timer T12 to the CC6xR and CC6xSR registers. In order to work in capture mode, the capture pins have to be configured as inputs. T12 CC6xST DTCx_o CC6x (CC6xPS=0) CC6xST COUT6x (CC6xPS=0) T12 Centre-aligned Edge-aligned

Data Sheet 46 V 1.0, 2003-05 Synchronization of T13 to T12 The timer T13 can be synchronized on a T12 event. Combined with the single shot mode, this feature can be used to generate a programmable delay after a T12 event. Synchronization of T13 to T12 Multi-channel Mode The multi-channel mode offers a possibility to modulate all six T12-related output signals within one instruction. The bits in bit field MCMP are used to select the outputs that may become active. If the multi-channel mode is enabled (bit MCMEN=’1’), only those outputs may become active, which have a ’1’ at the corresponding bit position in bit field MCMP. This bit field has its own shadow bit field MCMPS, which can be written by SW. The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events. This structure permits the SW to write the new value, which is then taken into account by the HW at a well-defined moment and synchronized to a PWM period. This avoids unintended pulses due to unsynchronized modulation sources (T12, T13, SW). 2T12 compare-match while counting up T13 T13R

Data Sheet 47 V 1.0, 2003-05 Trap Handling The trap functionality permits the PWM outputs to react on the state of the input pin CTRAP . This functionality can be used to switch off the power devices if the trap input becomes active (e.g. as emergency stop). Figure 21 Trap State Synchronization (with TRM2=’0’) CTRAP active T12 T13 sync. to T12 sync. to T13 no sync.TRPS TRPS TRPS TRPF

Data Sheet 48 V 1.0, 2003-05 Modulation control The modulation control part combines the different modulation sources, six T12-related signals from the three compare channels, the T13-related signal and the multi-channel modulation signals. each modulation source can be individually enabled for each output line. Furthermore, the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state (if enabled). Figure 22 Modulation Control example for CC60 and COUT60. T13 CC60 (MCMP0, no modulation) COUT60 (MCMP1, no modulation) COUT60 (T12, no modulation) CC60 (T12, no modulation) CC60 (MCMP0 modulated with T12) COUT60 (MCMP1 modulated with T12) CC60 (MCMP0 modulated with T12 and 13) COUT60 (MCMP1 modulated with T12 and T13)

Data Sheet 49 V 1.0, 2003-05 Hall Sensor Mode In Brushless-DC motors the next multi-channel state values depend on the pattern of the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the modulation pattern (MCMP). Because of different machine types the modulation pattern for driving the motor can be different. Therefore it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding modulation pattern. The CCU6 offers this by having a register which contains the actual Hall pattern (CURHS), the next expected Hall pattern (EXPHS) and its output pattern (MCMPS). At every correct Hall event (CHE, see figure Hall Event Actions) a new Hall pattern with its corresponding output pattern can be loaded (from a predefined table) by software into the register MCMOUTS. Loading this shadow register can also be done by a write action on MCMOUTS with bit STRHP = ’1’ The sampling of the Hall pattern (on CCPOSx) is done with the T12 clock. By using the dead-time counter DTC0 (mode MSEL6x= ’1000’) a hardware noise filter can be implemented to suppress spikes on the Hall inputs due to high di/dt in rugged inverter environment. In case of a Hall event the DTC0 is reloaded and starts counting. When the counter value of one is reached, the CCPOSx inputs are sampled (without noise and spikes) and are compared to the current Hall pattern (CURH) and to the expected Hall pattern (EXPH). If the sampled pattern equals to the current pattern the edge on CCPOSx was due to a noise spike and no action will be triggered (implicit noise filter). If the sampled pattern equals to the next expected pattern the edge on CCPOSx was a correct Hall event, the bit CHE is set which causes an interrupt and the resets T12 (for speed measurement, see description mode ’1000’ below). This correct Hall event can be used as a transfer request event for register MCMOUTS. The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as the next EXPH-pattern. In case of the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set which also can cause an interrupt and sets the IDLE mode clearing MCMP (modulation outputs are inactive). To restart from IDLE the transfer request of MCMOUTS have to be initiated by software (bit STRHP and bitfields SWSEL/SWSYN).

Data Sheet 50 V 1.0, 2003-05 Below is a table listing output (MCMP) for a BLDC motor. Block Commutation Control Table Mode CCPOS0- CCPOS2 Inputs CC60 - CC62 Outputs COUT60 - COUT62 Outputs CCP OS0 CCP OS1 CCP OS2 CC60 CC61 CC62 COUT6 COUT6 COUT6 Rotate left, 0° phase shift 1 0 1 inactive inactive active inactive active inactive 1 0 0 inactive inactive active active inactive inactive 1 1 0 inactive active inactive active inactive inactive 0 1 0 inactive active inactive inactive inactive active 0 1 1 active inactive inactive inactive inactive active 0 0 1 active inactive inactive inactive active inactive Rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive Slow down X X X inactive inactive inactive active active active Idle 1) In case of the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set which also can cause an interrupt and sets the IDLE mode clearing MCMP (modulation outputs are inactive). X X X inactive inactive inactive inactive inactive inactive

Data Sheet 51 V 1.0, 2003-05 For Brushless-DC motors there is a special mode (MSEL6x = ’1000b’) which is triggered by a change of the Hall-inputs (CCPOSx). This mode shows the capabilities of the CCU6. Here T12’s channel 0 acts in capture function, channel 1 and 2 in compare function (without output modulation) and the multi-channel-block is used to trigger the output switching together with a possible modulation of T13. After the detection of a valid Hall edge the T12 count value is captured to channel 0 (representing the actual motor speed) and resets the T12. When the timer reaches the compare value in channel 1, the next multi-channel state is switched by triggering the shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can be combined with several conditions which are necessary to implement a noise filtering (correct Hall event) and to synchronize the next multi-channel state to the modulation sources (avoiding spikes on the output lines). This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back-EMF technique is used instead of Hall sensors. The compare value in channel 2 can be used as a time-out trigger (interrupt) indicating that the motors destination speed is far below the desired value which can be caused by a abnormal load change. In this mode the modulation of T12 has to be disabled (T12MODENx = ’0’). Figure 0-2 Timer T12 Brushless-DC Mode (MSEL6x = 1000) capture event resets T12 ch0 gets captured value for act. speed ch1 compare for phase delay ch2 compare for timeout CC6x act. speedCC60 phase delayCC61 timeoutCC62 COUT6y 110001CCPOS2 CCPOS0 111 00 0 CCPOS1 001 11 0

Data Sheet 52 V 1.0, 2003-05 A/D Converter The C868 includes a high performance / high speed 8-bit A/D-Converter (ADC) with 5 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: – 5 multiplexed input channels, which can also be used as digital inputs – 8-bit resolution with TUE of +/- 2 LSB8. – Single or continuous conversion mode – Start of conversion by software and hardware – Interrupt request generation after each conversion – Using successive approximation conversion technique via a capacitor array – Powerdown in normal, idle and slow-down modes The ADC supports two conversion modes - single and continuous conversions. For each mode, there are two ways in which conversion can be started - by software and by the T13PM signal from the CCU module. Writing a ‘0’ to bit CCU_ADEX select conversion control by ADST. Writing a ’1’ to bit field ADST starts conversion on the channel that is specified by ADCH. In single conversion mode, bit field ADM is cleared to ’0’. This is the default mode selected after hardware reset. When a conversion is started, the channel specified is sampled. The busy flag ADBSY is set and ADST is cleared. When the conversion is completed, the interrupt request signal ADCIRQ is asserted possitively for 2 clocks and the 8-bit result together with the number of the converted channel is transferred to the result register ADDATH. In continuous conversion mode, bit field ADM is set to ’1’. In this mode, the ADC repeatedly converts the channel specified by ADCH. Bit ADST is cleared at the beginning of the first conversion. The busy flag ADBSY is asserted until the last conversion is completed. At the end of each conversion, the interrupt request signal ADCIRQ will be activated. To stop conversion, ADM has to be reset by software. If the channel number ADCH is changed while continuous conversion is in progress, the new channel specified will be sampled in the conversions that follow. A new request to start conversion will be allowed only after the completion of any conversion that is in progress. Writing a ‘1’ to bit CCU_ADEX select conversion control by T13PM trigger signal from the CCU module. Note: Caution must be taken when changing conversion start source. To change conversion source from software to hardware trigger, it is best to let remaining software conversion to complete before changing. To change conversion source from hardware trigger to software, it is best to change source first, let any

Data Sheet 53 V 1.0, 2003-05 remaining hardware conversion to complete before beginning a software conversion. Conversion and sample time control The conversion and sample times are programmed via the bit fields ADCTC and ADSTC respectively of the register ADCON1. Bit field ADCTC (conversion time control) selects the internal ADC clock - adc_clk. Bit field ADSTC (sample time control) selects the sample time. The total A/D conversion time is given by: t ADCC = 2/fSYS + tS + 8/adc_clk [5] The sample time tS is configured in periods of the selected internal ADC clock. The table below lists the possible combinations. ADCTC Clock Divider (TVC) ADC Basic Clock adc_clk ADSTC Sample Time t S (Periods of adc_clk, STC) 000 (default) 32 f SYS / 32 000 (default) 2 001 28 f SYS / 28 001 4 010 24 f SYS / 24 010 6 011 20 f SYS / 20 011 8 100 16 f SYS / 16 100 10 101 12 f SYS / 12 101 12 110 8 f SYS / 8 110 14 111 4 f SYS / 4 111 16

Data Sheet 54 V 1.0, 2003-05 Interrupt System The C868 provides 13 interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial channel, A/D converter, and the capture/compare unit with 4 interrupts) and four interrupts may be triggered externally. The wake-up from power-down mode interrupt has a special functionality which allows the software power-down mode to be terminated by a short negative pulse at pins CCPOS0/T2/INT0 /AN0 or P1.4/RxD. The 13 interrupt sources are divided into six groups. Each group can be programmed to one of the four interrupt priority levels. Additionally, 4 of these interrupt sources are channeled from 7 Capture/Compare (CCU6) interrupt sources. Figure 23 to Figure 28 give a general overview of the interrupt sources and illustrate the request and control flags.

Data Sheet 55 V 1.0, 2003-05 Figure 23 Capture/Compare module interrupt structure ENCC60R ICC60R ISL.0 IENL.0 ENCC60FICC60F ISL.1 IENL.1 ENCC61R ICC61R ISL.2 IENL.2 ENCC61FICC61F ISL.3 IENL.3 ENCC62R ICC62R ISL.4 IENL.4 ENCC62FICC62F ISL.5 IENL.5 P3.7/ CC0 P3.5/ CC1 P3.3/ CC2 ENT12OM ISL.6 IENL.6 ENT12PM ISL.7 IENL.7 ENTRPF TRPF ISH.2 IENH.2 ENWHEWHE ISH.5 IENH.5 T12 One Match T12 Period P3.1/ Wrong Hall Event Match T12PM T12OM INPL.0 Capcom Interrupt node 0 Capcom Interrupt node 1 Capcom Interrupt node 2 Capcom Interrupt node 3 INPL.1 ENT13CM T13CM ISH.0 IENH.0 ENT13PMT13PM ISH.1 IENH.1 ≥1T13 Compare Match T13 Period Match ENCHECHE ISH.4 IENH.4 Correct Hall Event INPL.2INPL.3 INPL.4INPL.5 INPH.0INPH.1 INPH.4INPH.5 INPH.2INPH.3 INPL.6INPL.7 CTRAP

Data Sheet 56 V 1.0, 2003-05 Figure 24 Interrupt Structure, Overview Part 1 0033H 000BH 0003H IEN0.7 IP0.0 Highest Priority Level EA EX0 IEN0.0 EADC IEN1.0 ET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow Bit addressable Request flag is cleared by hardware A/D Converter IADC IRCON1.0 IE0 IT0 TCON.0 TCON.1 IP1.1 IP0.1 Lowest Priority Level P o l l i n g S e q u e n c CCPOS2 / INT2 / EX2 IEN1.1 EX2 IRCON0.0ESEL2 EXICON.0 003BH IP1.0 INT0_ CORE_N (CCPOS / T2 / INT0 / AN0) AN2

Data Sheet 57 V 1.0, 2003-05 Figure 25 Interrupt Structure, Overview Part 2 IEN0.7 Highest Priority Level Lowest Priority Level P o l l i n g S e q u e n c EA Bit addressable Request flag is cleared by hardware 0013H 0043H EX1 IEN0.2 CCPOS1 / IE1 IT1 TCON.2 TCON.3 EX3 IEN1.2 EXINT3 IRCON0.1ESEL3 EXICON.1 INT3 P1.3 / IP1.2 IP0.2 EINP0 IEN2.2 0083H Capture/compare interrupt node 0 T2EX / INT1 / AN1 INP0 IRCON1.2

Data Sheet 58 V 1.0, 2003-05 Figure 26 Interrupt Structure, Overview Part 3 IEN0.7 IP0.3EA Timer 1 Overflow IP1.3 Bit addressable Request flag is cleared by hardware Priority Level Lowest Priority Level P o l l i n g S e q u e n c Highest 001BHET1 IEN0.3 TF1 TCON.7 008BH Capture/compare interrupt node 1 EINP1 IEN2.3 INP1 IRCON1.3

Data Sheet 59 V 1.0, 2003-05 Figure 27 Interrupt Structure, Overview Part 4 Priority Level Priority Level P o l l i n g S e q u e n c Highest IEN0.7 EA IP0.4IP1.4 0093H 0023H UART ES IEN0.4 TI RI SCON.0 SCON.1 Capture/compare interrupt node 2 EINP2 IEN2.4 Bit addressable Request flag is cleared by hardware INP2 IRCON1.4

Data Sheet 60 V 1.0, 2003-05 Figure 28 Interrupt Structure, Overview Part 5 IEN0.7 Priority Level Priority Level P o l l i n g S e q u e n c EA Bit addressable Request flag is cleared by hardware IP1.5 IP0.5 002BHET2 IEN0.5 Timer 2 Overflow TF2 IRCON0.6 Highest EINP3 IEN2.5 009BH Capture/compare interrupt node 3 INP3 IRCON1.5

Data Sheet 61 V 1.0, 2003-05 Table 12 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address(core connections) Interrupt Request Flags External Interrupt 0 0003 H (EX0) IE0 Timer 0 Overflow 000B H (ET0) TF0 External Interrupt 1 0013 H (EX1) IE1 Timer 1 Overflow 001B H (ET1) TF1 Serial Channel 0023 H (ES) RI / TI Timer 2 Overflow 002B H (EX5) TF2 A/D Converter 0033 H (EX6) IADC External Interrupt 2 003B H (EX7) IEX2 External Interrupt 3 0043 H (EX8) IEX3 004BH (EX9) 0053H (EX10) 005BH (EX11) 0063H (EX12) 006BH (EX13) CAPCOM interrupt node 0 0083 H (EX14) INP0 1) 1) Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/compare ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F. The other flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE. CAPCOM interrupt node 1 008B H (EX15) INP1 1) CAPCOM interrupt node 2 0093 H (EX16) INP2 1) CAPCOM interrupt node3 009B H (EX17) INP3 1) 00A3H (EX18) 00AB H (EX19) 00D3 H (EX20) 00DB H (EX21) 00E3H (EX22) Wake-up from power-down mode 007BH –

Data Sheet 62 V 1.0, 2003-05 lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure determined by the polling sequence. This is illustrated in Table 13 Within a column, the topmost interrupt is serviced first, then the second and the third, when available. The interrupt groups are serviced from left to right of the table. A low- priority interrupt can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same or a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt source. Table 13 Interrupt Source Structure Interrupt Group Priority Bits of Interrupt Group Interrupt Source Priority High Priority Low Priority Priority 0 IP0.0 EXINT0 IADC High Low 1 IP0.1 TF0 EXINT2 2 IP0.2 EXINT1 EXINT3 INP0 1) Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/ compare ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F. The other flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE. 3 IP0.3 TF1 INP1 1) 4 IP0.4 RI + TI INP2 1) 5 IP0.5 TF2 INP3 1)

Data Sheet 63 V 1.0, 2003-05 Fail Save Mechanisms The C868 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : a programmable watchdog timer (WDT), with variable time-out period from 12.8µs to 819.2µs at fSYS = 40 MHz. Programmable Watchdog Timer To protect the system against software failure, the user’s program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. The watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate of fSYS /2 upto fSYS /128. The machine clock of the C868 is divided by a prescaler, a divide- by-two or a divide-by-128 prescaler. The upper 8 bits of the Watchdog Timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits are reset on each service access. Figure 29 shows the block diagram of the watchdog timer unit. Figure 29 Block Diagram of the Programmable Watchdog Timer After a reset, the Watchdog Timer is automatically enabled. If it is disabled, it cannot be enabled again during active mode of the device. If the software fails to clear the watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTR in SCUWDT is set). A refresh of the watchdog timer is done by setting bits WDTRE and WDTRS (in WDT High Byte WDTRST WDTREL DISWDT WDTIN MUX1:2 WDT Low Byte WDT Control Clear 1:128 fSYS

Data Sheet 64 V 1.0, 2003-05 SFR SCUWDT) consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "Power Saving Modes"). It is not possible to use the idle mode in combination with the watchdog timer function. Therefore, even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally. The time period for an overflow of the Watchdog Timer is programmable in two ways : – the input frequency to the Watchdog Timer can be selected via bit WDTIN in register WDTCON to be either fSYS /2 or fSYS /128. – the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON. The period PWDT between servicing the Watchdog Timer and the next overflow can therefore be determined by the following formula: [0.1] Table 14 lists the possible ranges for the watchdog time which can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. For safety reasons, the user is advised to rewrite WDTCON each time before the Watchdog Timer is serviced. Table 14 Watchdog Time Ranges Reload value in WDTREL Prescaler for fSYS 2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)

40 MHz 20 MHz 16 MHz 40 MHz 20 MHz 16 MHz

PWDT = fSYS 2(1 +WDTIN*6) * (216 - WDTREL * 28)

Data Sheet 65 V 1.0, 2003-05 Power Saving Modes The C868 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode.  Idle Mode In the idle mode, the oscillator of the C868 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the capture/compare unit, and all timers are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode.  Slow Down Mode In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (for example, if the controller is waiting for an input signal). Since in CMOS devices, there is an almost linear dependence of the operating frequency and the power supply current, so, a reduction of the operating frequency results in reduced power consumption.  Software Power Down Mode In the software power down mode, the on-chip oscillator which operates with the XTAL pins and the PLL are all stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE is held at logic low level or high impedance if disabled. In the power down mode of operation, VDDP can be reduced to minimize power consumption. It must be ensured, however, that VDDP is not reduced before the power down mode is invoked, and that VDDP is restored to its normal operating level before the power down mode is terminated.

Data Sheet 66 V 1.0, 2003-05 Table 15 Power Saving Modes Overview Mode Entering Leaving by Remarks Idle Mode ORL PCON,#01 H Occurance of any enabled interrupt CPU clock is stopped; CPU maintains its data; peripheral units are active (if enabled) and provided with clock Hardware Reset Slow Down Mode In normal mode: ORL PCON,#10 H ANL PCON,#0EF H or Hardware Reset Internal clock rate is reduced to a configurable factor of 1/2 to 1/32 of the system clock rate With idle mode: ORL PCON,#11 H Occurance of any enabled interrupt to exit idle mode and the instruction ANL PCON,#0EF H to terminate slow down mode CPU clock is stopped; CPU maintains all its data; Peripheral units are active (if enabled) and provided with a configurable factor of 1/2 to 1/32 of the system clock rate Hardware Reset Software Power Down mode With external wake-up capability from power down enabled ORL PMCON0,#01 H (to wake-up via pin INT0) or ORL PMCON0,#03 H (to wake-up via pin RxD) ORL PCON,#02 H Hardware Reset Oscillator is stopped; Contents of on-chip RAM and SFR ’s are maintained When INT0 or RxD goes low for at least 10 µs (latch phase). But it is desired that the corresponding pin must be held at high level during the power down mode entry and up to the wake-up. With external wake-up capability from power down disabled ORL PCON,#02 H Hardware Reset

Data Sheet 67 V 1.0, 2003-05 Device Specifications Absolute Maximum Ratings Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( VIN>VDDP or VIN<VSSP , VIN2>VDDC or VIN2<VSSC ) the voltage on VDDP pin with respect to ground (VSSP ) must not exceed the values defined by the absolute maximum ratings. Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. Ambient temperature under biasTA -40 125 °C Storage temperature TSTG -65 150 °C- Voltage on VDDP pins with respect to ground (VSSP ) VDDP -0.3 4.6 V - Voltage on any pin except int/ analog and XTAL with respect to ground (VSSP ) VIN0 -0.5 4.6 V - Voltage on any int/analog pin with respect to ground (VSSP ) VIN1 -0.5 4.6 V - Voltage on XTAL pins with respect to ground (VSSC ) VIN2 -0.5 4.6 V - Input current on any pin during overload condition ΙOV -10 10 mA - 1) 1) Proper operation is not guaranteed if overload conditions occur on functional pins like XTAL2 etc. Absolute sum of all input currents during overload condition Σ|ΙOV |- 4 3 m A - Power dissipation PDISS -t b d W -

Data Sheet 68 V 1.0, 2003-05 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C868. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Operating Condition Parameters Parameter Symbol Limit Values Unit Notes min. max. Digital supply voltage VDDP 3.0 3.6 V Active mode, fSYSmax = 40 MHz tbd 3.6 V PowerDown mode 1) 1) Oscillator or external clock disabled. Digital ground voltages VSSC,VSSP 0V - Ambient temperatureTA -40 85 °C SAF-C868... Analog reference voltage VAREF 3.0V VDDP + 0.1 Analog ground voltage VAGND VSSP - 0.1VSSP + 0.1 Analog input voltageVAIN VAGND VAREF V- External Clock fOSC 6.67 10.67 MHz - Input current on any pin during overload condition except int/ analog and XTAL ΙOV0 -5 5 mA - 2)3) 2) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits. 3) Not 100% tested, but guaranteed by design characterization. int/analog pin ΙOV1 -2 5 mA - 3)4) XTAL pin ΙOV2 -5 5 mA - 3)5) Absolute sum of all input currents during overload condition ΣΙ OV -| 2 0 | m A - 3) Notes:

Data Sheet 69 V 1.0, 2003-05 4) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > tbd or V OV < VSSC -0.5V). The absolute sum of input currents on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits. 5) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDDC +0.5V or VOV < VSSC -0.5V). The absolute sum of input currents on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits.

Data Sheet 70 V 1.0, 2003-05 DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltages all except XTAL2, int/analog int/analog XTAL2 VIL0 VIL1 VIL2 -0.5 -0.5 -0.5 0.3V DDP 0.3VDDC 0.1VDDC V V V 1) Interrupt/analog pins are input only and has CMOS characteristics whereas the other I/O pins have TTL characteristics. Input high voltages all except XTAL2, int/analog int/analog XTAL2 VIH0 VIH1 VIH2 0.7VDDP 0.7VDDC 0.7VDDC VDDP +0.5 VDDP +0.5 VDDC +0.5 V V V Output low voltage VOL – 0.45 V SAF-C868... IOL =10mA – 0.55 V SAK-C868... IOL =10mA Output high voltage VOH 2.4 – VI OH =10mA Input leakage current (all except int/analog) ILI0 – ±0.5u A 0 . 4 < V IN<V DDP Input leakage current (int/ analog) ILI1 – ±0.5u A 0 . 4 < V IN<V DDP 2) 2) The leakage current of interrupt/analog pins depends on the leakage current of the CMOS pad for the digital functions and the analog pad. Input low current (XTAL2)ILI2 – ±10 uA 0.4<V IN<V DDC Digital supply voltage VDDC 2.253) 3) The VDDC is measured under the following conditions: Microcontroller in power down mode;RESET= VDDP ; XTAL2 = VSSC ; XTAL1 = N.C.; VAGND = V SSP ; VAREF = VDDP ; RxD/INT0 = V DDP ; all other pins are set to input and connected to gnd; ALE output disabled and connected to gnd; 20mA current sourced from the VDDC pin.

2.75 V –

Blocking capacitor for VDDC 136 470 nF –4) 4) Ceramic type (±20%) max ESR: 25mΩ ,max trace length to capacitor is 10mm. Pin capacitance C IO -1 0 p F fC = 1MHz TA= 250C Note:

Data Sheet 71 V 1.0, 2003-05 Power Supply Current Parameter Symbol Limit Values Unit Test Condition typ.1) 1) The typical IDDP values are periodically measured at TA = + 25°C but not 100% tested. max.2) 2) The maximum IDDP values are measured under worst case conditions (TA = – 40 °C and VDDP =3 . 6V ) . Active mode C868-1S 40 MHz 3) 3) System clock, set by using external clock of 10.67MHz and setting KDIV in CMCON to 010 (factor of 4) IDDP 13.1 15.6 mA 4) 4) IDDP (active mode) is measured with: XTAL2 driven with tR , tF =5n s , VIL1,VIL2= VSSP +0 . 5V , VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.; RESET = VDDP ; all other pins are disconnected. ?IDDP would be slightly higher if the crystal oscillator is used (approx. 1 mA). C868-1R 40 MHz 3) IDDP 13.5 15.5 mA Idle mode C868-1S 40 MHz 3) IDDP 7.8 9.6 mA 5) C868-1R 40 MHz 3) IDDP 7.9 9.1 mA Active mode with slow-down enabled C868-1S 40 MHz 3) IDDP 3.5 4.4 mA 6) C868-1R 40 MHz 3) IDDP 3.6 4.1 mA Idle mode with slow- down enabled C868-1S 40 MHz 3) IDDP 3.4 4.2 mA 7) C868-1R 40 MHz 3) IDDP 3.6 4.1 mA Power- down mode C868-1S IPDP 240 300 uA SAF-C868... 8) 240 400 uA SAK-C868...8) C868-1R IPDP 240 300 uA SAF-C868...8) 240 400 uA SAK-C868...8) Note:

Data Sheet 72 V 1.0, 2003-05 5) IDDP (idle mode) is measured with all output pins disconnected and with all peripheral disabled: XTAL2 driven with tR , tF =5n s , VIL1,VIL2= VSSP +0 . 5V , VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.; RESET = VDDP ; all other pins are disconnected. 6) IDDP (active mode with slow down mode) is measured with all output pins disconnected: XTAL2 driven with tR , tF =5n s , VIL1,VIL2= VSSP +0 . 5V , VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.; RESET = VDDP ; all other pins are disconnected; the microcontroller is put into slow-down mode by software with the slow-down clock set to 1/32 of system clock. 7) IDDP (idle mode with slow down mode) is measured with all output pins disconnected and with all peripheral disabled: XTAL2 driven with tR , tF =5n s , VIL1,VIL2= VSSP +0 . 5V , VIH1,VIH2 = VDDP – 0.5 V; XTAL1 = N.C.; RESET = VDDP ; all other pins are disconnected; the microcontroller is put into slow-down mode by software with the slow-down clock set to 1/32 of system clock. 8) IPDC and IPDP (power-down mode) are measured under the following conditions: RESET = VDDP ; XTAL2 = VSSC ; XTAL1 = N.C.; VAGND = V SSP ; VAREF = V DDP ; RxD/INT0 = VDDP ; all other pins are set to input and connected to gnd; ALE output disabled and connected to gnd.

Data Sheet 73 V 1.0, 2003-05 Power Supply Current Calculation Formulae Parameter Symbol Formula 1) 1) fSYS is in MHz and results in mA. Active mode C868-1S IDDP typ 0.25* fSYS + 3.1 0.26 * fSYS + 5.2IDDP max C868-1R IDDP typ 0.27* fSYS + 2.7 0.29 * fSYS + 3.9IDDP max Idle mode C868-1S IDDP typ 0.13* fSYS + 2.6 0.13 * fSYS + 4.0IDDP max C868-1R IDDP typ 0.13* fSYS + 3.7 0.15 * fSYS + 3.1IDDP max Active mode with slow-down enabled C868-1S IDDP typ 0.01 * fSYS + 3.1 0.02 * fSYS + 3.6IDDP max C868-1R IDDP typ 0.01 * fSYS + 3.2 0.01 * fSYS + 3.7IDDP max Idle mode with slow- down enabled C868-1S IDDP typ 0.01* fSYS + 3.0 0.01 * fSYS + 3.8IDDP max C868-1R IDDP typ 0.02* fSYS + 2.8 0.02 * fSYS + 3.3IDDP max

Data Sheet 74 V 1.0, 2003-05 A/D Converter Characteristics (Operating Condition Parameters) Parameter Symbol Limits Unit Test Condition min max Analog input voltageVAIN VAGND VAREF V 1) 1) VAIN may exceed VAGND or VAREF up to the maximum ratings. However, the conversion result in these cases will be 00H or FFH , respectively. Sample time tS 64*tSYS 52*tSYS 48*tSYS 40*tSYS 32*tSYS 24*tSYS 16*tSYS 8*tSYS 512*tSYS 448*tSYS 384*tSYS 320*tSYS 256*tSYS 192*tSYS 128*tSYS 64*tSYS ns Prescaler/32 Prescaler/28 Prescaler/24 Prescaler/20 Prescaler/16 Prescaler/12 Prescaler/8 Prescaler/4 Conversion cycle time tADCC 322*tSYS 282*tSYS 242*tSYS 202*tSYS 162*tSYS 122*tSYS 82*tSYS 42*tSYS 770*tSYS 674*tSYS 578*tSYS 482*tSYS 386*tSYS 290*tSYS 194*tSYS 98*tSYS ns Prescaler/32 Prescaler/28 Prescaler/24 Prescaler/20 Prescaler/16 Prescaler/12 Prescaler/8 Prescaler/4 Total unadjusted error TUE – ±2 LSB V AGND ≤ VAIN ≤ VAREF VAGND ≤ VAIN ≤ VAREF 3) 2) TUE (max.) is tested at – 20 ≤ TA ≤ 125 °C; VDDP = 3.3 V; VAREF = VDDP V and V SSP = VAGND . It is guaranteed by design characterization for all other voltages within the defined voltage range. 3) TUE (max.) is tested at – 40 ≤ TA < – 20 °C; VDDP ≤ 3.3 V; VAREF = VDDP and VSSP = VAGND . It is guaranteed by design characterization for all other voltages within the defined voltage range. ADC input resistanceRAIN – 1.5 k Ω 4)5) ADC input capacitanceC AIN – 10 pF 5) ADC reference pin capacitance C AREF – 40 pF 5) Note:

Data Sheet 75 V 1.0, 2003-05 4) During the sample time the input capacitance C AIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 5) Not 100% tested, but guaranteed by design characterization.

Data Sheet 76 V 1.0, 2003-05 Clock calculation table for ADC TVC 1) 32 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 322 386 450 514 578 642 706 770 tSYS tS 64 128 192 256 320 384 448 512 tSYS TVC 1) 28 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 282 338 394 450 506 562 618 674 tSYS tS 56 112 168 224 280 336 392 448 tSYS TVC 1) 24 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 242 290 338 386 434 482 530 578 tSYS tS 48 96 144 192 240 288 336 384 tSYS TVC 1) 20 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 202 242 282 322 362 402 442 482 tSYS tS 40 80 120 160 200 240 280 320 tSYS TVC 1) 16 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 162 194 226 258 290 322 354 386 tSYS tS 32 64 96 128 160 192 224 256 tSYS TVC 1) 12 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 122 146 170 194 218 242 266 290 tSYS tS 24 48 72 96 120 144 168 192 tSYS

Data Sheet 77 V 1.0, 2003-05 TVC 1) 8 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 82 98 114 130 146 162 178 194 tSYS tS 16 32 48 64 80 96 112 128 tSYS TVC 1) 4 STC 2) 24681 0 1 2 1 4 1 6 tADC tADCC 42 50 58 66 74 82 90 98 tSYS tS 8 1 62 43 24 04 85 66 4 tSYS 1) TVC is the clock divider specified by bit fields ADCTC. 2) STC is the sample time control specified by bit fields ADSTC. 3) tADC is tSYS*TVC

Data Sheet 78 V 1.0, 2003-05 AC Characteristics (Operating Condition Apply) External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Ext Clock 6.67 to 10.67 MHz min max Oscillating period tOSC 93.75 150 ns High time t1 46.875 75 ns Low time t2 46.875 75 ns Rise time tR -1 0 n s Fall time tF -1 0 n s ALE Characteristics Parameter Symbol Limit Values Unit System freq = 6.25MHz to 40MHz Duty Cycle 0.5 min max ALE pulse width tAWD 50 320 ns ALE period tACY 150 960 ns

Data Sheet 79 V 1.0, 2003-05 Figure 30 External Clock Drive on XTAL2 Figure 31 ALE Characteristic MCT04105 tR tF tOSC

0.7 V DD

0.2 V DD - 0.1c c tAWD tACY

Data Sheet 80 V 1.0, 2003-05 Package Outlines Figure 32 DSO-28-1 Package Outlines 0.35 x 45˚ -0.2 Index Marking -0.418.1 141) 0.35 1.27 +0.152) 0.2 28x0.2 2.65 MAX. 0.1 2.45 -0.1 -0.2 7.6 1) 10.3±0.3 0.23 +0.09 MAX.8˚ +0.80.4 Does not include dambar protrusion of 0.05 max. per side Does not include plastic or metal protrusion of 0.15 max. per side Plastic Package, P-DSO-28-1 for SAF-C868-1RG BA, SAF-C868-1SG BA SAF-C868A-1RG BA, SAF-C868A-1SG BA and SAF-C868P-1SG BA, SAK-C868-1RG BA, SAK-C868-1SG BA, SAK-C868A-1RG BA, SAK-C868A-1SG BA and SAK-C868P-1SG BA.

Data Sheet 81 V 1.0, 2003-05 Figure 33 TSSOP-38-1 Package Outlines Does not include plastic or metal protrusion of 0.25 max. per side Does not include dambar protrusion of 0.08 max. per side Does not include plastic or metal protrusion of 0.15 max. per side Index Marking A A 9.7 ±0.11) 0.08 M 38xC 0.2-0.03 +0.07 0.5 -0.2 ±0.050.1 C +0.051 1.2 MAX. 0.1 -0.035+0.075 ±0.14.4 3) B ...8˚0˚0.125 38x 6.4 ±0.150.6 0.2 B Plastic Package, P-TSSOP-38-1 for SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868P-1SR BA, SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868A-1RR BA, SAK-C868A-1SR BA, and SAK-C868P-1SR BA.

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