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© Semiconductor Components Industries, LLC, 2010 April, 2010 − Rev. 3

1 Publication Order Number:

Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable The ADP3419 is a dual MOSFET driver optimized for driving two N-channel switching MOSFETs in nonisolated synchronous buck power converters used to power CPUs in portable computers. The driver impedances have been chosen to provide optimum performance in multiphase regulators at up to 25 A per phase. The high-side driver can be bootstrapped relative to the switch node of the buck converter and is designed to accommodate the high voltage slew rate associated with floating high-side gate drivers. The ADP3419 includes an anticross-conduction protection circuit, undervoltage lockout to hold the switches off until the driver has sufficient voltage for proper operation, a crowbar input that turns on the low-side MOSFET independently of the input signal state, and a low-side MOSFET disable pin to provide higher efficiency at light loads. The SD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3419 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 10-lead MSOP package.

FEATURES

  • All-In-One Synchronous Buck Driver
  • One PWM Signal Generates Both Drives
  • Anticross-Conduction Protection Circuitry
  • Output Disable Function
  • Crowbar Control
  • Synchronous Override Control
  • Undervoltage Lockout
  • Pb−Free Package is Available

APPLICATIONS

  • Mobile Computing CPU Core Power Converters
  • Multiphase Desk-Note CPU Supplies
  • Single-Supply Synchronous Buck Converters
  • Non-Synchronous-to-Synchronous Drive Conversion http://onsemi.com PIN ASSIGNMENT See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

(Top View) MARKING DIAGRAM MSOP−10 CASE 846AC P9x RYW/C0071 /C0071 P9x = Device Code x = A or B R = Assembly Location Y = Year W = Work Week /C0071= Pb−Free Package (Note: Microdot may be in either location) DRVH SW GND DRVL

Figure 1. Simplified Block Diagram Figure 2. General Application Circuit NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

http://onsemi.com PIN ASSIGNMENT Pin No. Mnemonic Description 1 IN Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. 2 SD Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low. 3 DRVLSD Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled and controlled by IN and by the adaptive overlap protection control circuitry. 4 CROWBAR Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition. 5 VCC Input Supply. This pin should be bypassed to GND with a 4.7 /C0109F or larger ceramic capacitor. 6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. 7 GND Ground. This pin should be closely connected to the source of the lower MOSFET. 8 SW Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V. 9 DRVH Buck Drive. Output drive for the upper (buck) MOSFET. 10 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. ELECTRICAL CHARACTERISTICS VCC = SD = 5.0 V, BST = 4.0 V to 26 V. TA = 0°C to 100°C, unless otherwise noted All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Parameter Symbol Conditions Min Typ Max Unit LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR) Input Voltage High VIH 2.0 V Input Voltage Low VIL 0.8 V Input Current IIN Inputs = 0 V or 5.0 V −1.0 +1.0 /C0109A DRVLSD Propagation Delay Time tpdl DRVLSD, tpdh DRVLSD CLOAD = 3 nF, Figure 3 20 ns HIGH-SIDE DRIVER Output Resistance, Sourcing Current BST − SW = 4.6 V 1.7 3.3 /C0087 Output Resistance, Sinking Current BST − SW = 4.6 V 0.8 2.3 /C0087 Transition Times trDRVH tfDRVH BST − SW = 4.6 V, CLOAD = 3 nF , Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF , Figure 4 ns Propagation Delay Times (Note 1) tpdhDRVH tpdlDRVH BST − SW = 4.6 V, CLOAD = 3 nF , Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF , Figure 4 15 32 ns LOW-SIDE DRIVER Output Resistance, Sourcing Current 1.7 3.3 /C0087 Output Resistance, Sinking Current 0.8 2.3 /C0087 Transition Times trDRVL tfDRVL CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 ns Propagation Delay Times (Note 2) tpdhDRVL tpdlDRVL CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 ns SW Transition Timeout (Note 1 and 2) tSWTO BST − SW = 4.6 V 150 350 600 ns Zero-Crossing Threshold VZC 1.0 V SUPPLY Supply Voltage Range VCC 4.6 6.0 V Supply Current Normal Mode Shutdown Mode ISYS(NM) ISYS(SD) ICC + IBST, IN = 0 V or 5.0 V ICC + IBST, SD = 0 V 0.8 325 1.5 600 mA /C0109A Undervoltage Lockout Threshold VCC rising 3.8 4.25 4.5 V Undervoltage Lockout Hysteresis (Note 3) VCC falling 50 120 mV 1. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%. 2. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of t SWTO. 3. Guaranteed by characterization, not production tested.

Figure 16. Detailed Block Diagram of the ADP3419 MOSFET driver outputs low during VCC supply ramp-up. before releasing control of the drivers to the control pins. driven so that the SW node follows the polarity of IN. circuit, which is connected between the BST and SW pins. capacitor to charge up to VCC again. DRVH and the different control inputs of the ADP3419. the delay from Q2’s turn-off to Q1’s turn-on. DRVH is asserted high and Q1 turns on. for reverse voltage protection purposes.

http://onsemi.com When DRVLSD is low, the low-side driver stays low. When DRVLSD is high, the low-side driver is enabled and controlled by the driver signals, as previously described. Low-Side Driver Timeout In normal operation, the DRVH signal tracks the IN signal and turns off the Q1 high-side switch with a few 10 ns delay pdlDRVH) following the falling edge of the input signal. When Q1 is turned off, DRVL is allowed to go high, Q2 turns on, and the SW node voltage collapses to zero. But in a fault condition such as a high-side Q1 switch drain-source short circuit, the SW node cannot fall to zero, even when DRVH goes low. The ADP3419 has a timer circuit to address this scenario. Every time the IN goes low, a DRVL on-time delay timer is triggered. If the SW node voltage does not trigger a low-side turn-on, the DRVL on-time delay circuit does it instead, when it times out with t SW(TO) delay. If Q1 is still turned on, that is, its drain is shorted to the source, Q2 turns on and creates a direct short circuit across the VDCIN voltage rail. The crowbar action causes the fuse in the VDCIN current path to open. The opening of the fuse saves the load (CPU) from potential damage that the high-side switch short circuit could have caused. Crowbar Function In addition to the internal low-side drive time-out circuit, the ADP3419 includes a CROWBAR input pin to provide a means for additional overvoltage protection. When CROWBAR goes high, the ADP3419 turns off DRVH and turns on DRVL. The crowbar logic overrides the overlap protection circuit, the shutdown logic, the DRVLSD logic, and the UVLO protection on DRVL. Thus, the crowbar function maximizes the overvoltage protection coverage in the application. The CROWBAR can be either driven by the CLAMP pin of buck controllers, such as the ADP3422, ADP3203, ADP3204, or ADP3205, or controlled by an independent overvoltage monitoring circuit. Table 1. ADP3419 Truth Table

Application Information

Supply Capacitor Selection For the supply input (VCC) of the ADP3419, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 10 /C0109F or 4.7 /C0109F multilayer ceramic (MLC) capacitor. MLC capacitors provide the best combination of low ESR and small size, and can be obtained from the following vendors. Table 2. Vendor Part Number Web Address Murata GRM235Y5V106Z16 www.murata.com Taiyo-Yuden EMK325F106ZF www.t-yuden.com Tokin C23Y5V1C106ZP www.tokin.com Keep the ceramic capacitor as close as possible to the ADP3419. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode (D1), as shown in Figure 16. Selection of these components can be done after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle at least 5.0 V more than the maximum supply voltage. The capacitance is determined by: CBST /C0043 QHSGATE /C0068VBST (eq. 1) where: QHSGATE is the total gate charge of the high-side MOSFET. /C0068VBST is the voltage droop allowed on the high-side MOSFET drive. For example, two IRF7811 MOSFETs in parallel have a total gate charge of about 36 nC. For an allowed droop of 100 mV , the required bootstrap capacitance is 360 nF. A good quality ceramic capacitor should be used, and derating for the significant capacitance drop of MLCs at high temperature must be applied. In this example, selection of 470 nF or even 1 /C0109F would be recommended. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side MOSFET. The bootstrap diode must also be able to handle at least 5.0 V more than the maximum battery voltage. The average forward current can be estimated by: IF(AVG) /C0043QHSGATE /C0032fMAX (eq. 2) where fMAX is the maximum switching frequency of the controller. Power and Thermal Considerations The major power consumption of the ADP3419-based driver circuit is from the dissipation of MOSFET gate charge. It can be estimated as: PMAX /C0091VCC /C0032(QHSGATE /C0041QLSGATE) /C0032fMAX (eq. 3) where: VCC is the supply voltage 5.0 V . f MAX is the highest switching frequency. QHSGATE and QLSGATE are the total gate charge of high-side and low-side MOSFETs, respectively. For example, the ADP3419 drives two IRF7821 high-side MOSFETs and two IRF7832 low-side MOSFETs. According

http://onsemi.com to the MOSFET data sheets, Q HSGATE = 18.6 nC and QLSGATE = 68 nC. Given that fMAX is 300 kHz, PMAX would be about 130 mW. Part of this power consumption generates heat inside the ADP3419. The temperature rise of the ADP3419 against its environment is estimated as: /C0068T /C0091/C0113JA /C0032PMAX /C0032/C0104 (eq. 4) where θJA is ADP3419’s thermal resistance from junction to air, given in the absolute maximum ratings as 220 °C/W for a 4−layer board. The total MOSFET drive power dissipates in the output resistance of ADP3419 and in the MOSFET gate resistance as well. η represents the ratio of power dissipation inside the ADP3419 over the total MOSFET gate driving power. For normal applications, a rough estimation for η is 0.7. A more accurate estimation can be calculated using: /C0104/C0091 QHSGATE QHSGATE /C0041QLSGATE /C0032/C04660.5 /C0032R1 R1 /C0041RHSGATE /C0041R /C00410.5 /C0032R2 R2 /C0041RHSGATE /C0467 (eq. 5) /C0041 QLSGATE QHSGATE /C0041QLSGATE /C0032/C04660.5 /C0032R3 R3 /C0041RLSGATE /C00410.5 /C0032R4 R4 /C0041RLSGATE /C0467 where: R1 and R2 are the output resistances of the high-side driver: R1 = 1.7 (DRVH − BST), R2 = 0.8 (DRVH − SW). R3 and R4 are the output resistances of the low-side driver: R3 = 1.7 (DRVL − VCC), R4 = 0.8 (DRVL − GND). R is the external resistor between the BST pin and the BST capacitor. R HSGATE and RLSGATE are gate resistances of high-side and low-side MOSFETs, respectively. Assuming that R = 0 and that RHSGATE = RLSGATE = 0.5, Equation 5 gives a value of η = 0.71. Based on Equation 4, the estimated temperature rise in this example is about 22°C. PC Board Layout Considerations Use the following general guidelines when designing printed circuit boards. Figure 17 gives an example of the typical land patterns based on the guidelines given here.

  • The VCC bypass capacitor should be located as close as possible to the VCC and GND pins. Place the ADP3419 and bypass capacitor on the same layer of the board, so that the PCB trace between the ADP3419 VCC pin and the MLC capacitor does not contain any via. An ideal location for the bypass MLC capacitor is near Pin 5 and Pin 6 of the ADP3419.
  • High frequency switching noise can be coupled into the VCC pin of the ADP3419 via the BST diode. Therefore, do not connect the anode of the BST diode to the VCC pin with a short trace. Use a separate via or trace to connect the anode of the BST diode directly to the VCC 5.0 V power rail.
  • It is best to have the low-side MOSFET gate close to the DRVL pin; otherwise, use a short and very thick PCB trace between the DRVL pin and the low-side MOSFET gate.
  • Fast switching of the high-side MOSFET can reduce switching loss. However, EMI problems can arise due to the severe ringing of the switch node voltage. Depending on the character of the low-side MOSFET, a very fast turn-on of the high-side MOSFET may falsely turn on the low-side MOSFET through the dv/dt coupling of its Miller capacitance. Therefore, when fast turn-on of the high-side MOSFET is not required by the application, a resistor of about 1 /C0087 to 2 /C0087 can be placed between the BST pin and the BST capacitor to limit the turn-on speed of the high-side MOSFET.

Figure 17. External Component Placement Example Device Number Branding Package Type Shipping† ADP3419JRM−REEL P9A 10−Lead MSOP 3000 Tape & Reel ADP3419JRMZ−REEL P9B 10−Lead MSOP 3000 Tape & Reel ADP34190091RMZR P9B 10−Lead MSOP 3000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb−Free part.

http://onsemi.com PACKAGE DIMENSIONS MSOP10 CASE 846AC−01 ISSUE O SBM0.08 (0.003) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C 0.95 1.10 0.037 0.043 D 0.20 0.30 0.008 0.012 G 0.50 BSC 0.020 BSC H 0.05 0.15 0.002 0.006 J 0.10 0.21 0.004 0.008 K 4.75 5.05 0.187 0.199 L 0.40 0.70 0.016 0.028 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION “A” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION “B” DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B −01 OBSOLETE. NEW STANDARD 846B−02 −B− −A− D K G PIN 1 ID 8 PL 0.038 (0.0015) −T− SEATING PLANE C H J L /C0466mm inches/C0467SCALE 8:1 10X 10X 1.04 0.041 0.32 0.0126 5.28 0.208 4.24 0.167 3.20 0.126 0.50 0.0196 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ADP3419/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative