Memory

C2388

NXP Semiconductors

Single-chip 16-bit/32-bit micro; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 01-19 December 2008

Manufacturer: NXP Semiconductors

Document: 61 Pages / 275Kb

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Technical content

General description The LPC2388 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with 512 kB of embedded high-speed ﬂash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2388 is ideal for multi-purpose serial communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), USB device/host/OTG with 4 kB of endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial Ports (SSP), three I 2C-bus interfaces, an I2S-bus interface, and an External Memory Controller (EMC). This blend of serial communications interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of 64 kB, 16 kB SRAM for Ethernet, 16 kB SRAM for USB and general purpose use, together with 2 kB battery powered SRAM make this device very well suited for communication gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO lines with up to 50 edge and up to four level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. Features n ARM7TDMI-S processor, running at up to 72 MHz. n Up to 512 kB on-chip ﬂash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access. n 64 kB of SRAM on the ARM local bus for high performance CPU access. n 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. n 16 kB SRAM for general purpose DMA use also accessible by the USB. n Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip ﬂash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem. n EMC provides support for static devices such as ﬂash and SRAM as well as off-chip memory mapped peripherals. n Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts. LPC2388 Single-chip 16-bit/32-bit micro; 512 kB ﬂash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 01 — 19 December 2008 Product data sheet

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 2 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller n General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial interfaces, the I2S-bus port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers. n Serial Interfaces: u Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. u USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller. u Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. u CAN controller with two channels. u SPI controller. u Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller. u Three I 2C-bus interfaces (one with open-drain and two with standard port pins). u I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. n Other peripherals: u SD/MMC memory card interface. u 104 General purpose I/O pins with conﬁgurable pull-up/down resistors. u 10-bit ADC with input multiplexing among 8 pins. u 10-bit DAC. u Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input. u One PWM/timer block with support for three-phase motor control. The PWM has two external count inputs. u Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or the APB clock. u 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off. u WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. n Standard ARM test/debug interface for compatibility with existing tools. n Emulation trace module supports real-time trace. n Single 3.3 V power supply (3.0 V to 3.6 V). n Three reduced power modes: idle, sleep, and power-down. n Four external interrupt inputs conﬁgurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. n Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt). n Two independent power domains allow ﬁne tuning of power consumption based on needed features. n Each peripheral has its own clock divider for further power saving. n Brownout detect with separate thresholds for interrupt and forced reset. n On-chip power-on reset. n On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.

LPC2388_1 © NXP B.V. 2008. All rights reserved. the system clock. When used as the CPU clock, does not allow CAN and USB to run. oscillator, or the RTC oscillator. n Boundary scan for simpliﬁed board testing.

4.1 Ordering options

Table 1. Ordering information Table 2. Ordering options

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 4 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller 5. Block diagram Fig 1. LPC2388 block diagram PWM1 ARM7TDMI-S PLL EINT3 to EINT0 FLASH P3, P4 P0, P1, P2, LEGACY GPI/O

56 PINS TOTALP0, P1

SCK, SCK0 MOSI, MOSI0 SSEL, SSEL0 SCK1 MOSI1 MISO1 SSEL1 SCL0, SCL1, SCL2 I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS 8 × AD0 RTCX1 RTCX2 MCICLK, MCIPWR RXD0, RXD2, RXD3 TXD1 RXD1 RD1, RD2 TD1, TD2CAN1, CAN2 USB port 1 XTAL1 TCK TDO EXTIN0 XTAL2 RESETTRST TDITMS HIGH-SPEED GPI/O

104 PINS

VDD(3V3) VREF VSSA , VSS VECTORED INTERRUPT CONTROLLER 16 kB SRAM USB WITH 4 kB RAM AND DMA GP DMA CONTROLLER I2S INTERFACE SPI, SSP0 INTERFACE I2SRX_SDA I2STX_SDA MISO, MISO0 SSP1 INTERFACE SD/MMC CARD INTERFACE MCICMD, MCIDAT[3:0] TXD0, TXD2, TXD3UART0, UART2, UART3 UART1 DTR1, RTS1 DSR1, CTS1, DCD1, RI1 I2C0, I2C1, I2C2 SDA0, SDA1, SDA2 EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3 A/D CONVERTER D/A CONVERTER 2 kB BATTERY RAM RTC OSCILLATOR REAL- TIME CLOCK WATCHDOG TIMER SYSTEM CONTROL 2 × CAP0/CAP1/ CAP2/CAP3 4 × MAT2, 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 AOUT VBAT AHB TO APB BRIDGE SRAM RMII(8) VBUS 002aad332 P0, P2 power domain 2 AHB2 AHB1 power domain 2 VDD(DCDC)(3V3) A[15:0] D[7:0]EXTERNAL MEMORY CONTROLLER OE, CS0, CS1, BLS0 ALARM

6.1 Pinning

6.2 Pin description

Table 3. Pin description [1] I/O P0[0] —General purpose digital input/output pin. I RD1 — CAN1 receiver input. O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). 67[1] I/O P0[1] —General purpose digital input/output pin. O TD1 — CAN1 transmitter output. I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[2]/TXD0 141 [1] I/O P0[2] —General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. P0[3]/RXD0 142 [1] I/O P0[3] —General purpose digital input/output pin. I RXD0 — Receiver input for UART0. [1] I/O P0[4] —General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in theI2S-bus speciﬁcation. I RD2 — CAN2 receiver input. I CAP2[0] — Capture input for Timer 2, channel 0.

LPC2388_1 © NXP B.V. 2008. All rights reserved. [1] I/O P0[5] —General purpose digital input/output pin. slave. Corresponds to the signal WS in theI2S-bus speciﬁcation. O TD2 — CAN2 transmitter output. I CAP2[1] — Capture input for Timer 2, channel 1. [1] I/O P0[6] —General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in theI2S-bus speciﬁcation. I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. [1] I/O P0[7] —General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in theI2S-bus speciﬁcation. I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. [1] I/O P0[8] —General purpose digital input/output pin. slave. Corresponds to the signal WS in theI2S-bus speciﬁcation. I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. [1] I/O P0[9] —General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in theI2S-bus speciﬁcation. I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. 69[1] I/O P0[10] —General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. 70[1] I/O P0[11] —General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. 29[2] I/O P0[12] —General purpose digital input/output pin. I/O MISO1 — Master In Slave Out for SSP1. O USB_PPWR2 — Port power enable signal for USB port 2. I AD0[6] — A/D converter 0, input 6. [2] I/O P0[13] —General purpose digital input/output pin. conﬁgured or during global suspend. I/O MOSI1 — Master Out Slave In for SSP1. I AD0[7] — A/D converter 0, input 7.

LPC2388_1 © NXP B.V. 2008. All rights reserved. [1] I/O P0[14] —General purpose digital input/output pin. O USB_HSTEN2 — Host Enabled status for USB port 2. I/O SSEL1 — Slave Select for SSP1. 89[1] I/O P0[15] —General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. 90[1] I/O P0[16] —General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. 87[1] I/O P0[17] —General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. 86[1] I/O P0[18] —General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. 85[1] I/O P0[19] —General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. O MCICLK — Clock output line for SD/MMC interface. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). 83[1] I/O P0[20] —General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. I MCICMD — Command line for SD/MMC interface. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). 82[1] I/O P0[21] —General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. O MCIPWR — Power Supply Enable for external SD/MMC power supply. I RD1 — CAN1 receiver input. 80[1] I/O P0[22] —General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. O MCIDAT0 — Data line for SD/MMC interface. O TD1 — CAN1 transmitter output. Table 3. Pin description …continued

LPC2388_1 © NXP B.V. 2008. All rights reserved. [2] I/O P0[23] —General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in theI2S-bus speciﬁcation. I CAP3[0] — Capture input for Timer 3, channel 0. [3] I/O P0[24] —General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. slave. Corresponds to the signal WS in theI2S-bus speciﬁcation. I CAP3[1] — Capture input for Timer 3, channel 1. [2] I/O P0[25] —General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in theI2S-bus speciﬁcation. O TXD3 — Transmitter output for UART3. 8[2] I/O P0[26] —General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — D/A converter output. I RXD3 — Receiver input for UART3. P0[27]/SDA0 35 [4] I/O P0[27] —General purpose digital input/output pin. The output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). P0[28]/SCL0 34 [4] I/O P0[28] —General purpose digital input/output pin. The output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29]/USB_D+1 42 [5] I/O P0[29] —General purpose digital input/output pin. I/O USB_D+1 — USB port 1 bidirectional D+ line. P0[30]/USB_D−14 3 [5] I/O P0[30] —General purpose digital input/output pin. I/O USB_D −1 — USB port 1 bidirectional D− line. P0[31]/USB_D+2 36 [5] I/O P0[31] —General purpose digital input/output pin. I/O USB_D+2 — USB port 2 bidirectional D+ line. block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. [1] I/O P1[0] —General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. 135[1] I/O P1[1] —General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. 133[1] I/O P1[4] —General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. 132[1] I/O P1[8] —General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. 131[1] I/O P1[9] —General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data.

LPC2388_1 © NXP B.V. 2008. All rights reserved. 129[1] I/O P1[10] —General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. 128[1] I/O P1[14] —General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. 126[1] I/O P1[15] —General purpose digital input/output pin. I ENET_REF_CLK/ENET_RX_CLK — Ethernet receiver clock. 125[1] I/O P1[16] —General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock. 123[1] I/O P1[17] —General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MI data input and output. [1] I/O P1[18] —General purpose digital input/output pin. conﬁgured or during global suspend. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. 47[1] I/O P1[19] —General purpose digital input/output pin. O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). O USB_PPWR1 — Port Power enable signal for USB port 1. I CAP1[1] — Capture input for Timer 1, channel 1. [1] I/O P1[20] —General purpose digital input/output pin. O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. [1] I/O P1[21] —General purpose digital input/output pin. O USB_TX_DM1 — D − transmit data for USB port 1 (OTG transceiver). O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. [1] I/O P1[22] —General purpose digital input/output pin. I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver). I USB_PWRD1 — Power Status for USB port 1 (host power switch). O MAT1[0] — Match output for Timer 1, channel 0. [1] I/O P1[23] —General purpose digital input/output pin. I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver). O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. [1] I/O P1[24] —General purpose digital input/output pin. I USB_RX_DM1 — D − receive data for USB port 1 (OTG transceiver). O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0.

LPC2388_1 © NXP B.V. 2008. All rights reserved. 56[1] I/O P1[25] —General purpose digital input/output pin. O USB_LS1 — Low-speed status for USB port 1 (OTG transceiver). O USB_HSTEN1 — Host Enabled status for USB port 1. O MAT1[1] — Match output for Timer 1, channel 1. [1] I/O P1[26] —General purpose digital input/output pin. O USB_SSPND1 — USB port 1 bus suspend status (OTG transceiver). O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. 61[1] I/O P1[27] —General purpose digital input/output pin. I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver). I USB_O VRCR1 — USB port 1 Over-Current status. I CAP0[1] — Capture input for Timer 0, channel 1. [1] I/O P1[28] —General purpose digital input/output pin. I/O USB_SCL1 — USB port 1 I2C-bus serial clock (OTG transceiver). I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. [1] I/O P1[29] —General purpose digital input/output pin. I/O USB_SDA1 — USB port 1 I2C-bus serial data (OTG transceiver). I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 0. 30[2] I/O P1[30] —General purpose digital input/output pin. I USB_PWRD2 — Power Status for USB port 2. I VBUS — Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. 28[2] I/O P1[31] —General purpose digital input/output pin. I USB_O VRCR2 — Over-Current status for USB port 2. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. block. Pins 14 through 31 of this port are not available. [1] I/O P2[0] —General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. [1] I/O P2[1] —General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. O PIPESTAT0 — Pipeline Status, bit 0.

LPC2388_1 © NXP B.V. 2008. All rights reserved. [1] I/O P2[2] —General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O PIPESTAT1 — Pipeline Status, bit 1. [1] I/O P2[3] —General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline Status, bit 2. [1] I/O P2[4] —General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACESYNC — Trace Synchronization. [1] I/O P2[5] —General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. O TRACEPKT0 — Trace Packet, bit 0. [1] I/O P2[6] —General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACEPKT1 — Trace Packet, bit 1. [1] I/O P2[7] —General purpose digital input/output pin. I RD2 — CAN2 receiver input. O RTS1 — Request to Send output for UART1. O TRACEPKT2 — Trace Packet, bit 2. [1] I/O P2[8] —General purpose digital input/output pin. O TD2 — CAN2 transmitter output. O TXD2 — Transmitter output for UART2. O TRACEPKT3 — Trace Packet, bit 3. [1] I/O P2[9] —General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I EXTIN0 — External Trigger Input. P2[10]/EINT0 76 [6] I/O P2[10] —General purpose digital input/output pin. control of the part after a reset. I EINT0 — External interrupt 0 input.

LPC2388_1 © NXP B.V. 2008. All rights reserved. [6] I/O P2[11] —General purpose digital input/output pin. I EINT1 — External interrupt 1 input. O MCIDAT1 — Data line for SD/MMC interface. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in theI2S-bus speciﬁcation. [6] I/O P2[12] —General purpose digital input/output pin. I EINT2 — External interrupt 2 input. O MCIDAT2 — Data line for SD/MMC interface. slave. Corresponds to the signal WS in theI2S-bus speciﬁcation. [6] I/O P2[13] —General purpose digital input/output pin. I EINT3 — External interrupt 3 input. O MCIDAT3 — Data line for SD/MMC interface. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in theI2S-bus speciﬁcation. block. Pins 8 through 22, and 27 through 31 of this port are not available. [1] I/O P3[0] —General purpose digital input/output pin. I/O D0 — External memory data line 0. P3[1]/D1 140 [1] I/O P3[1] —General purpose digital input/output pin. I/O D1 — External memory data line 1. P3[2]/D2 144 [1] I/O P3[2] —General purpose digital input/output pin. I/O D2 — External memory data line 2. P3[3]/D3 2 [1] I/O P3[3] —General purpose digital input/output pin. I/O D3 — External memory data line 3. P3[4]/D4 9 [1] I/O P3[4] —General purpose digital input/output pin. I/O D4 — External memory data line 4. P3[5]/D5 12 [1] I/O P3[5] —General purpose digital input/output pin. I/O D5 — External memory data line 5. P3[6]/D6 16 [1] I/O P3[6] —General purpose digital input/output pin. I/O D6 — External memory data line 6. P3[7]/D7 19 [1] I/O P3[7] —General purpose digital input/output pin. I/O D7 — External memory data line 7. 45[1] I/O P3[23] —General purpose digital input/output pin. I CAP0[0] — Capture input for Timer 0, channel 0. I PCAP1[0] — Capture input for PWM1, channel 0. 40[1] I/O P3[24] —General purpose digital input/output pin. I CAP0[1] — Capture input for Timer 0, channel 1. O PWM1[1] — Pulse Width Modulator 1, output 1.

LPC2388_1 © NXP B.V. 2008. All rights reserved. 39[1] I/O P3[25] —General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. 38[1] I/O P3[26] —General purpose digital input/output pin. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. block. Pins 16 through 23, 26, and 27 of this port are not available. [1] I/O P4[0] —]General purpose digital input/output pin. I/O A0 — External memory address line 0. P4[1]/A1 55 [1] I/O P4[1] —General purpose digital input/output pin. I/O A1 — External memory address line 1. P4[2]/A2 58 [1] I/O P4[2] —General purpose digital input/output pin. I/O A2 — External memory address line 2. P4[3]/A3 68 [1] I/O P4[3] —General purpose digital input/output pin. I/O A3 — External memory address line 3. P4[4]/A4 72 [1] I/O P4[4] —General purpose digital input/output pin. I/O A4 — External memory address line 4. P4[5]/A5 74 [1] I/O P4[5] —General purpose digital input/output pin. I/O A5 — External memory address line 5. P4[6]/A6 78 [1] I/O P4[6] —General purpose digital input/output pin. I/O A6 — External memory address line 6. P4[7]/A7 84 [1] I/O P4[7] —General purpose digital input/output pin. I/O A7 — External memory address line 7. P4[8]/A8 88 [1] I/O P4[8] —General purpose digital input/output pin. I/O A8 — External memory address line 8. P4[9]/A9 91 [1] I/O P4[9] —General purpose digital input/output pin. I/O A9 — External memory address line 9. P4[10]/A10 94 [1] I/O P4[10] —General purpose digital input/output pin. I/O A10 — External memory address line 10. P4[11]/A11 101 [1] I/O P4[11] —General purpose digital input/output pin. I/O A11 — External memory address line 11. P4[12]/A12 104 [1] I/O P4[12] —General purpose digital input/output pin. I/O A12 — External memory address line 12. P4[13]/A13 108 [1] I/O P4[13] —General purpose digital input/output pin. I/O A13 — External memory address line 13. P4[14]/A14 110 [1] I/O P4[14] —General purpose digital input/output pin. I/O A14 — External memory address line 14. P4[15]/A15 120 [1] I/O P4[15] —General purpose digital input/output pin. I/O A15 — External memory address line 15.

LPC2388_1 © NXP B.V. 2008. All rights reserved. P4[24]/OE 127 [1] I/O P4[24] —General purpose digital input/output pin. O OE — LOW active Output Enable signal. P4[25]/BLS0 124 [1] I/O P4[25] —General purpose digital input/output pin. O BLS0 — LOW active Byte Lane select signal 0. 118[1] I/O P4[28] —General purpose digital input/output pin. O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. 122[1] I/O P4[29] —General purpose digital input/output pin. O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. P4[30]/CS0 130 [1] I/O P4[30] —General purpose digital input/output pin. O CS0 — LOW active Chip Select 0 signal. P4[31]/CS1 134 [1] I/O P4[31] —General purpose digital input/output pin. O CS1 — LOW active Chip Select 1 signal. USB_D −2 37 I/O USB_D −2 — USB port 2 bidirectional D− line. DBGEN 6 [1] I DBGEN — JTAG interface control signal. Also used for boundary scanning. TDO 1 [1] O TDO — Test Data out for JTAG interface. TDI 3 [1] I TDI — Test Data in for JTAG interface. TMS 4 [1] I TMS — Test Mode Select for JTAG interface. TRST 5 [1] I TRST — Test Reset for JTAG interface. clock (CCLK) for the JTAG interface to operate. RTCK 143 [1] I/O RTCK — JTAG interface control signal. address 0. TTL with hysteresis, 5 V tolerant. [8] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 33 [8] O Output from the oscillator ampliﬁer. RTCX1 23 [8] I Input to the RTC oscillator circuit. RTCX2 25 [8] O Output from the RTC oscillator circuit. but should be isolated to minimize noise and error.

LPC2388_1 © NXP B.V. 2008. All rights reserved. [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. digital section of the pad is disabled. digital section of the pad is disabled. conﬁguration applies to all functions on this pin. [6] 5 V tolerant pad with 5 ns glitch ﬁlter providing digital I/O functions with TTL levels and hysteresis. [7] 5 V tolerant pad with 20 ns glitch ﬁlter providing digital I/O function with TTL levels and hysteresis. [8] Pad provides special analog functionality. [9] Pad provides special analog functionality. [10] Pad provides special analog functionality. [11] Pad provides special analog functionality. [12] Pad provides special analog functionality. [13] Pad provides special analog functionality. [14] Pad provides special analog functionality.

7.1 Architectural overview

I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. I Leave these pins unconnected. [14] I RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 16 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller The LPC2388 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block. AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB bus. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space. The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

the standard 32-bit ARM set
a 16-bit Thumb set The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system.

7.2 On-chip ﬂash programming memory

The LPC2388 incorporates a 512 kB ﬂash memory system. This memory may be used for both code and data storage. Programming of the ﬂash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the ﬂash while the application is running, allowing a great degree of ﬂexibility for data storage ﬁeld and ﬁrmware upgrades. The ﬂash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. The LPC2388 provides a minimum of 100000 write/erase cycles and 20 years of data retention.

7.3 On-chip SRAM

The LPC2388 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the USB device can be used both for data and code storage, too. The 2 kB RTC can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2388 memory map incorporates several distinct regions as shown inFigure3. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either ﬂash memory (default), boot ROM, or SRAM (seeSection7.26.6).

7.5 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Fig 3. LPC2388 memory map 0.0 GB 1.0 GB TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY 0x0000 0000 0x0007 FFFF 0x0008 0000 RESERVED FOR ON-CHIP MEMORY 64 kB LOCAL ON-CHIP STATIC RAM RESERVED ADDRESS SPACE RESERVED ADDRESS SPACE 0x4000 0000 0x4001 0000 0x7FD0 0000 0x7FE0 0000 0x7FD0 3FFF 0x7FE0 3FFF 0x4000 FFFF 2.0 GB BOOT ROM AND BOOT FLASH (BOOT FLASH REMAPPED FROM ON-CHIP FLASH)

3.0 GB 0xC000 0000RESERVED ADDRESS SPACE

3.75 GB 4.0 GB 3.5 GB AHB PERIPHERALS APB PERIPHERALS 0xE000 0000 0xF000 0000 0xFFFF FFFF USB RAM (16 kB) ETHERNET RAM (16 kB) 002aad331 0x8000 0000 0x8000 FFFF 0x8100 FFFF 0x8100 0000 EXTERNAL MEMORY BANK 0 (64 kB) EXTERNAL MEMORY BANK 1 (64 kB)

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 19 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classiﬁed as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identiﬁes which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classiﬁed as FIQs, have a programmable interrupt priority. When more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered VIC channel will be serviced ﬁrst. The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several interrupt ﬂags. Individual interrupt ﬂags may also represent more than one interrupt source. Any pin on PORT0 and PORT2 (total of 46 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from PORT0 and/or PORT2 will be combined with the EINT3 interrupt requests.

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one function. Conﬁguration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undeﬁned.

7.7 External memory controller

The LPC2388 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and ﬂash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.

7.7.1 Features

Asynchronous static memory device support including RAM, ROM, and ﬂash, with or without asynchronous page mode
Low transaction latency
Read and write buffers to reduce latency and to improve performance
8 data and 16 address lines wide static memory support
Two chip selects for static memory devices

Static memory features include: – Asynchronous page mode read – Programmable Wait States (WST) – Bus turnaround delay – Output enable and write enable delays – Extended wait

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2388 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master.

7.8.1 Features

Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA can transfer data between the 16 kB SRAM and peripherals such as the SD/MMC, two SSP , and I 2S-bus interfaces.
Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a speciﬁc hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced ﬁrst.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the DMA control registers over the AHB slave interface.
One AHB master for transferring data. This interface transfers data when a DMA request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more efﬁciently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral.
Internal four-word FIFO per channel.
Supports 8-bit, 16-bit, and 32-bit wide transactions.

An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred.
Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC2388 use accelerated GPIO functions:

GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved.
Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
All GPIO registers are byte and half-word addressable.
Entire port value can be written in one instruction. Additionally, any pin on PORT0 and PORT2 (total of 46 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.

7.9.1 Features

Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Backward compatibility with other earlier devices is maintained with legacy PORT0 and PORT1 registers appearing at the original addresses on the APB bus.

7.10 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, ﬂow control, control frames, hardware acceleration for transmit retry, receive packet ﬁltering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB trafﬁc in the LPC2388 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 22 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller via the EMC, as well as the SRAM located on another AHB, if it is not being used by the USB block. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.

7.10.1 Features

Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support.
Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory trafﬁc optimized by buffering and pre-fetching.
Enhanced Ethernet features: – Receive ﬁltering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive ﬁlters or a magic frame detection ﬁlter.
Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface.

7.11 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The Host Controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic conﬁguration of the devices. All transactions are initiated by the Host Controller. The LPC2388 USB interface includes a device, Host, and OTG Controller. Details on typical USB interfacing solutions can be found in Section11.1.

7.11.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host Controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM.

7.11.1.1 Features

Fully compliant withUSB 2.0 speciﬁcation (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum speciﬁcation) by software at run time.
Supports SoftConnect and GoodLink features.
While the USB is in the Suspend mode, the LPC2388 can enter one of the reduced power modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.

7.11.2 USB Host Controller

The Host Controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine, and DMA controller. The register interface complies with the OHCI speciﬁcation.

7.11.2.1 Features

OHCI compliant.
Two downstream ports.
Supports per-port power switching.

7.11.3 USB OTG Controller

USB OTG (On-The-Go) is a supplement to the USB 2.0 speciﬁcation that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the Host Controller, device controller, and a master-only I 2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver.

7.11.3.1 Features

Fully compliant withOn-The-Go supplement to the USB 2.0 Speciﬁcation, Revision 1.0a.
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol (SRP).
Supports any OTG transceiver compliant with theOTG Transceiver Speciﬁcation (CEA-2011), Rev. 1.0.

7.12 CAN controller and acceptance ﬁlters

The Controller Area Network (CAN) is a serial communications protocol which efﬁciently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identiﬁers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter.

7.12.1 Features

Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible withCAN speciﬁcation 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identiﬁers for all CAN buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identiﬁers.
FullCAN messages can generate interrupts.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 25 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller 7.13 10-bit ADC The LPC2388 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.

7.13.1 Features

10-bit successive approximation ADC
Input multiplexing among 8 pins
Power-down mode
Measurement range 0 V to Vi(VREF)
10-bit conversion time≥ 2.44µs
Burst conversion mode for single or multiple inputs
Optional conversion on transition of input pin or Timer Match signal
Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2388 to generate a variable analog output. The maximum output value of the DAC is Vi(VREF).

7.14.1 Features

10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive

7.15 UARTs

The LPC2388 contains four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 can be achieved with any crystal frequency above 2 MHz.

7.15.1 Features

16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software ﬂow control implementation.
UART1 equipped with standard modem interface signals. This module also provides full support for hardware ﬂow control (auto-CTS/RTS).

UART3 includes an IrDA mode to support infrared communication.

7.16 SPI serial I/O controller

The LPC2388 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.

7.16.1 Features

Compliant with SPI speciﬁcation
Synchronous, Serial, Full Duplex Communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer

7.17 SSP serial I/O controller

The LPC2388 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data ﬂowing from the master to the slave and from the slave to the master. In practice, often only one of these data ﬂows carries meaningful data.

7.17.1 Features

Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA

7.18 SD/MMC card interface

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Speciﬁcation Version 2.11.

7.18.1 Features

The MCI provides all functions speciﬁc to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer.
Conforms toMultimedia Card Speciﬁcation v2.11.
Conforms toSecure Digital Memory Card Physical Layer Speciﬁcation, v0.96.

Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card.
DMA supported through the GPDMA controller.

7.19 I2C-bus serial I/O controllers

The LPC2388 contains three I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I 2C-bus is a multi-master bus and can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2388 supports bit rates up to 400 kbit/s (Fast I2C-bus).

7.19.1 Features

I2C0 is a standard I2C compliant bus interface with open-drain pins.
I2C1 and I2C2 use standard I/O pins and do not support powering off of individual devices connected to the same bus lines.
Easy to conﬁgure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.

7.20 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus speciﬁcation deﬁnes a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface on the LPC2388 provides a separate transmit and receive channel, each of which can operate as either a master or a slave.

7.20.1 Features

The interface has separate input/output channels each of which can operate in master or slave mode.

Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 48 kHz ((16, 22.05, 32, 44.1, 48) kHz).
Conﬁgurable word select period in master mode (separately for I2S-bus input and output).
Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block.
Controls include reset, stop and mute options separately for I2S-bus input and output.

7.21 General purpose 32-bit timers/external event counters

The LPC2388 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at speciﬁed timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.21.1 Features

A 32-bit Timer/Counter with a programmable 32-bit prescaler.
Counter or Timer operation.
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.

7.22 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2388. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when speciﬁed timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 29 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, speciﬁc match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

7.22.1 Features

LPC2388 has one PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
Pulse period and width can be any number of timer counts. This allows complete ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.23 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

7.23.1 Features

Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in multiples of Tcy(WDCLK) × 4.
The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability.

7.24 RTC and battery RAM

The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2388, the RTC can be clocked by a separate 32.768 kHz oscillator or by a programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device. The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation.

7.24.1 Features

Measures the passage of time to maintain a calendar and clock.
Ultra low power design to support battery powered systems.
Provides Seconds, Minutes, Hours, Day of Month, Month, Y ear, Day of Week, and Day of Y ear.
Dedicated 32 kHz oscillator or programmable prescaler from APB clock.
Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

An alarm output pin is included to assist in waking up from Power-down mode, or when the chip has had power removed to all functions except the RTC and Battery RAM.
Periodic interrupts can be generated from increments of any ﬁeld of the time registers, and selected fractional second values.
2 kB data SRAM powered by VBAT.
RTC and Battery RAM power supply is isolated from the rest of the chip.

7.25 Clocking and power control

7.25.1 Crystal oscillators

The LPC2388 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU. Following reset, the LPC2388 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

7.25.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy. Upon power-up or any chip reset, the LPC2388 uses the IRC as the clock source. Software may later switch to one of the other available clock sources.

7.25.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section7.25.2 for additional information.

7.25.1.3 RTC oscillator

The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU.

7.25.2 PLL

The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and the USB block. The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 32 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must conﬁgure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source.

7.25.3 Wake-up timer

The LPC2388 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V DD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

7.25.4 Power control

The LPC2388 supports a variety of power control features. There are three special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconﬁguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing ﬁne tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The LPC2388 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM.

7.25.4.1 Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

7.25.4.2 Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. The Sleep mode can be terminated and normal operation resumed by either a Reset or certain speciﬁc interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value. The ﬂash memory is left on in Sleep mode, allowing a very quick wake-up. On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconﬁgure the PLL and clock dividers accordingly.

7.25.4.3 Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC oscillator and the ﬂash memory. This saves more power, but requires waiting for resumption of ﬂash operation before execution of code or data access in the ﬂash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60µs to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the ﬂash wake-up timer then counts 4 MHz IRC clock cycles to make the 100µs ﬂash start-up time. When it times out, access to the ﬂash will be allowed. The customers need to reconﬁgure the PLL and clock dividers accordingly.

7.25.4.4 Power domains

The LPC2388 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2388, I/O pads are powered by the 3.3 V (V DD(3V3)) pins, while the VDD(DCDC)(3V3) pin powers the on-chip DC-to-DC converter which in turn provides power to the CPU and most of the peripherals. Depending on the LPC2388 application, a design can use two power options to manage power consumption.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 34 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller The ﬁrst option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the ﬂy” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (V DD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3) ). Having the on-chip DC-to-DC converter powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the ﬂy”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation.

7.26 System control

7.26.1 Reset

Reset has four sources on the LPC2388: theRESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. TheRESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.25.3 “Wake-up timer”), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a ﬁxed number of clocks have passed, and the ﬂash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

7.26.2 Brownout detection

The LPC2388 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts Reset to inactivate the LPC2388 when the voltage on the V DD(3V3) pins falls below 2.65 V. This Reset prevents alteration of the ﬂash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event loop to sense the condition.

7.26.3 Code security (Code Read Protection - CRP)

This feature of the LPC2388 allows user to enable different levels of security in the system so that access to the on-chip ﬂash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a dedicated ﬂash location. IAP commands are not affected by the CRP . There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and ﬂash ﬁeld updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP . This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) ﬂash update mechanism using IAP calls or call reinvoke ISP command to enable ﬂash update via UART0.

7.26.4 AHB

The LPC2388 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 8 kB SRAM primarily intended for use by the USB. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

7.26.5 External interrupt inputs

The LPC2388 includes up to 50 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode.

7.26.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM, the SRAM, or external memory. This allows code running in different memory spaces to have control of the interrupts. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

7.27 Emulation and debugging

The LPC2388 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself.

7.27.1 EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present on the target system. The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ﬂow or even entering the debug state. The DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program ﬂow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate.

7.27.2 Embedded trace

Since the LPC2388 have signiﬁcant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows conﬁguration of the ETM using a JTAG interface and displays the trace information that has been captured. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external Trace Port Analyzer captures the trace information under software debugger control. The trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.

7.27.3 RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2388 contain a speciﬁc conﬁguration of RealMonitor software programmed into the on-chip ROM memory.

LPC2388_1 © NXP B.V. 2008. All rights reserved. static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. [2] Including voltage on outputs in 3-state mode. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. Table 4. Limiting values

LPC2388_1 © NXP B.V. 2008. All rights reserved. [2] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [3] Including voltage on outputs in 3-state mode. DD(3V3) supply voltages must be present. [5] 3-state outputs go into 3-state mode when VDD(3V3) is grounded. [6] Please also see the errata note in errata sheet. [7] Accounts for 100 mV voltage drop in all supply lines. [8] Allowed as long as the current limit does not exceed the maximum current allowed by the device. I= 4.5 V, maximum condition for VI= 5.5 V. [12] Includes external resistors of 18Ω± 1 % on D+ and D−. Tamb = −40 °C to +85°C for commercial applications, unless otherwise speciﬁed. Table 6. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85°C unless otherwise speciﬁed; ADC frequency 4.5 MHz.

LPC2388_1 © NXP B.V. 2008. All rights reserved. [1] Conditions: VSSA =0V , VDDA = 3.3 V. [2] The ADC is monotonic, there are no missing codes. D ) is the difference between the actual step width and the ideal step width. SeeFigure4. appropriate adjustment of gain and offset errors. SeeFigure4. error, and the straight line which ﬁts the ideal transfer curve. SeeFigure4. and the ideal transfer curve. SeeFigure4. Table 6. ADC static characteristics …continued VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85°C unless otherwise speciﬁed; ADC frequency 4.5 MHz.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 43 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E D ). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics 002aab136 1023 1022 1021 1020 1019 (2) (1) 10241018 1019 1020 1021 1022 10237123456 1018 (5) (4) (3)

1 LSB

(ideal) code out VDDA − VSSA 1024 offset error EO gain error EG offset error EO Via (LSBideal)

1 LSB =

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 44 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 5. Suggested ADC interface - LPC2388 AD0[y] pin LPC23XX AD0[y]SAMPLE AD0[y]20 kΩ 3 pF 5 pF R vsi VSS VEXT 002aac610

LPC2388_1 © NXP B.V. 2008. All rights reserved. [1] Characterized but not implemented as production test. Guaranteed by design. [1] Parameters are valid over operating temperature range unless otherwise speciﬁed. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25°C), nominal supply voltages. [3] Bus capacitance Cb in pF , from 10 pF to 400 pF . Table 7. Dynamic characteristics of USB pins (full-speed) C L = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3),unless otherwise speciﬁed. Table 8. Dynamic characteristics

LPC2388_1 © NXP B.V. 2008. All rights reserved. [4] Latest of address valid,CS LOW, OE LOW to data valid. [5] Earliest ofCS HIGH, OE HIGH, address change to data invalid. [6] Byte lane state bit (PB) = 1. Table 9. Dynamic characteristics: Static external memory interface

10.1 Timing

Fig 6. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Fig 7. External memory read access CS addr data OE BLS tCSLAV tOELAV tOELOEH tCSLOEL tam th(D) tCSHOEH tOEHANV 002aad955 tBLSLAV tCSHBLSH

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 49 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 8. External memory write access addr data BLS/WE OE tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tBLSHANV tWEHDNV tBLSHDNV 002aad956 tAVCSL CS Fig 9. Differential data-to-EOP transition skew and EOP width 002aab561 tPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR1 , tEOPR2 crossover point extended differential data to SE0/EOP skew n × tPERIOD + tFDEOP

11.1 Suggested USB interface solutions

Fig 10. MISO line set-up time in SSP Master mode tsu(SPI_MISO) SCK shifting edges MOSI MISO 002aad326 sampling edges Fig 11. LPC2388 USB interface on a self-powered device (applies to USB ports 1 and 2) LPC23XX USB-B connector USB_D+ USB_CONNECT SoftConnect switch USB_D − VBUS VSS VDD(3V3) 1.5 kΩ R S = 33 Ω 002aac578 R S = 33 Ω USB_UP_LED

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 51 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 12. LPC2388 USB interface on a bus-powered device (applies to USB ports 1 and 2) LPC23XX VDD(3V3) 1.5 kΩ USB_UP_LED 002aac579 USB-B connector USB_D+ USB_D − VBUS VSS R S = 33 Ω R S = 33 Ω

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 52 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 13. LPC2388 USB OTG port conﬁguration: USB port 1 OTG dual-role device, USB port 2 host USB_UP_LED1 USB_D+1 USB_D −1 USB_PWRD2 USB_SDA1 USB_SCL1 RSTOUT 15 kΩ 15 kΩ LPC2388 USB-A connector Mini-AB connector 33 Ω 33 Ω 33 Ω 33 Ω VDD VDD VDD USB_UP_LED2 VDD USB_OVRCR2 LM3526-L ENA IN 5 V OUTA FLAGA VDD D − VBUS USB_PPWR2 USB_D+2 USB_D −2 002aad336 R4 R5 R6 R1 R2 R3 R4 USB_INT1 RESET_N ADR/PSW SPEED SUSPEND OE_N/INT_N SCL SDA INT_N VBUS ID DP DM ISP1301 VSS VSS

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 53 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 14. LPC2388 USB OTG port conﬁguration: VP_VM mode USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 USB_SCL1 USB_SDA1 SPEED ADR/PSW SDA SCL RESET_N INT_N VP VM SUSPEND OE_N/INT_N SE0_VM DAT_VP RCV VBUS ID DP DM LPC2388 ISP1301 USB MINI-AB connector 33 Ω 33 Ω 002aad337 USB_TX_E1 RSTOUT VDD VDD USB_INT1 USB_UP_LED1 VDD VSS

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 54 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 15. LPC2388 USB OTG port conﬁguration: USB port 2 device, USB port 1 host USB_UP_LED1 USB_D+1 USB_D −1 USB_PWRD1 15 kΩ 15 kΩ LPC2388 USB-A connector USB-B connector 33 Ω 33 Ω 33 Ω 33 Ω 002aad335 VDD USB_UP_LED2 USB_CONNECT2 VDD VDD USB_OVRCR1 USB_PPWR1 LM3526-L ENA IN 5 V FLAGA OUTA VDD D − D − VBUS USB_D+2 USB_D −2 VBUS VBUS VSS VSS

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 55 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller Fig 16. LPC2388 USB OTG port conﬁguration: USB port 1 host, USB port 2 host USB_UP_LED1 USB_D+1 USB_D −1 USB_PWRD1 USB_PWRD2 15 kΩ 15 kΩ 15 kΩ 15 kΩ LPC2388 USB-A connector USB-A connector 33 Ω 33 Ω 33 Ω 33 Ω 002aad338 VDD USB_UP_LED2 VDD USB_OVRCR1 USB_OVRCR2 USB_PPWR1 LM3526-L ENA ENB IN 5 V FLAGA OUTA OUTB FLAGB VDD VDD D − D − VBUS VBUS USB_PPWR2 USB_D+2 USB_D −2 VSS VSS

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 56 of 61 NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller 12. Package outline Fig 17. Package outline SOT486-1 (LQFP144) UNIT A 1 A 2 A 3 bp cE (1) eH E LL p Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 o o0.080.2 0.081 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT486-1 136E23 MS-026 00-03-14 03-02-20 D (1) (1)(1) 20.1 19.9 H D 22.15 21.85 EZ 1.4 1.1 D 0 5 10 mm scale bpe q E A 1 A Lp detail X L (A )3 B c bp EH A 2 DH v M B D Z D A Z E e v M A X y w M w M A max. 1.6 LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 108 109 pin 1 index 144

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I 2C-bus — logo is a trademark of NXP B.V. SoftConnect —is a trademark of NXP B.V. GoodLink — is a trademark of NXP B.V. 16. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

LPC2388_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 19 December 2008 60 of 61 continued >> NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller 17. Contents 7.19 I

7.21 General purpose 32-bit timers/external

7.26.3 Code security (Code Read Protection - CRP) 35

NXP Semiconductors LPC2388 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 December 2008 Document identifier: LPC2388_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

Product Information

C2388 specifications and overview.

Summary

Single-chip 16-bit/32-bit micro; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 01-19 December 2008

Description

Single-chip 16-bit/32-bit micro; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 01-19 December 2008

Source title C2388 Datasheet(PDF) - NXP Semiconductors

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