C1851BCU

UPC1851B NEC | Alldatasheet

Document overview

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• PDF pages: 60

Technical content

Datasheet sections

• 2.1 Stereo Demodulation Block
• 2.2 SAP Demodulation Block
• 2.4 Matrix Block
• 2.5 Selector Block
• 3.1 Data Transfer
• 3.2 Data Transfer Format
• 4.1 Subaddress List
• 4.2 Setting Procedure
• 4.3 Explanation of Write Register
• 4.4 Explanation of Read Register
• 7.1 Caution on Shock Noise Reduction
• 7.2 Supply Voltage
• 7.3 Impedance of Input and Output Pins
• 7.4 Drive Capability of Output Pins
• 7.5 Caution on External Components
• 7.6 Change of Electrical Characteristics by External Components

BIPOLAR ANALOG INTEGRATED CIRCUIT µPC1851B I2C BUS-COMPATIBLE US MTS PROCESSING LSI The µPC1851B is an integrated circuit for US MTS (Multiplexed Television Sound) system with the addition of the I2C bus interface. All functions required for US MTS system are incorporated on a single chip. The µPC1851B allows users to switch modes, control volume and tone, and adjust the separation circuit through the I2C bus.

FEATURES

• Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, I2C bus interface, input selector (2 channels), surround processor (1 phase), volume and tone control circuits incorporated on a single chip
• Mode switching, volume and tone control, and separation adjustment through the I2C bus
• Power supply: 8 V to 10 V
• On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control)
• Output level: 1.4 Vp-p (with L+R signals, 100 % modulation) APPLICATION
• TV sets and VCRs for north America

ORDERING INFORMATION

µPC1851BCU 42-pin plastic SDIP (15.24 mm (600)) The µPC1851B is available only to licensees of THAT Corporation. For information, please call: (508) 229-2500 (U.S.A), or (03) 5790-5391 (Tokyo). The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. The mark shows major revised points. © 1998 DATA SHEET Document No. S13417EJ2V0DS00 (2nd edition) Date Published June 2000 N CP(K) Printed in Japan

µPC1851B Data Sheet S13417EJ2V0DS00 SYSTEM BLOCK DIAGRAM l TV Tuner DTS interface Tuning microcontroller Remote controller receive amp. IF processing PC1851B SCL SDA R L C, Y, and deflecting signal output Chroma output Vertical output CRT Power amplifier PIN photodiode Graphic equalizer (Surround processor) MTS processing LL RR µ

µPC1851B Data Sheet S13417EJ2V0DS00 BLOCK DIAGRAM DGND 24 SCL 23 SDA 22 D2 6 D1 5 PD1 3 PD2 4 I2C Bus Interface L+R LPF Switch 1 F 0.1 F 2 1/2VCC 22 F VRE 1 F MOA MOR 34 MOL ER1 ER2 EL1 EL2 FOL FOR Input Attenuator D/AFilter Control Filter +0.1 F LBC +2.2 F TLO2200 pF LTC 1VCC LOT +10 F ROT +10 F RBC TRO RTC AGND 0.1 F 2200 pF 2.2 F 0.022 F

27 SUR

0.1 F Noise BPF Noise DetectorD/A 9 COM 2.2 F SOA 0.1 F SDT 0.047 F VOA WTI WRB STI SRB dO ITI* SI SOT ++ + 3.3 F 5.1 kΩ 10 F 16.6 kΩ 0.47 F 68 kΩ 1 kΩ

4.7 F I2C Bus

+3 kΩ NDT 1 F 1 F 1 F VOL-C 4.7 F D/A Volume Control Tone Control Surround Block Matrix Block Selector Block dbx Noise Reduction Block Offset Absorption De- emphasis SAP Demodulation Block Stereo Demodulation Block 9 V µ µ µ µ µ µ µ µ µ µ φ φ µ µ µ µ µ µµ µ µ µ µ µ µ µ Remark Use the followings for external parts. Resistor (*): Metal film resistor (– 1 %). Unless otherwise specified; –5 % Capacitors (**): Tantalum capacitor (–10 %). Unless otherwise specified; –20 %

µPC1851B Data Sheet S13417EJ2V0DS00 STEREO DEMODULATION BLOCK SAP DEMODULATION BLOCK From Input Attenuator Stereo LPF Pilot Canceler L–R AM Demodulator To Switch To L+R LPF Stereo Phase Comparator Pilot Discrimination Phase Comparator To I C bus Interface Stereo VCO PD1 PD2 D/A Divider φ φ From Input Attenuator 8SDT SOA SAP BPF Phase Detector Loop Filter SAP VCO To Noise BPF Offset Absorption SAP Detector To I C bus Interface SAP LPF SOT D/A

µPC1851B Data Sheet S13417EJ2V0DS00 dbx NOISE REDUCTION BLOCK SELECTOR BLOCK Notes 1. Switch (TV signal/External input 1/External input 2). 2. The input gain 0 dB/6 dB can be selected by the command of the I2C bus (refer to 4.3 (5) Input gain). From Switch LPF fH Trap 408-Hz LPF 2 fH Trap 2.19-kHz LPF Offset Absorption Spectral RMS Filter Wide-band RMS Filter Wide-band VCA Offset Absorption To Matrix Block dO SRB STI WTI WRB VOA D/AD/A Spectral RMS Timing Current ITI Variable Emphasis Wide-band RMS 40 kΩ ER1 ER2 EL1 EL2 40 kΩ 40 kΩ 40 kΩ To Surround Block To Surround Block Switch (Monaural/Stereo) Switch Note1 From Matrix Block (L-channel signal) From Matrix Block (R-channel signal) Note2 Note2

µPC1851B Data Sheet S13417EJ2V0DS00 SURROUND BLOCK Phase Shifter– From Selector Block (L-channel) From Selector Block (R-channel) To Tone Control Block To Tone Control Block SUR

µPC1851B Data Sheet S13417EJ2V0DS00 PIN CONFIGURATION (Top View) 42-pin plastic SDIP (15.24 mm (600))

• µPC1851BCU VCC VRE PD1 PD2 COM SDT NDT SOT SI SOA STI SRB ITI WTI WRB dO VOL-C VOA AGND MOA FOL FOR EL1 ER1 EL2 ER2 MOL MOR LBC LTC TLO RBC RTC TRO SUR LOT ROT DGND SCL SDA Monaural Offset Absorption L-channel Fixed Output R-channel Fixed Output External L-channel Input 1 External R-channel Input 1 External L-channel Input 2 External R-channel Input 2 L-channel Matrix Output R-channel Matrix Output L-channel Capacity of Low Frequency Band Width L-channel Capacity of High Frequency Band Width L-channel Offset Absorption R-channel Capacity of Low Frequency Band Width R-channel Capacity of High Frequency Band Width R-channel Offset Absorption Surround Timing L-channel Output R-channel Output Digital GND (for I C bus) SCL (for I C bus) SDA (for I C bus) Power Supply (9 V) Vcc Filter Pilot Discrimination Filter 1 Pilot Discrimination Filter 2 Phase Comparator Filter 1 Phase Comparator Filter 2 Composite Signal Input SAP Discrimination Filter Noise Detector Filter SAP Single Output SAP Single Input SAP Offset Absorption Spectral RMS Timing Spectral RMS Offset Absorption Timing Current Setting Wide-band RMS Timing Wide-band RMS Offset Absorption Variable Emphasis Offset Absorption Volume Control Offset Absorption VCA Offset Absorption Analog GND φ φ

µPC1851B Data Sheet S13417EJ2V0DS00 1. PIN EQUIVALENT CIRCUITS (1/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

1 Power Supply (9 V) V CC

2 V CC Filter VRE

3 Pilot Discrimination Filter 1 PD1

4 Pilot Discrimination Filter 2 PD2

20 kΩ 5 kΩ 10 kΩ 10 kΩ20 kΩ 5 kΩ 10 kΩ 10 kΩ 20 kΩ 20 kΩ GND VCC 15 kΩ 15 kΩ 5 kΩ 15 kΩ15 kΩ 5 kΩ VCC VCC VCC

µPC1851B Data Sheet S13417EJ2V0DS00 (2/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

5 Phase Comparator Filter 1 φD1

6 Phase Comparator Filter 2 φD2

7 Composite Signal Input COM

8 SAP Discrimination Filter SDT

5 kΩ 15 kΩ 5 kΩ 5 kΩ15 kΩ 5 kΩ VCC VCC VCC 5 kΩ 5 kΩ 17 kΩ3 kΩ 80 kΩ GND VCC VCC GND VCC 20 kΩ20 kΩ 20 kΩ 10 kΩ 10 kΩ

µPC1851B Data Sheet S13417EJ2V0DS00 (3/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

9 Noise Detector Filter NDT

10 SAP Single Output SOT

20 kΩ20 kΩ 20 kΩ 20 kΩ 20 kΩ 20 kΩ20 kΩ VCC GND 2 kΩ 2 kΩ 200 Ω

µPC1851B Data Sheet S13417EJ2V0DS00 (4/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

11 SAP Single Input SI

12 SAP Offset Absorption SOA

13 Spectral RMS Timing STI

5 kΩ 10 kΩ 10 kΩ VCC GND 5 kΩ 80 kΩ VCC 10 kΩ10 kΩ VCC 5 pF 3 kΩ50 kΩ 10 kΩ2.3 kΩ GND 5 kΩ 600 Ω GND 5 kΩ 5 kΩ 5 kΩ VCC 5 kΩ

µPC1851B Data Sheet S13417EJ2V0DS00 (5/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

14 Spectral RMS Offset Absorption SRB

15 Timing Current Setting ITI

16 Wide-band RMS Timing WTI Same as pin 13

17 Wide-band RMS Offset Absorption WRB Same as pin 14

18 Variable Emphasis Offset dO

5 kΩ 5 kΩ GND 3 kΩ 3 kΩ 3 kΩ 5 kΩ 5 kΩ VCC 30 kΩ GND 10 kΩ 10 kΩ 10 kΩ VCC 10 kΩ 20 pF 5 kΩ 10 kΩ 10 kΩ VCC GND 10 kΩ 10 kΩ 20 kΩ 20 kΩ 6 pF 10 kΩ 50 kΩ 3 kΩ

µPC1851B Data Sheet S13417EJ2V0DS00 (6/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

19 Volume Control Offset Absorption VOL-C

20 VCA Offset Absorption VOA Same as pin 12

21 Analog GND AGND

22 SDA (for I

2C bus) Note SDA

23 SCL (for I 2C bus) Note SCL

24 Digital GND (for I2C bus) DGND

Note A protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line down to 0 V while the power supply is off (VCC = 0 V). 10 kΩ 10 kΩ 10 kΩ 30 kΩ30 kΩ VCC 5 kΩ GND 10 kΩ 10 kΩ 10 kΩ 30 kΩ30 kΩ VCC 50 kΩ 5 kΩ GND VCC GND 5 kΩ5 kΩ 20 kΩ 5 pF 10 kΩ 10 kΩ10 kΩ 5 kΩ 10 kΩ 10 kΩ 5 kΩ 25 kΩ

µPC1851B Data Sheet S13417EJ2V0DS00 (7/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

25 R-channel Output ROT

26 L-channel Output LOT Same as pin 25

27 Surround Timing SUR

28 R-channel Offset Absorption TRO

10 kΩ 5 kΩ 1 kΩ 200 Ω 200Ω 1 kΩ 5 kΩ VCC GND VCC 20 kΩ40 kΩ 20 kΩ 24 kΩ 2 kΩ GND VCC 35 kΩ 5 kΩ 35 kΩ 5 kΩ GND 40 kΩ 10 kΩ10 kΩ

µPC1851B Data Sheet S13417EJ2V0DS00 (8/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

29 R-channel Capacity of High RTC

30 R-channel Capacity of Low RBC

31 L-channel Offset Absorption TLO Same as 28

32 L-channel Capacity of High LTC Same as 29

33 L-channel Capacity of Low LBC Same as 30

34 R-channel Matrix Output MOR Same as 25

35 L-channel Matrix Output MOL

36 kΩ 5 kΩ 36 kΩ 5 kΩ GND 40 kΩ 10 kΩ 10 kΩ VCC 5 kΩ1 kΩ 5.3 kΩ 3 kΩ 2.5 kΩ GND 5 kΩ

µPC1851B Data Sheet S13417EJ2V0DS00 (9/9) Pin No. Pin Name Symbol Internal Equivalent Circuit

36 External R-channel Input 2 ER2

37 External L-channel Input 2 EL2

38 External R-channel Input 1 ER1

39 External L-channel Input 1 EL1

40 R-channel Fixed Output FOR Same as pin 25

41 L-channel Fixed Output FOL

42 Monaural Offset Absorption MOA Same as pin 18

10 kΩ10 kΩ 15 pF 40 kΩ 40 kΩ 10 kΩ I2C Bus

µPC1851B Data Sheet S13417EJ2V0DS00 2. BLOCK FUNCTIONS

2.1 Stereo Demodulation Block

(1) Stereo LPF This filter eliminates signals in the vicinity of 5 fH to 6 fH , such as SAP (Sub Audio Program) (5 fH ) and telemetry signals (6.5 fH ) . The µPC1851B’s internal L–R demodulator, which uses a double-balanced circuit, demodulates L–R signals by multiplication of the L–R signal with the signal at the L–R carrier frequency (2 fH ). The L–R signal tends to receive interference from the 6 fH signal because a square waveform is used as the switching carrier in this method. To eliminate this interference, the µPC1851B incorporates traps at 5 fH and 6 fH . The filter response is adjusted by setting the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5). (2) Stereo Phase Comparator The 8 fH signal generated at the Stereo VCO is divided by 8 (4 × 2) and then multiplied by the pilot signal passed through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase. The resistor and capacitor connected to the φD1 and φD2 pins form a filter that smoothes the phase error signal output from the Stereo Phase Comparator, converting the error signal to the DC voltage. When the voltage difference between φD1 and φD2 pins becomes 0 V (strictly speaking, not 0 V by the internal offset voltage), the VCO runs at 8 fH . The lag/lead filter externally connected to the pins φD1 and φD2 determines the capture range. (3) Stereo VCO The Stereo VCO runs at 8 fH with the internal capacitor. The frequency is adjusted by setting the STEREO VCO SETTING bits (Write register, subaddress 01H, bits D0 to D5). (4) Divider (Flip-flop) Produces two separate fH signals: the inphase fH signal, and the fH signal differing by 90 degrees from the input pilot signal by dividing the 8 fH frequency from the Stereo VCO by 8 (4 × 2). (5) Pilot Discrimination Phase Comparator (Level detector) Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC voltage that is used to determine whether or not a stereo pilot is present (Read register, bit D6). (6) Pilot Canceler The fH signal from the divider is added to the stereo signal matrix depending on the level of the input pilot signal to cancel the pilot signal. (7) L+R LPF This LPF which has traps at fH and 24 kHz, allows only the monaural signal to pass through. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (8) De-emphasis The 75-µs de-emphasis filter is for the monaural signal. The response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (9) L–R AM Demodulator Demodulates the L–R AM-DSB modulated signal by multiplying with the 2-fH signal which is synchronized to the pilot signal. The 2-fH square wave is used as the switching carrier.

µPC1851B Data Sheet S13417EJ2V0DS00

2.2 SAP Demodulation Block

(1) SAP BPF Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 fH . The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (2) Noise BPF The µPC1851B monitors signals picked up by the noise BPF (fO = 180 kHz), and distinguishes noise from signals. By this method, the µPC1851B prevents faulty SAP detection in a weak electric field. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). (3) Noise Detector Performs full-wave rectification of noise from noise BPF, changes it to the DC voltage, and inputs it to the comparator. When the noise level exceeds the reference level, the Noise detection bit (Read register, bit D4) turns “1”. The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor connected to the NDT pin. (4) SAP Detector Detects the signal from the SAP BPF and smoothes it through the SDT pin and inputs it to the comparator. When it detects the SAP signal, the SAP broadcast (Broadcast status) (Read register, bit D5) turns “1”. (5) SAP Demodulator The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit). The SAP VCO oscillates at 10 f H , and performs phase comparison between the signal divided by 2 of the SAP VCO frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the SAP VCO SETTING bit (Write register, subaddress 05H, bits D0 to D5). (6) SAP LPF Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order LPF and fH trap filter. The filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5). . .

µPC1851B Data Sheet S13417EJ2V0DS00 2.3 dbx Noise Reduction Block All the filters required for TV-dbx Noise Reduction are incorporated. These filter responses are adjusted by setting all the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5). (1) LPF This LPF has traps at fH and 24 kHz each. The fH trap filter minimizes interference by the fH signal which is not synchronized with the pilot signal (for example, leakage of the synchronous idle and buzz from the video signal). (2) 408-Hz LPF This filter is a de-emphasis filter. Its transfer function is as follows: f1 + j 5.23kT(f) = f1 + j 408 (3) Variable Emphasis It is also called the spectral VCA. It is controlled by the spectral RMS. The transfer function is as follows: f 1 + 51b1 + j x20.1k b + 1S –1 (f, b) = f 1 + 511 + j x20.1k b + 1 where “b” is the variable transferred from the spectral RMS for controlling. (4) Wide-band VCA A VCA whose operating frequency range is mainly low to mid frequencies and controlled by the wide-band RMS. The transfer function is as follows: W –1 (a) = a where “a” is the variable transferred from the wide-band RMS for controlling. (5) 2.19-kHz LPF This filter is a de-emphasis filter. Its transfer function is as follows: f1 + j 62.5kT(f) = f1 + j 2.19k (6) Spectral RMS Filter A filter that limits the band width of the signal input to the RMS which controls the variable emphasis. The transfer function is as follows: ff( j )2 j7.66k 3.92kT (f) = x ff f1 + j + ( j )2 1 + j7.31k 7.66k 3.92k

µPC1851B Data Sheet S13417EJ2V0DS00 (7) Wide-band RMS Filter A filter that limits the band width of the signal input to the wide-band RMS which controls the wide-band VCA. The transfer function is as follows: 1T(f) = f1 + j 2.09k (8) Spectral RMS Detects the RMS value of the signal passed through the spectral RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current IT of the µPC1851B and the capacitance of the external capacitor connected to the STI pin. The current IT is adjusted by adjusting the current from the ITI pin. (9) Wide-band RMS Detects the RMS value of the signal passed through the wide-band RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current IT of the µPC1851B and the capacitance of the external capacitor connected to the WTI pin. The current IT is adjusted by adjusting the current from the ITI pin.

2.4 Matrix Block

(1) Matrix Adds L+R signal and L–R signal to output L signal, and substracts L+R signal from L–R signal to output R signal. (2) Mode Selector The matrix block selects the signal from the monaural signal, Stereo signal, SAP signal by the User Mode.

2.5 Selector Block

It selects the signal from the TV signal (signal with the audio multiple signal processed in the µPC1851B) and external input (signal input from EL1, EL2, ER1 and ER2 pins), and outputs it to the surround processor block (surround, tone control, and volume control block). It also selects the gain of the selection signal (0 dB/6 dB) as well as switches the stereo/monaural output (by the I 2C bus).

µPC1851B Data Sheet S13417EJ2V0DS00 3. I2C BUS INTERFACE The µPC1851B uses a 2-wire serial bus developed by Philips. The serial clock line (SCL) and serial data line (SDA) employ the 2-wire configuration as shown in Figure 3-1. The µPC1851B contains an I2C bus interface circuit, eleven (8-bit) read/write registers, and one read-only register. Serial Clock Line (SCL) The master CPU outputs a serial clock to achieve data synchronicity. The µPC1851B receives serial data based on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz. Serial Data Line (SDA) The master CPU outputs data synchronously with the serial clock. The µPC1851B receives this data based on the serial clock. The input level is CMOS-compatible Figure 3-1. Internal Equivalent Circuit of Interface Pins For SCL and SDA pins, a protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line down to 0 V while the power supply is off (VCC = 0 V). SCL SDA RP RP PC1851Bµ

µPC1851B Data Sheet S13417EJ2V0DS00

3.1 Data Transfer

(1) Start condition The start condition is created when SDA changes from high to low while SCL is high, as shown in Figure 3-2. When the µPC1851B receives this information, it captures data sent in synchronization with the clock. (2) Stop condition The stop condition is created when SDA changes from low to high while SCL is high, as shown in Figure 3-2. When the µPC1851B receives this information, it stops receiving or outputting data. Figure 3-2. Data Transfer Start/Stop Condition (3) Data transfer When transferring data, be sure to switch data only when SCL is low, as shown in Figure 3-3. When SCL is high, the data must not be changed. Figure 3-3. Data Transfer Notes 1. Data hold time: 300 ns MIN. 2. Data setup time: 250 ns MIN. 3. Interval when data must not be changed. 4. Interval when data can be changed. SDA SCL 3.5 V 1.5 V 3.5 V 1.5 V 4.0 s MIN. 4.7 s MIN. Start Stop µ µ SDA SCL Note 2Note 1 Note 3 Note 4

µPC1851B Data Sheet S13417EJ2V0DS00

3.2 Data Transfer Format

An example of data transfer in the write mode is shown in Figure 3-4. Figure 3-4. Data Transfer Example in Write Mode Data consists of 8-bit units. This 8-bit data must always be followed by an acknowledge bit. Data transfer must be done on an MSB-first basis. The first byte after a start condition specifies the slave address. The slave address consists of 7 bits. Table 3-1 shows the slave addresses of the µPC1851B. These slave addresses are registered by Philips. Table 3-1. Slave Addresses of µPC1851B Slave address D6 D5 D4 D3 D2 D1 D0 Read/Write Mode Write 1 0 1 1 0 0 0 0 Read 1 0 1 1 0 0 0 1 The bit following the slave address is the read/write bit specifying the direction of the data to be transferred. During the read operation, data is transferred from the µPC1851B to the master CPU. During the write operation, data is transferred from the master CPU to the µPC1851B. “0” and “1” are written to the READ/WRITE bit during the Write and Read modes, respectively. The byte following the slave address is the subaddress of the µPC1851B in the write mode. The µPC1851B has eleven subaddresses, SA0 to SAA, which are made up of 8 bits. Following the subaddress byte is the data to be set to the subaddress. Start Slave address SubaddressRead/ write Acknow- ledge Acknow- ledge Acknow- ledge Data Stop D6SDA SCL D5 D4 D3 D2 D1 D0 Write mode D6 D5D7 D4 D3 D2 D1 D0 D6 D5D7 D4 D3 D2 D1 D0 123456789 123456789 123456789

µPC1851B Data Sheet S13417EJ2V0DS00 (1) 1-byte data transfer The format for 1-byte data transfer is the following: (2) Continuous data transfer The format when transferring multiple (7) bytes of data at one time by using the automatic increment function is the following: The master CPU transfers “00H” as subaddress SA0 following the start condition and slave address. After the subaddress SA0, the master CPU transfers the SA0 data, and continues with SA1, SA2,..., SAA data without transferring stop conditions in between. Finally, the stop condition is transferred and the transfer is completed. (3) Data read The µPC1851B has one read register. The contents of this register can be read by the master CPU. The format when data is read is the following: (4) Acknowledge In the case of the I2C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data transfer was successful. The master CPU determines the success or failure of data transfer based on whether this acknowledge bit is a logical low or high. If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical high, this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus. Start Slave address Write mode Acknow -ledge Subaddress Acknow -ledge Data Acknow -ledge Stop Start Slave address Write mode Acknow -ledge Subaddress Acknow -ledge Data1 Acknow -ledge Data2 Acknow -ledge Acknow -ledge StopData7 Start Slave address Acknow -ledge Data Non- acknow -ledge StopRead

µPC1851B Data Sheet S13417EJ2V0DS00 (5) Automatic increment The µPC1851B has the automatic increment function. The automatic increment is applied to the subaddresses 00H to 05H of the write register. The user can set ON/OFF the automatic increment of the subaddresses 06H to 0AH (refer to 4.1 Subaddress List). Automatic increment ON: The subaddress is automatically increased. Setting the slave address and subaddress once enables the data of the next subaddress to be transferred without actually setting it. Automatic increment OFF: The subaddress is fixed. The data of the fixed subaddress can be set time after time. The increment of the subaddresses 06H to 0AH is individually controlled by each automatic increment ON/OFF bit. For example, if the automatic increment function of the subaddress 06H is set to ON and that of the subaddress 07H set to OFF, the subaddress is to be automatically increased from 06H to 07H and then fixed to 07H. Though the automatic increment function of the subaddress 0AH is set to ON, the subaddress is not to be increased. After setting the data of 0AH (acknowledge bit: low level), if the next data is transferred, the acknowledge is to be in non-acknowledge state (acknowledge bit: high level) and the data transfer from the master CPU is aborted.

µPC1851B Data Sheet S13417EJ2V0DS00 4. I2C BUS COMMANDS

4.1 Subaddress List

(1) Write register (command list) Bit MSB LSB Sub- D7 D6 D5 D4 D3 D2 D1 D0 address 00H 0 During noise Input level setting detection Stereo/SAP output stop 0: SAP OFF 1: Stereo, SAP OFF 01H 0 f H monitor Stereo VCO setting ON/OFF 0: OFF 1: ON 02H 0 Pilot canceler Filter setting ON/OFF 0: ON 1: OFF 03H 0 Input gain Low-band separation setting 0: 0 dB 1: 6 dB 04H 0 Surround High-band separation setting 0: OFF 1: ON 05H 0 5f H monitor SAP VCO setting ON/OFF 0: OFF 1: ON 06H Automatic Input select 1 Input select 2SAP1/SAP2 Stereo/SAP Forced Mute increment 00: TV signal 0: Stereo switch Note switch monaural 0: ON 0: OFF 01: External input 1 1: Monaural 0: SAP1 0: Stereo 0: OFF 1: OFF 1: ON 10: External input 2 1: SAP2 1: SAP 1: ON 11: Setting prohibited 07H 0 Automatic Volume control increment 0: OFF 1: ON 08H 0 Automatic Balance control increment 0: OFF 1: ON 09H 0 Automatic Bass control increment 0: OFF 1: ON 0AH 0 Automatic Treble control increment 0: OFF 1: ON

µPC1851B Data Sheet S13417EJ2V0DS00 Note Output when SAP1 or SAP2 is selectd is as follows: L-channel output (LOT pin) R-channel output (ROT pin) SAP1 SAP SAP2 Monaural (L+R) SAP (2) Read register MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Broadcast status Reception status Power-on reset Stereo pilot SAP signal Noise detection Stereo broadcast SAP broadcast reception reception 1 1 0: Not available 0: Not available 0: Not available 0: Not available 0: Not available 1: Detect 1: Available 1: Available 1: Available 1: Available 1: Available

µPC1851B Data Sheet S13417EJ2V0DS00

4.2 Setting Procedure

Precise adjustment of the dbx decoder is absolutely critical for optimum performance. Where possible, the adjustment should be performed after the µPC1851B is mounted on the chassis and with the video system active. Set the data of write register as follows before the adjustment. Table 4-1. Default Setting of Write Register Bit D7 D6 D5 D4 D3 D2 D1 D0 Subaddress 00H 0 0 1 0 0 0 0 0 01H 0 0 1 0 0 0 0 0 02H 0 0 1 1 1 1 1 1 03H 0 0 1 0 0 0 0 0 04H 0 0 1 0 0 0 0 0 05H 0 0 1 0 0 0 0 0 06H 0 0 0 0 0 0 0 1 07H 0 1 1 1 1 1 1 1 08H 0 1 1 0 0 0 0 0 09H 0 1 1 0 0 0 0 0 0AH 0 1 1 0 0 0 0 0 (1) Input level setting (Write register, subaddress 00H, bits D5 to D0) <1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H. <2> Input sine wave of 300 Hz, 150 mVrms to COM pin. <3> Set bits D5 to D0 (INPUT LEVEL SETTING bits) of subaddress 00H so that the output level of FOR pin is 500 mV rms (±10 mV rms). (2) Stereo VCO setting (Write register, subaddress 01H, bits D6 to D0) Perform this adjustment with no signal applied. <1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H. <2> Write “1” to bit D6 (fH monitor: ON) of subaddress 01H. <3> Connect frequency counter to FOR pin, and set bits D5 to D0 (STEREO VCO SETTING bits) of subaddress 01H so that frequency counter displays 15.73 kHz (±0.1 kHz). <4> When setting is completed, write “0” to bit D6 (fH monitor: OFF) of subaddress 01H.

µPC1851B Data Sheet S13417EJ2V0DS00 (3) Filter setting (Write register, subaddress 02H, bits D6 to D0) <1> Write “1” to bit D6 (Pilot canceler: OFF) of subaddress 02H. <2> Input pilot signal (15.734 kHz, 30 mVrms or higher Note) to COM pin and set data of bits D5 to D0 (FILTER SETTING bits) of subaddress 02H so that the AC output level of the FOR pin becomes as small as possible (Decrease the set data from 63 (decimal)). <3> When setting is completed, write “0” to bit D6 (pilot canceler: ON) of subaddress 02H. Note Recommended 100 mV rms. (4) Separation setting (Write register, subaddresses 03H and 04H, bits D5 to D0) <1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H. <2> Write “20H” to bits D5 to D0 (HIGH-BAND SEPARATION SETTING bits) of subaddress 04H. <3> Input composite signal to COM pin (300 Hz, 30 % modulation, L-only, with noise reduction), and set bits D5 to D0 (LOW-BAND SEPARATION SETTING bits) of subaddress 03H so that the output level of the FOR pin is as small as possible. <4> Change the modulation frequency of the composite signal to 3 kHz, and set bits D5 to D0 of subaddress 04H so that the output level of the FOR pin is as small as possible. <5> While bits D5 to D0 of subaddress 04H are set as in step <4> above, repeat the setting procedure of step <3> for bits D5 to D0 of subaddress 03H. (5) SAP VCO setting (Write register, subaddress 05H, bits D6 to D0) Perform this adjustment with no signal applied. <1> Add a 1 MΩ resistor between the SOA pin and GND. <2> Write “1” to bit D0 (Mute: OFF) of subaddress 06H. <3> Write “1” to bit D6 (5 fH monitor: ON) of subaddress 05H. <4> Connect a frequency counter to the FOR pin, and set bits D5 to D0 of subaddress 05H (SAP VCO SETTING bits) so that 78.67 kHz (±0.5 kHz) is displayed on the frequency counter. <5> When setting is completed, write “0” to bit D6 (5 fH monitor: OFF) of subaddress 05H. <6> Delete the 1 MΩ resistor between the SOA pin and GND.

µPC1851B Data Sheet S13417EJ2V0DS00

4.3 Explanation of Write Register

(1) Stereo/SAP output stop function during noise detection Stereo/SAP output stop can be selected with the data of bit D6 of subaddress 00H during weak electrical field conditions (recommended noise level during circuit use is 34 mVrms (TYP.) or more). SAP output stop : Only SAP output is stopped. SAP and stereo output stop : SAP and stereo outputs are stopped, switch to monaural output. Noise level detection is performed, when detected a noise about at 11.5 fH (180 kHz), a frequency that is sufficiently apart from that of the high frequency signals such as the stereo, SAP, and telemetry signal. If noise is detected, “1” is set to bit D4 of the read register (Refer to section 4.4, (4) Noise detection) Figure 4-1. Stereo/SAP Output Stop Function During Noise Detection (2) Mute The mute function can be set ON/OFF with the data of bit D0 of subaddress 06H. The mute on state is entered when bit D0 is set to 0 after power-on reset. Figure 4-2. Mute Caution When switching the power ON/OFF, use the external mute (200 ms) in order to minimize shock noise. D7 D6 D5 D4 D3 D2 D1 D0 000H During noise detection Input level setting Stereo/SAP output stop function during noise detection SAP output stop SAP and stereo output stopD7 D6 D5 D4 D3 D2 D1 D0 Automatic increment 06H Input select 1 Input select 2 SAP1/SAP2 switch Stereo/SAP switch Forced monaural ON/OFF Mute ON/OFF Mute ON Mute OFF Mute

µPC1851B Data Sheet S13417EJ2V0DS00 (3) Mode switch (L-, R-channel output (LOT, ROT pins)) The output signal for the L- and R-channel outputs (LOT, ROT pins) can be selected with bits D3 to D1 of subaddress 06H. For the combinations of data of each output signal bit, refer to 5. MODE MATRIX . Forced monaural ON/OFF : When set to ON, a monaural signal is forcibly output regardless of the selection of other bits. Stereo/SAP switch : When forced monaural is set to OFF, performs selection of stereo or SAP. SAP1/SAP2 switch : When SAP output is selected with the stereo/SAP switch, performs selection of SAP1 or SAP2. L-Channel Output (LOT pin) R-Channel Output (ROT pin) SAP1 SAP output SAP2 Monaural (L+R) output SAP output Figure 4-3. Mode Switch (L-, R-Channel Output (LOT, ROT pins)) D7 D6 D5 D4 D3 D2 D1 D0 Automatic increment06H Input select 1 SAP1/SAP2 switch Stereo/SAP switch Forced monaural ON/OFF Mute ON/OFF Forced monaural Forced monaural OFF Forced monaural ON Stereo/SAP switch Stereo output SAP output SAP1/SAP2 switch SAP1 output SAP2 output Input select 2

µPC1851B Data Sheet S13417EJ2V0DS00 (4) Input select The signal to be input to the selector block in the µPC1851B can be selected by the data of bits D4 to D6 of subaddress 06H. The selected signal is output from the LOT, ROT, FOL and FOR pins. For the combination of bits for the signal to be selected, refer to 6. SELECTOR TABLE . Input select 1 : switches the TV signal (signal with the audio multiple signal processed in the µPC1851B) and external inputs 1 and 2 (signal input from EL1, EL2, ER1 and ER2 pins). Input select 2 : switches the stereo signal and monaural signal. Figure 4-4. Input Select Note When SAP2 is selected by switching SAP1/SAP2, the L+R signal and SAP signal are composite to be output. 06H Automatic increment Input select 1 Input select 2 SAP1/SAP2 switch Stereo/SAP switch D6 D5 D4 D3 D2 D1 D0 TV signal External input 1 External input 2 Setting prohibited Input select 1 L-channel signal Note R-channel signal Monaural (L+R) signal L-channel output (LOT, FOL pins) R-channel output (ROT, FOR pins) Input select 2 Forced monaural ON/OFF Mute

µPC1851B Data Sheet S13417EJ2V0DS00 (5) Input gain The gain of the signal to be input to the selector block in the µPC1851B can be selected by the data of bit D6 of subaddress 03H. Figure 4-5. Input Gain 03H 0 dB 6 dB Input gain

0 Input gain Low-band separation setting

(6) Surround function The surround function ON/OFF can be selected by the data of bit D6 of subaddress 04H. Figure 4-6. Surround Function 04H Surround OFF Surround ON Surround function D6 D5 D4 D3 D2 D1 D0

0 Surround High-band separation setting

µPC1851B Data Sheet S13417EJ2V0DS00 (7) Volume, Balance control The volume and balance of the output (LOT and ROT pins) can be controlled at 64 levels by the data of bits D0 to D5 of subaddresses 07H and 08H. The volume attenuation is 80 dB or higher. Figure 4-7. Volume, Balance Control

• Volume control
• Balance control Data D5 - D0 07H Volume control D6 D5 D4 D3 D2 D1 D0

0 Automatic

Flat (0 dB) Low 08H D6 D5 D4 D3 D2 D1 D0 L-ch Low, R-ch Flat TYP. L-ch Flat, R-ch Low

µPC1851B Data Sheet S13417EJ2V0DS00 (8) Bass, Treble control The bass and treble sound quality of the output (LOT and ROT pins) can be controlled at 64 levels by the data of the bits D0 to D5 of subaddresses 09H and 0AH. The bass control amount of the low frequency band width boost/cut is ±11 dB TYP. at 100 Hz. The treble control amount of the high frequency band width boost/cut is ±13 dB TYP. at 10 kHz. Figure 4-8. Bass, Treble control

• Bass control
• Treble control Data D5 - D0 09H Bass control D6 D5 D4 D3 D2 D1 D0

µPC1851B Data Sheet S13417EJ2V0DS00 (9) Automatic increment function The automatic increment function ON/OFF can be selected by the data of bit D7 of subaddress 06H and that of bit D6 of subaddresses 07H to 0AH. For the details of the automatic increment function, refer to 3.2 (5) Automatic increment. Figure 4-9. Automatic Increment Function Caution After power-on reset, be sure to set the data. 06H Automatic increment Input select 1 Input select 2 SAP1/SAP2 switch Stereo/SAP switch D6 D5 D4 D3 D2 D1 D0 Automatic increment function OFF Automatic increment function ON Automatic increment function Forced monaural ON/OFF Mute

µPC1851B Data Sheet S13417EJ2V0DS00

4.4 Explanation of Read Register

(1) Power-on reset detection Whether a power-on reset was detected is detected with bit D7 of the read register. Figure 4-10. Power-On Reset Detection (2) Stereo, SAP broadcast (broadcast status) detection Whether SAP or stereo broadcast from a broadcasting station is being broadcast is detected with bits D5 and D6 of the read register. When a SAP signal (5 fH ) or stereo pilot signal is detected, the register data becomes “1”. Figure 4-11. Stereo, SAP Broadcast (Broadcast Status) Detection D7 D6 D5 D4 D3 D2 D1 D0 Power-on reset Noise detection 11 Broadcast status Stereo broadcast SAP broadcast Power-on reset detection Power-on reset detection Stereo broadcast reception SAP broadcast reception Reception status D7 D6 D5 D4 D3 D2 D1 D0 Power-on reset Noise detection 11 Broadcast status Stereo broadcast SAP broadcast Stereo broadcast reception SAP broadcast reception Reception status Stereo broadcast SAP broadcast (SAP signal detected) No SAP broadcast SAP broadcast No Stereo broadcast Stereo broadcast (stereo pilot signal detected)

µPC1851B Data Sheet S13417EJ2V0DS00 5. MODE MATRIX Mute OFF (Write register, subaddress 06H, bit D0 : “1”) (1) Read register, bit D4: 0 Broadcast Write Register Output Read Register mode Forced Stereo SAP1 Stereo L-ch R-ch Broadcast status Reception status monaural /SAP /SAP2 /SAP output output Stereo SAP Stereo SAP ON/OFF switch switch output (LOT ) (ROT) pilot signal broadcast broadcaststop reception reception Subaddress Subaddress 06H 00H Bit D1 Bit D2 Bit D3 Bit D6 Bit D6 Bit D5 Bit D3 Bit D2 Monaural –––– L + R 0000 Stereo 0––– L R 1010

1 L+R 0

Monaural+SAP 00–– L + R 0100 1 0 SAP 1

1 L+R SAP

1–– L + R 0 Stereo+SAP 00–– L R 1110

10 S A P 01

1–– L + R 0 (2) Read register, bit D4: 1 Broadcast Write Register Output Read Register mode Forced Stereo SAP1 Stereo L-ch R-ch Broadcast status Reception status monaural /SAP /SAP2 /SAP outputl output Stereo SAP Stereo SAP ON/OFF switch switch output (LOT) (ROT) pilot signal broadcast broadcaststop reception reception Subaddress Subaddress 06H 00H Bit D1 Bit D2 Bit D3 Bit D6 Bit D6 Bit D5 Bit D3 Bit D2 Monaural –––– L + R 0000 Stereo 0––0 L R 1010

1 L+R 0 0

Monaural+SAP 0100 L + R 0000 Stereo+SAP 00–0 L R 1010 Remarks 1. When the µPC1851B recognizes a weak electric field, bit D4 of the read register becomes “1”. 2. —: Don’t care.

µPC1851B Data Sheet S13417EJ2V0DS00 6. SELECTOR TABLE Input signal: TV signal (signal with the audio multiple signal processed in the µPC1851B) L-channel, R-channel External input 1 (signal input from EL1, ER1 pins) L-channel, R-channel External input 2 (signal input from EL2, ER2 pins) L-channel, R-channel Write Register Output Mute ON/OFF Input select 1 Input select 2 L-channel output R-channel output Subaddress : 06H (LOT, FOL pins) (ROT, FOR pins) Bit : D0 Bits : D6, D5 Bit : D4 0 – – – Mute 1 00 0 TV signal (L) TV signal (R)

01 External input 1 (L) External input 1 (R)

10 External input 2 (L) External input 2 (R)

11 Setting prohibited (no signal, unconnected)

00 1 TV signal (L+R)

01 External input 1 (L+R)

10 External input 2 (L+R)

Remark – : Don’t care

µPC1851B Data Sheet S13417EJ2V0DS00 7. USAGE CAUTIONS

7.1 Caution on Shock Noise Reduction

When switching the power ON/OFF, use the external mute (approx. 200 ms) in order to minimize shock noise (Refer to section 4.3 (2) Mute).

7.2 Supply Voltage

Pass data through the I2C bus only after stabilizing the supply voltage of the entire application system.

7.3 Impedance of Input and Output Pins

Table 7-1. Impedance of Input and Output Pins Input pin Output pin Symbol Description Impedance Symbol Description Impedance COM Composite signal input 80 k Ω SOT SAP single input 360 Ω SI SAP single input ROT R-channel output 15 Ω EL1, EL2 External L-channel input LOT L-channel output ER1, ER2 External R-channel input MOR R-channel matrix output MOL L-channel matrix output FOR R-channel fixed output FOL L-channel fixed output

7.4 Drive Capability of Output Pins

Table 7-2. Drive Capability of Output Pins Pin symbol Pin description Output pin-GND Connection Resistance Drive capability SOT SAP single output 10 k Ω 3-kΩ load or less ROT R-channel output 700- Ω load or less LOT L-channel output MOR R-channel matrix output MOL L-channel matrix output FOR R-channel fixed output FOL L-channel fixed output Remark If the load capacitance of the output pins (SOT, ROT, LOT, MOR, MOL, FOR, FOL pins) exceeds 100 pF, parasitic oscillation may occur. In this case, connect a resistor between the output pins and the load capacitance. Bear in mind that the load capacitance is changed by wiring pattern on the printed circuit board.

µPC1851B Data Sheet S13417EJ2V0DS00

7.5 Caution on External Components

According to the license contract with THAT Corporation, use the following for external components. With regard to the use of other external components, please contact to THAT corporation. Table 7-3. External Components Pin symbol Pin description External component ITI Timing current setting Metal film resistor ( ±1 %) STI Spectral RMS timing Tantalum capacitor ( ±10 %) WTI Wide-band RMS timing

7.6 Change of Electrical Characteristics by External Components

(1) SAP sensitivity can be lowered by inserting a resistor between the SDT pin and GND. (2) Noise sensitivity can be changed by changing the value of the resistor between the NDT pin and GND. (3) The capture range can be changed by changing the recommended 1 µF value of the capacitor between the φD1 and φD2 pins. Reducing the capacitor value increases the capture range, and increasing it reduces the capture range. However, too small a capacitor value may cause the distortion rate to become worse during stereo output, or may cause malfunction. In this case, please contact NEC.

µPC1851B Data Sheet S13417EJ2V0DS00 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (unless otherwise specified, TA = 25 °C) Parameter Symbol Conditions Ratings Unit Power supply voltage V CC VCC pin 11.0 V I2C bus input pin voltage V cont SDA, SCL pins V CC V Composite signal input voltage V in COM pin V CC V Package power dissipation P D 700 mW Operating ambient temperature T A VCC = 9 V –20 to +75 °C Storage temperature T stg –40 to +125 °C Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. Recommended Operating Conditions (unless otherwise specified, TA = 25 ˚C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage V CC VCC pin 8.0 9.0 10.0 V I2C bus input pin voltage (High level)Vcont(H) SDA, SCL pins 3.5 – 5.0 V I2C bus input pin voltage (Low level)Vcont(L) 0 – 1.5 V Input impedance R in COM, SI, EL1, EL2, ER1, ER2 pins 60 – 95 k Ω Output load impedance 1 R L1 LOT, ROT, MOL, MOR, FOL, FOR pins, 2.0 – – k Ω AC load impedance at 100 % modulation Output load impedance 2 R L2 SOT pin, AC load impedance at 100 % 10.0 – – k Ω modulation Output load impedance 3 R L3 LOT, ROT, MOL, MOR, FOL, FOR pins, 5.0 – – k Ω DC load impedance at 100 % modulation Output load impedance 4 R L4 SOT pin, DC load impedance at 100 % 25.0 – – k Ω modulation Composite signal input voltage V in COM pin L+R signal, 100 % modulation – 0.424 – V p-p L–R signal, 100 % modulation – 0.848 – V p-p Pilot signal – 0.0848 – V p-p SAP signal – 0.254 – V p-p External input signal voltage V ext EL1, EL2, ER1, ER2 pins – 1.4 5.6 V p-p Clock frequency f SCL SCL pin – – 100 kHz

µPC1851B Data Sheet S13417EJ2V0DS00

Electrical Characteristics

(unless otherwise specified, TA = 25 °C, RH ≤ 70 %, VCC = 9.0 V, adding 30 kHz LPF to output pins) (1/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input: COM pin, Output: FOL, FOR pins Supply current I CC No signal – 57 75 mA Stereo detection input sensitivity ST SENCE 15.734 kHz, sine wave 11 16 21 mV rms Stereo detection hysteresis ST HY Only stereo pilot signal input 5.0 5.7 10 dB Stereo detection capture range ST CCL Vin = 30 mVrms –5.5 –4.0 –2.5 % ST CCH Only stereo pilot signal input +2.5 +4.0 +5.5 % SAP detection input sensitivity SAP SENCE f = 78.67 kHz, 0% modulation 17 23 30 mV rms SAP detection hysteresis SAP HY Only SAP carrier input 3.3 4.8 6.3 dB Noise detection input sensitivity NO SENCE Input sine wave 20 30 40 mV rms f: Noise BPF peak Noise detection hysteresis NO HY Input sine wave 1 2 3 dB f: Noise BPF peak Monaural total output voltage V OMO 300 Hz, 100% modulation, 480 500 520 mV rm Pre-emphasis: ON Stereo total output voltage V OST 300 Hz, 100 % modulation 450 500 550 mV rms SAP total output voltage V OSAP1 Noise reduction: ON 400 500 600 mV rms Difference between monaural L and R V OLR 300 Hz, 100% modulation –0.5 – +0.5 dB output voltage Monaural total frequency characteristics 1 V OMO1 1 kHz, 30% modulation, (f = 300 Hz: 0 dB) –0.5 – +0.5 dB Pre-emphasis: ON Monaural total frequency characteristics 2 VOMO2 3 kHz, 30% modulation, (f = 300 Hz: 0 dB) –0.5 – +0.5 dB Pre-emphasis: ON Monaural total frequency characteristics 3 VOMO3 8 kHz, 30% modulation, (f = 300 Hz: 0 dB) –0.8 – +0.8 dB Pre-emphasis: ON Monaural total frequency characteristics 4 VOMO4 12 kHz, 30% modulation, (f = 300 Hz: 0 dB) –5.5 –3.0 –1.5 dB Pre-emphasis: ON Stereo total frequency characteristics 1 VOST1 1 kHz, 30% modulation, (f = 300 Hz: 0 dB) –0.5 – +0.5 dB Noise reduction: ON Stereo total frequency characteristics 2 VOST2 3 kHz, 30% modulation, (f = 300 Hz: 0 dB) –0.5 – +0.5 dB Noise reduction: ON Stereo total frequency characteristics 3 VOST3 8 kHz, 30% modulation, (f = 300 Hz: 0 dB) –1.0 – +1.0 dB Noise reduction: ON Stereo total frequency characteristics 4 VOST4 12 kHz, 30% modulation, (f = 300 Hz: 0 dB) –8.0 –5.0 –2.0 dB Noise reduction: ON SAP total frequency characteristics 1 V OSAP11 1 kHz, 30% modulation, (f = 300 Hz: 0 dB) –1.2 +0.3 +1.2 dB Noise reduction: ON SAP total frequency characteristics 2 V OSAP12 3 kHz, 30% modulation, (f = 300 Hz: 0 dB) –1.2 0.0 +1.2 dB Noise reduction: ON SAP total frequency characteristics 3 V OSAP13 8 kHz, 30% modulation, (f = 300 Hz: 0 dB) –4.0 –1.0 +1.0 dB Noise reduction: ON Stereo channel separation 1 Sep 1 300 Hz, 30% modulation 27 32 – dB

µPC1851B Data Sheet S13417EJ2V0DS00 (2/3) Parameter Symbol Conditions MIN. TYP. MAX. Unit Stereo channel separation 2 Sep 2 1 kHz, 30% modulation 23 30 – dB Stereo channel separation 3 Sep 3 3 kHz, 30% modulation 27 35 – dB Stereo channel separation 4 Sep 4 5 kHz, 30 % modulation 23 30 – dB Stereo channel separation 5 Sep 5 8 kHz, 30 % modulation – 25 – dB Monaural total harmonic distortion THD MO 1 kHz, 100% modulation – 0.1 0.5 % Pre-emphasis: ON Stereo total harmonic distortion 1 THD ST1 1 kHz, 100% modulation – 0.3 1.5 % Noise reduction: ON Stereo total harmonic distortion 2 THD ST2 8 kHz, 30% modulation – 0.8 1.8 % Noise reduction: ON SAP total harmonic distortion THD SAP 1 kHz, 100% modulation – 0.5 2.0 % Noise reduction: ON Crosstalk 1 (SAP → Stereo) CT 1 SAP : 1 kHz, 100 % modulation – – –65 dB Stereo : Pilot signal only, 0 % modulation Filter: 1 kHz BPF User mode: Stereo Crosstalk 2 (Stereo → SAP) CT 2 Stereo : 1 kHz, 100 % modulation, – – –65 dB SAP : Carrier only, 0 % modulation Filter: 1 kHz BPF User mode: SAP1 Monaural total S/N S/N MO 300 Hz, 100% modulation 65 68 – dB Pre-emphasis: ON Stereo total S/N S/N ST 300 Hz, 100 % modulation 60 65 – dB SAP total S/N S/N SAP Noise reduction: ON 70 80 – dB Input: External input pins, output: LOT, ROT pins Total muting level Mute TV signal : 1 kHz, 100 % modulation 80 – – dB External input : 1 kHz, 500 mVrms Timing current I T Current provided to STI and WTI pins 7.1 7.5 7.9 µA Inter-mode DC offset 1 V DOF1 Mute → Monaural –50 – +50 mV Inter-mode DC offset 2 V DOF2 Mute → Stereo –50 – +50 mV Inter-mode DC offset 3 V DOF3 Mute → SAP1 –50 – +50 mV Inter-mode DC offset 4 V DOF4 Mute → External input –50 – +50 mV Surround output characteristics 1 V SR1L External L-channel input : 100 Hz, 150 mVrms –7.5 –4.5 0.0 dB Surround : ON, LOT pin Surround output characteristics 2 V SR2L External L-channel input : 1 kHz, 150 mVrms 4.0 5.6 7.0 dB Surround : ON, LOT pin Surround output characteristics 3 V SR3L External L-channel input : 10 kHz, 150 mVrms 4.5 – 8.0 dB Surround : ON, LOT pin Surround output characteristics 4 V SR4R External L-channel input : 1 kHz, 150 mVrms –1.5 – +1.5 dB Surround : ON, ROT pin

µPC1851B Data Sheet S13417EJ2V0DS00 (3/3) Parameter Symbol Conditions Sub- Data MIN. TYP. MAX. Unit address Low frequency band width boost control V BB 100 Hz, 09H 3FH 9 11 13 dB Low frequency band width cut control V BC External input = 150 mVrms 00H –13 –11 –9 dB High frequency band width boost control VTB 10 kHz, 0AH 3FH 10 13 16 dB High frequency band width cut control V TC External input = 150 mVrms 00H –16 –13 –10 dB Volume attenuation 1 ATT VL1 1 kHz, 07H 3FH –1.0 0.0 +1.0 dB Volume attenuation 2 ATT VL2 External input = 500 mVrms 20H –20 –17.5 –14 dB Volume attenuation 3 ATT VL3 00H – – –80 dB Balance attenuation L-ch 1 ATT BL1 1 kHz, 08H 3FH – – –60 dB Balance attenuation L-ch 2 ATT BL2 External input = 500 mVrms 30H –14 –10 –6 dB Balance attenuation L-ch 3 ATT BL3 20H –1.0 0.0 +1.0 dB Balance attenuation L-ch 4 ATT BL4 00H –1.0 0.0 +1.0 dB Balance attenuation R-ch 1 ATT BR1 3FH –1.0 0.0 +1.0 dB Balance attenuation R-ch 2 ATT BR2 20H –1.0 0.0 +1.0 dB Balance attenuation R-ch 3 ATT BR3 10H –14 –10 –6 dB Balance attenuation R-ch 4 ATT BR4 00H – – –60 dB Difference between monaural L and R V OLR1 1 kHz, 07H 3FH –1.5 0.0 +1.5 dB output voltage 1 External input = 500 mV rms (in case of external input) Difference between monaural L and R V OLR2 20H –2.0 0.0 +2.0 dB output voltage 2 (in case of external input) Difference between monaural L and R V OLR3 10H –3.0 0.0 +3.0 dB output voltage 3 (in case of external input) Crosstalk 3 CT 3 TV signal: 1 kHz, 07H 3FH – – –80 dB TV signal → External input 100 % modulation Crosstalk 4 CT 4 External input: – –80 –70 dB L-ch → R-ch 1 kHz, 500 mV rms Total harmonic distortion THD EXT 1 kHz, 07H 3FH – 0.1 0.5 % (in case of external input) External input = 500 mV rms Maximum input voltage of external input VIEM 1 kHz, 07H 3FH 1.7 2.1 – V rms Total harmonic distortion rate: 1 % (External input) Output noise NO No signal, R g = 600 Ω , 07H 3FH – 50 150 µVrms (in case of external input) Filter: DIN/AUDIO

µPC1851B Data Sheet S13417EJ2V0DS00 Test Condition Parameters for Electrical Characteristics (Unless otherwise specified, TA = 25 ˚C, RH ≤ 70 %, VCC = 9 V, adding 30 kHz LPF to output pins) (1/8) Parameter Symbol Test Conditions User Mode Note Supply current I CC ICC : Current sent to VCC pin when there is no signal Monaural Stereo detection input ST SENCE ST SENCE : Input signal level of COM pin (input signal: 15.734 kHz) Stereo sensitivity When read register D6 changes from 0 to 1 Stereo detection hysteresis ST HY ST HY =20 log (STSENCE ÷ V) ST SENCE : Stereo detection input sensitivity V: Input signal level of COM pin (Input signal: 15.734 kHz) Read register D6 is first set to 1, then input signal level is gradually lowered until D6 is changed to 0 Stereo detection ST CCL ST CCL = Δ f ÷ 15.734 kHz capture range Δ f: Difference between f and 15.734 kHz f: Input signal (14.5 kHz, 30 mVrms) to COM pin. Gradually raise frequency and measure frequency when read register D6 becomes 1. ST CCH ST CCH = Δ f ÷ 15.734 kHz Δf: Difference between f and 15.734 kHz f: Input signal (17.0 kHz, 30 mVrms) to COM pin. Gradually lower frequency and measure frequency when read register D6 becomes 1. SAP detection input SAP SENCE SAP SENCE : Input signal level of COM pin (input signal: 78.67 kHz) SAP sensitivity When read register D5 changes from 0 to 1 SAP detection hysteresis SAP HY SAP HY =20 log (SAPSENCE ÷ V) SAPSENCE : SAP detection input sensitivity V: Input signal level of COM pin (Input signal: 78.67 kHz) When read register D5 is first set to 1, input signal level is gradually lowered until D5 becomes 0. Noise detection input NO SENCE NO SENCE : Input signal level of COM pin SAP sensitivity Read register D4: Apply 6-V DC voltage to SDT pin to change it to 0 Read register D4: Input signal (160 kHz, 10 mVrms) to COM pin. Raise the frequency until the DC voltage of the NDT pin reaches the maximum level, and then, while maintaining the frequency level, gradually raise the input signal level until D4 becomes 1. Noise detection hysteresis NOHY NO HY = 20 log (NOSENCE ÷ V) NOSENCE : Noise detection input sensitivity V: Input signal level of NDT pin COM pin: Signal (160 kHz, 10 mV rms) input After read register D4 is set to 1, raise the frequency until the DC voltage of the NDT pin reaches the maximum level, and then, while maintaining the frequency level, gradually lower the input signal level until D4 becomes 0. Monaural total output voltageVOMO VOMO : Output voltage of FOL and FOR pins Monaural COM pin: Monaural signal (300 Hz, 100 % modulation) input Stereo total output voltage VOST L-channel Stereo VOST : Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 100 % modulation) input R-channel V OST : Output voltage of FOR pin COM pin: Stereo signal (R-only, 300 Hz, 100 % modulation) input Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 (2/8) Parameter Symbol Test Conditions User Mode Note Note For details about the User Mode, refer to 5. MODE MATRIX . SAP total output voltage V OSAP1 VOSAP1 : Output voltage of FOL and FOR pins SAP1 COM pin: SAP signal (300 Hz, 100 % modulation) input Difference between monaural VOLR VOLR = 20 log (VL ÷ VR ) Monaural L and R output voltage VL: Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 100 % modulation) input V R : Output voltage of FOR pin COM pin: Monaural signal (300 Hz, 100 % modulation) input Monaural total frequency V OMO1 VOMO1 = 20 log {V(1k) ÷ V(300)} Monaural characteristics 1 V(1k): Output voltage of FOL pin COM pin: Monaural signal (1 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input Monaural total frequency V OMO2 VOMO2 = 20 log {V(3k) ÷ V(300)} characteristics 2 V(3k): Output voltage of FOL pin COM pin: Monaural signal (3 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input Monaural total frequency V OMO3 VOMO3 = 20 log {V(8k) ÷ V(300)} characteristics 3 V(8k): Output voltage of FOL pin COM pin: Monaural signal (8 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input Monaural total frequency V OMO4 VOMO4 = 20 log {V(12k) ÷ V(300)} characteristics 4 V(12k): Output voltage of FOL pin COM pin: Monaural signal (12 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Monaural signal (300 Hz, 30 % modulation) input Stereo total frequency V OST1 VOST1 = 20 log {V(1k) ÷ V(300)} Stereo characteristics 1 V(1k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input Stereo total frequency V OST2 VOST2 = 20 log {V(3k) ÷ V(300)} characteristics 2 V(3k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input Stereo total frequency V OST3 VOST3 = 20 log {V(8k) ÷ V(300)} characteristics 3 V(8k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input Stereo total frequency V OST4 VOST4 = 20 log {V(12k) ÷ V(300)} characteristics 4 V(12k): Output voltage of FOL pin COM pin: Stereo signal (L-only, 12 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input

µPC1851B Data Sheet S13417EJ2V0DS00 SAP total frequency V OSAP11 VOSAP11 = 20 log {V(1k) ÷ V(300)} SAP1 characteristics 1 V(1k): Output voltage of FOL pin COM pin: SAP signal (1 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: SAP signal (300 Hz, 30 % modulation) input SAP total frequency V OSAP12 VOSAP12 = 20 log {V(3k) ÷ V(300)} characteristics 2 V(3k): Output voltage of FOL pin COM pin: SAP signal (3 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: SAP signal (300 Hz, 30 % modulation) input SAP total frequency V OSAP13 VOSAP13 = 20 log {V(8k) ÷ V(300)} characteristics 3 V(8k): Output voltage of FOL pin COM pin: SAP signal (8 kHz, 30 % modulation) input V(300): Output voltage of FOL pin COM pin: SAP signal (300 Hz, 30 % modulation) input Stereo channel Sep 1 L-channel Stereo separation 1 Sep 1 = 20 log (VL ÷ VR ) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 300 Hz, 30% modulation) input V R : Output voltage of FOR pin COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input R-channel Sep 1 = 20 log (VR ÷ VL) VR : Output voltage of FOR pin COM pin: Stereo signal (R-only, 300 Hz, 30 % modulation) input V L: Output voltage of FOL pin COM pin: Stereo signal (R-only, 300 Hz, 30 % modulation) input Stereo channel Sep 2 L-channel separation 2 Sep 2 = 20 log (VL ÷ VR ) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input V R : Output voltage of FOR pin COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input R-channel Sep 2 = 20 log (VR ÷ VL) VR : Output voltage of FOR pin COM pin: Stereo signal (R-only, 1 kHz, 30 % modulation) input V L: Output voltage of FOL pin COM pin: Stereo signal (R-only, 1 kHz, 30 % modulation) input Stereo channel Sep 3 L-channel separation 3 Sep 3 = 20 log (VL ÷ VR ) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input V R : Output voltage of FOR pin COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input R-channel Sep 3 = 20 log (VR ÷ VL) VR : Output voltage of FOR pin COM pin: Stereo signal (R-only, 3 kHz, 30 % modulation) input V L: Output voltage of FOL pin COM pin: Stereo signal (R-only, 3 kHz, 30 % modulation) input (3/8) Parameter Symbol Test Conditions User Mode Note Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 Stereo channel separation 4Sep 4 L-channel Stereo Sep 4 = 20 log (VL ÷ VR ) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 5 kHz, 30 % modulation) input V R : Output voltage of FOR pin COM pin: Stereo signal (L-only, 5 kHz, 30 % modulation) input R-channel Sep 4 = 20 log (VR ÷ VL) VR : Output voltage of FOR pin COM pin: Stereo signal (R-only, 5 kHz, 30 % modulation) input V L: Output voltage of FOL pin COM pin: Stereo signal (R-only, 5 kHz, 30 % modulation) input Stereo channel separation 5Sep 5 L-channel Sep 5 = 20 log (VL ÷ VR ) VL: Output voltage of FOL pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input V R : Output voltage of FOR pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input R-channel Sep 5 = 20 log (VR ÷ VL) VR : Output voltage of FOR pin COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input V L: Output voltage of FOL pin COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input Monaural total harmonic THD MO THD MO : Distortion rate of FOL and FOR pins Monaural distortion COM pin: Monaural signal (1 kHz, 100 % modulation) input Stereo total harmonic THD ST1 L-channel Stereo distortion 1 THD ST1 : Distortion rate of FOL pin COM pin: Stereo signal (L-only, 1 kHz, 100 % modulation) input R-channel THD ST1 : Distortion rate of FOR pin COM pin: Stereo signal (R-only, 1 kHz, 100 % modulation) input Stereo total harmonic THD ST2 L-channel distortion 2 THD ST2 : Distortion rate of FOL pin COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input R-channel THD ST2 : Distortion rate of FOR pin COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input SAP total harmonic THD SAP THD SAP : Distortion rate of FOL and FOR pins SAP1 distortion COM pin: SAP signal (1 kHz, 100 % modulation) input Crosstalk 1 (SAP→ Stereo) CT 1 CT 1 = 20 log (VCT1 ÷ 500 mV) Stereo VCT1 : Measure output voltage of FOL or FOR pins after BPF (1 kHz) SAP: 1 kHz, 100 % modulation Stereo: Pilot signal only, 0 % modulation Crosstalk 2 (Stereo→ SAP) CT 2 CT 2 = 20 log (VCT2 ÷ 500 mV) SAP1 VCT2 : Measure output voltage of FOL or FOR pins after BPF (1 kHz) Stereo: 1 kHz, 100 % modulation SAP: Carrier only, 0 % modulation (4/8) Parameter Symbol Test Conditions User Mode Note Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 (5/8) Parameter Symbol Test Conditions User Mode Note Monaural total S/N S/N MO L-channel Monaural S/NMO = 20 log (VOMOL ÷ VL) VOMOL : Output voltage of FOL pin after LPF (30 kHz) COM pin: Monaural signal (300 Hz, 100 % modulation) input V L: Output voltage of FOL pin (no signal) R-channel S/NMO = 20 log (VOMOR ÷ VR ) VOMOR : Output voltage of FOR pin after LPF (30 kHz) COM pin: Monaural signal (300 Hz, 100 % modulation) input VR : Output voltage of FOR pin (no signal) Stereo total S/N S/N ST L-channel Stereo S/NST = 20 log (VOSTL ÷ VL) VOSTL : Output voltage of FOL pin after LPF (30 kHz) COM pin: Stereo signal (L-only, 300 Hz, 100 % modulation) input V L: Output voltage of FOL pin COM pin: Pilot signal input R-channel S/NST = 20 log (VOSTR ÷ VR ) VOSTR : Output voltage of FOR pin after LPF (30 kHz) COM pin: Stereo signal (R-only, 300 Hz, 100 % modulation) input V R : Output voltage of FOR pin COM pin: Pilot signal input SAP total S/N S/N SAP L-channel SAP1 S/NSAP = 20 log (VOSAP1L ÷ VL) VOSAP1L : Output voltage of FOL pin after LPF (30 kHz) COM pin: SAP signal (300 Hz, 100 % modulation) input V L: Output voltage of FOL pin COM pin: SAP carrier (0 % modulation) input R-channel S/NSAP = 20 log (VOSAP1R ÷ VR ) VOSAP1R : Output voltage of FOR pin after LPF (30 kHz) COM pin: SAP signal (300 Hz, 100 % modulation) input V R : Output voltage of FOR pin COM pin: SAP carrier (0 % modulation) input Total muting level Mute Mute = 20 log (V OMOL ÷ VM ) Monaural VOMOL : Output voltage of LOT pin mute COM pin: Monaural signal (1 kHz, 100 % modulation) input V M : Output voltage of LOT pin Write register 06H, D0: 0 COM pin: Monaural signal (1 kHz, 100 % modulation) input Timing current I T IT : Current that flows from VCC to STI, WTI pins STI, WTI pins : 6 V DC is applied. Inter-mode DC offset 1 V DOF1 VDOF1 = VMONO – VMute Mute VMONO : DC voltage at LOT and ROT pins to User mode : Monaural Monaural NDT pin: 6 V DC is applied. V Mute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 (6/8) Parameter Symbol Test Conditions User Mode Note Inter-mode DC offset 2 V DOF2 VDOF2 = VST – VMute Mute VST : DC voltage at LOT and ROT pins to User mode : Stereo Stereo NDT pin: 6 V DC is applied. V Mute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. Inter-mode DC offset 3 V DOF3 VDOF3 = VSAP – VMute Mute VSAP : DC voltage at LOT and ROT pins to User mode : SAP1 SAP1 NDT pin: 6 V DC is applied. V Mute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. Inter-mode DC offset 4 V DOF4 VDOF4 = VMONO – VMute Mute VMONO : DC voltage at LOT and ROT pins to User mode : External input External NDT pin: 6 V DC is applied. input V Mute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1: 0) NDT pin: 6 V DC is applied. Surround output V SR1L VSR1L = 20 log (VL1 ÷ VEL ) External input 1 characteristics 1 V L1: Output voltage of LOT pin External input 2 VEL : Input voltage of EL1, EL2 pins (100 Hz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) Surround output V SR2L VSR2L : 20 log (VL2 ÷ VEL ) characteristics 2 V L2: Output voltage of LOT pin VEL : Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) Surround output V SR3L VSR3L : 20 log (VL3 ÷ VEL ) characteristics 3 V L3: Output voltage of LOT pin VEL : Input voltage of EL1, EL2 pins (10 kHz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) Surround output V SR4R VSR4R : 20 log (VR ÷ VEL ) characteristics 4 V R : Output voltage of ROT pin VEL : Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms) ER1, ER2 pins: No signal Surround: ON (Subaddress 04H, Bit D6: 1) Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 (7/8) Parameter Symbol Test Conditions Sub- Data User Mode Note address 09H 0AH 07H 08H 08H 07H 3FH 00H 3FH 00H 3FH 20H 00H 3FH 30H 20H 00H 3FH 20H 10H 00H 3FH 20H 10H VBB VBC VTB VTC ATT VL1 ATT VL2 ATT VL3 ATT BL1 ATT BL2 ATT BL3 ATT BL4 ATT BR1 ATT BR2 ATT BR3 ATT BR4 VOLR1 VOLR2 VOLR3 Bass response = 20 log (VOUT ÷ VIN) VIN: Input signal level (sine wave: 100 Hz, 150 mVrms) of external input 1 (EL1, ER1 pins) or external input 2 (EL2, ER2 pins) V OUT : Output signal level of LOT, ROT pins Treble response = 20 log (VOUT ÷ VIN) VIN: Input signal level (sine wave: 10 kHz, 150 mVrms) of external input 1 (EL1, ER1 pins) or external input 2 (EL2, ER2 pins) V OUT : Output signal level of LOT, ROT pins Volume attenuation = 20 log (VOUT ÷ VIN) VIN: Input signal level (sine wave: 1 kHz, 500 mVrms) of external input 1 (EL1, ER1 pins) or external input 2 (EL2, ER2 pins) V OUT : Output signal level of LOT, ROT pins Balance attenuation = 20 log (VOUT ÷ VIN) VIN: Input signal level (sine wave: 1 kHz, 500 mVrms) of external input 1 (EL1 pin) or external input 2 (EL2 pin) VOUT : Output signal level of LOT pin Balance attenuation = 20 log (VOUT ÷ VIN) VIN: Input signal level (sine wave: 1 kHz, 500 mVrms) of external input 1 (ER1 pin) or external input 2 (ER2 pin) VOUT : Output signal level of ROT pin Error between channels = 20 log (VROUT ÷ VRIN) – 20 log (VLOUT ÷ VLIN) External input 1 V ROUT : Output signal level of ROT pin VRIN: Input signal level of ER1 pin (sine wave: 1 kHz, 500 mVrms) VLOUT : Output signal level of LOT pin VLIN: Input signal level of EL1 pin (sine wave: 1 kHz, 500 mVrms) External input 2 V ROUT : Output signal level of ROT pin VRIN: Input signal level of ER2 pin (sine wave: 1 kHz, 500 mVrms) VLOUT : Output signal level of LOT pin VLIN: Input signal level of EL2 pin (sine wave: 1 kHz, 500 mVrms) External input 1, External input 2 External input 1, External input 2 External input 1, External input 2 External input 1, External input 2 External input 1, External input 2 Low frequency band width boost control Low frequency band width cut control High frequency band width boost control High frequency band width cut control Volume attenuation 1 Volume attenuation 2 Volume attenuation 3 Balance attenuation L-ch 1 Balance attenuation L-ch 2 Balance attenuation L-ch 3 Balance attenuation L-ch 4 Balance attenuation R-ch 1 Balance attenuation R-ch 2 Balance attenuation R-ch 3 Balance attenuation R-ch 4 Difference between monaural L and R output voltage 1 (in case of external input) Difference between monaural L and R output voltage 2 (in case of external input) Difference between monaural L and R output voltage 3 (in case of external input) Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 (8/8) Parameter Symbol Test Conditions Sub- Data User Mode Note address External input 1, External input 2, Stereo, SAP, Monaural External input 1, External input 2 External input 1, External input 2 External input 1, External input 2 External input 1, External input 2 07H 07H 07H 07H 07H 3FH 3FH 3FH 3FH 3FH CT 3 = 20 log (VEXT ÷ VTV ) VEXT : Output voltage of LOT or ROT pin when the input select 1 is set to the external input 1 or 2 (the data of bits D6 and D5 of subaddress 06H are “01” or “10”). V TV : Output voltage ROT or LOT pin when the input select 1 is set to the TV signal (the data of bits D6 and D5 of subaddress 06H are “00”). COM pin: Monaural, stereo or SAP signal (1 kHz, 100 % modulation) input External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): No input Measure the values of the external inputs 1 and 2 individually. CT 4 = 20 log (VEXTR ÷ VEXTL ) VEXTR : Output voltage of ROT pin when the input select 1 is set to the external input 1 or 2 (the data of bits D6 and D5 of subaddress 06H are “01” or “10”). V EXTL : Output voltage LOT pin when the input select 1 is set to the external input 1 or 2 (the data of bits D6 and D5 of subaddress 06H are “01” or “10”). EL1, EL2 pins: External input signal (1 kHz, 500 mV rms) input ER1, ER2 pins: No input Measure the values of the external inputs 1 and 2 individually. THD EXT : Total harmonic distortion rate of LOT, ROT pins External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): External input signal (1 kHz, 500 mVrms) input VIEM : Maximum input voltage level External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): External input signal (1 kHz) input when the total harmonic distortion rate of LOT and ROT pins becomes 1 %. NO: Output noise of LOT, ROT pins through DIN/AUDIO External input 1 (EL1, ER1 pins), external input 2 (EL2, ER2 pins): No input (grounded through the resistor (R g = 600 Ω )) CT 3 CT 4 THD EXT VIEM NO Crosstalk 3 TV signal → External input Crosstalk 4 L-ch → R-ch Total harmonic distortion (in case of external input) Maximum input voltage of external input Output noise (in case of external input) Note For details about the User Mode, refer to 5. MODE MATRIX .

µPC1851B Data Sheet S13417EJ2V0DS00 9. TEST CIRCUIT PC connectorSDA(P) SCL(P) IN(P) SDA SCL DV DD (+5 V) DGND Interface block COM L COM EEPROM TM block DV DD (+5 V) DGND SCL SDA K VCC FHM AGND DGND VDD VCC JP 0.1 F PC78M05AHF 0.1 F ER1 EL2EL1 ER2 MOL MOR LOT ROTFORFOL AGND DGND SDA SCL LPRS520-35 (88PJ)FORFOL AB C D E F G H I J PC1851B peripheral block Microcontroller/PC change-over switch Connector for cable Overall surface analog GNDOverall surface digital GND A B C D E F G H I J K L L-channel fixed output R-channel fixed output External L-channel input 1 External R-channel input 1 External L-channel input 2 External R-channel input 2 L-channel Matrix output R-channel Matrix output L-channel output R-channel output f H monitor Composite signal input Test Points DGND DV DD (+5 V) SDA SCL Microcontroller peripheral block µ µ µµ

µPC1851B Data Sheet S13417EJ2V0DS00 µPC1851B Peripheral Block Note Filter: 126XGS-7990Z, TOKO Remark Use the followings for external parts. Resistor (*): Metal film resistor (±1 %). Unless otherwise specified; ±5 % Capacitors (**): Tantalum capacitor (±10 %). Unless otherwise specified, ±20 % V CC VRE PD1 PD2 COM SDT NDT SOT SI SOA STI SRB ITI WTI WRB dO VOL-C VOA AGND MOA FOL FOR EL1 ER1 EL2 ER2 MOL MOR LBC LTC TLO RBC RTC TRO SUR LOT ROT DGND SCL SDA 1 F 2.2 F LOT ROT DGND SCL SDA VCC AGND FHM + 2.2 F 2.2 F 2.2 F 2.2 F 2.2 F 2.2 F 0.1 F 2200 pF 2.2 F 0.1 F 2200 pF 2.2 F 0.022 F 10 F 10 F 2.2 F 22 F 0.1 F 2.2 F 0.047 F 1 F4.7 F 1 kΩ 68 kΩ 0.47 F 0.1 F 0.1 F 3.3 F 3 kΩ 16.6 kΩ 10 F 5.1 kΩ 1 F 4.7 F 1 F 1 F 1 F PC1851B + – 10 kΩ 6.8 kΩ 10 kΩ 91 kΩ 3 kΩ 10 F

10 F30 kΩ

PC842C (1/2) PC842C (1/2) 1 2 3 4 6 Note FOL FOR EL1 ER1 EL2 ER2 MOL MOR µ µ µ µ µ φ φ µ µµ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ 1 MΩ 10 Fµ COM

µPC1851B Data Sheet S13417EJ2V0DS00 10. PACKAGE DRAWINGS NOTES 1. Each lead centerline is located within 0.17 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 39.13 MAX. B 1.78 MAX. C 1.778 (T.P.) D 0.50 ±0.10 F 0.85 MIN. G 3.2 ±0.3 J 5.72 MAX. K 15.24 (T.P.) M 0.25 N 0.17 H 0.51 MIN. I 4.31 MAX. L 13.2 +0.10 −0.05 2. Item "K" to center of leads when formed parallel. P42C-70-600B-2 R0 ∼15° 42 22 12 1 N B I M RM C D F H G A J K L 42-PIN PLASTIC SDIP (15.24mm(600))

µPC1851B Data Sheet S13417EJ2V0DS00 11. RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document ”Semiconductor Device Mounting Technology Manual” (C10535E). µPC1851BCU: 42-pin plastic SDIP (15.24 mm (600)) Process Conditions Wave soldering (only to leads) Solder temperature: 260 °C or below, Flow time: 10 seconds or less Partial heating method Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per each lead) Caution The wave soldering process must be applied only to leads, and the make sure that the package body does not get jet soldered.

µPC1851B EEPROM is a trademark of NEC Corporation. Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specifications as defined by Philips. M8E 00. 4 The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard":Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).