BTN7030-1EPA

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NovalithIC??Lite ??smart integrated half-bridge v1.1 2020-11-20

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Technical content

Features

Low-side and high-side switch in half-bridge configuration with diagnosis and embedded protection
Part of NovalithIC TM family
Switch ON capability while inverse current condition (InverseON)
Green product (RoHS compliant) Protection features
Temperature limitation with intelligent latch
Overcurrent protection (tripping) with intelligent latch for both the low-side and high-side output stage
Undervoltage shutdown
Cross current protection Diagnostic features
Proportional load current sense for high-side load currents
Open load in ON and OFF state
Short circuit to ground or battery Potential applications
Replaces electromechanical relays, fuses and discrete circuits
Suitable for driving motors and solenoids of a max. inductance of 3 mH at maximal current
Temperature dependent overload detection current level with min. 17 A (T J < 75°C), min. 15 A (TJ = 125°C) and min. 14 A (TJ = 150°C)
Current sense diagnosis optimized for motor and solenoid applications VDD GPIO ADC VSS VDD Microcontroller IN EN DEN IS GND OUT VS COUT DZ2 M TREV BTN7030 RA/D RIS_PROT RDEN REN RIN GPIO GPIO CVS VS RSENSEDZ1 CSENSE Figure 1 Potential application Product Type Package Marking BTN7030-1EPA PG-TSDSO-14 BTN7030-1EPA Datasheet Please read the Important Notice and Warnings at the end of this document 1.1 www.infineon.com 2020-11-20

Description

The BTN7030-1EPA is a protected half-bridge with integrated driver, providing protection and diagnosis functions. The device is integrated in SMART7 technology. Table 1 Product Summary Parameter Symbol Values Minimum operating voltage (at switch ON) VS(OP) 3.8 V Minimum operating voltage (cranking) VS(UV) 3.5 V Maximum operating voltage VS 28 V Minimum overvoltage protection (TJ ≥ 25°C) VDS(CLAMP)_25 35 V Maximum current in sleep mode (TJ ≤ 85°C) IVS(SLEEP)_85_stdy 3 µA Maximum operative current IGND(ACTIVE) 5 mA Maximum ON-state resistance (TJ = 150°C) high-side RDS(ON)_150(HS) 25.5 mΩ Maximum ON-state resistance (TJ = 150°C) low-side RDS(ON)_150(LS) 36.5 mΩ Min. overload detection current at TJ < 75°C IL(OVL0)_-40(HS) 17 A Min. overload detection current at TJ = 125°C IL(OVL0)_125(HS) 15 A Min. overload detection current at TJ = 150°C IL(OVL0)_150(HS) 14 A Typical current sense ratio at IL = IL(NOM) kILIS 4300 Nominal load current IL(NOM) 7 A Product validation Qualified for automotive applications. Product validation according to AEC-Q100. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Datasheet 2 1.1 2020-11-20

NovalithIC™ Lite – smart integrated half-bridge Table of contents Datasheet 3 1.1 2020-11-20

NovalithIC™ Lite – smart integrated half-bridge Table of contents Datasheet 4 1.1 2020-11-20

1 Block diagram and terms

T LS Gate Control LS Over Temperature Over Voltage Clamping LS Over Current Protection T driver logic HS Gate Control Chargepump Load Current Sense HS Over Temperature Output Voltage Limitation Voltage Sensor GND Over Voltage Clamping HS Over Current Protection OUT VS Figure 2 Block Diagram of BTN7030-1EPA

1.1 Terms

Figure 3 shows all terms used in this data sheet, with associated convention for positive values. IIN IEN VS IL IS VS OUT VIN VEN VIS VOUT, VDS(LS) VDS(HS) IVS GND IGND IN EN DEN VDEN IDEN VSIS IIS Figure 3 Voltage and current convention BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Block diagram and terms Datasheet 5 1.1 2020-11-20

2 Pin configuration

n.c. GND EN DEN IS n.c. GND GND n.c. exposed pad (bottom) IN n.c. OUT OUT OUT Figure 4 Pin configuration

2.1 Pin definitions and functions

EP VS (exposed pad) Supply Voltage Battery voltage

2 EN Enable

Digital signal to enable the normal operational mode (active mode) of the BTN7030-1EPA and to clear the protection latch

3 DEN Diagnostic Enable

Digital signal to enable device diagnosis ("high" active) and to clear the protection latch If not used: connect to GND pin or to module ground with a 10 kΩ resistor

4 IS SENSE current output

Analog/digital signal for diagnosis If not used: left open

6 IN Input

Digital signal to switch ON either the low-side or high-side output stage of the half-bridge 8-10 OUT Output Protected half-bridge power output 1) 12-14 GND Ground Signal ground and ground connection for the low-side switch 1) 1, 5, 7, 11 n.c. Not connected, internally not bonded 1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Pin configuration Datasheet 6 1.1 2020-11-20

3 Absolute maximum ratings

3.1 Absolute maximum ratings

Table 3 Absolute maximum ratings TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified); all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Supply pins Power supply voltage VS -0.3 – 28 V – PRQ-6 Load dump voltage VBAT(LD) – – 35 V Suppressed Load Dump acc. to ISO16750-2 (2010). Ri= 2 Ω PRQ-8 Supply voltage for short circuit protection VBAT(SC) 0 – 24 V Setup acc. to AEC- Q100-012 PRQ-9 Current through DI pin IDI -1 – 2 mA (1) PRQ-25 IS pin Voltage at IS pin VIS -1.5 – VS V IIS= 10 μA PRQ-26 Current through IS pin IIS -25 – IIS(FAUL T),MAX mA – PRQ-28 Temperatures Junction temperature TJ -40 – 150 °C – PRQ-29 Storage temperature TSTG -55 – 150 °C – PRQ-30 ESD Susceptibility ESD susceptibility all pins (HBM) VESD(HBM) -2 – 2 kV HBM (2) PRQ-31 ESD susceptibility OUT vs GND and VS connected (HBM) VESD(HBM)_OUT -4 – 4 kV HBM (2) PRQ-32 ESD susceptibility all pins (CDM) VESD(CDM) -500 – 500 V CDM (3) PRQ-34 ESD susceptibility corner pins (CDM) VESD(CDM)_CRN -750 – 750 V pins 1, 7, 8, 14 CDM (3) PRQ-35 Power stages - 12 mΩ high-side Load current, high-side switch |IL|(HS) – – IL(OVL), MAX A – PRQ-39 Power stages - 20 mΩ low-side BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Absolute maximum ratings Datasheet 7 1.1 2020-11-20

Table 3 Absolute maximum ratings (continued) TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified); all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Load current, low-side switch |IL|(LS) – – IL(OVL), MAX A – PRQ-42 (1) Maximum VDI to be considered for latch-up tests: 5.5 V (2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) (3) ESD susceptibility, Charged Device Model "CDM" according JEDEC JESD22-C101

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

3.2 Functional range

Not subject to production test - specified by design. Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Supply voltage range for normal operation VS(NOR) 6 13.5 18 V – PRQ-43 Lower extended supply voltage range for operation VS(EXT ,LOW) 3.5 – 6 V (1) (2) parameter deviations possible PRQ-44 Upper extended supply voltage range for operation VS(EXT ,UP) 18 – 28 V (1) parameter deviations possible PRQ-45 (1) Protection functions still operative (2) In case of VS voltage decreasing: VS(EXT ,LOW),MIN = 3.5 V. In case of VS voltage increasing: VS(EXT ,LOW),MIN = 3.8 V Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table.

3.3 Thermal resistance

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Absolute maximum ratings Datasheet 8 1.1 2020-11-20

Table 5 Thermal resistance Not subject to production test - specified by design. Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Thermal resistance junction- to-case, high-side switch RthJC(HS) – 2.7 4.3 K/W (1) PRQ-48 Thermal resistance junction- to-case, low-side switch RthJC(LS) – 0.95 1.5 K/W (1) PRQ-540 Thermal resistance junction to ambient, high-side switch RthJA(HS) – 36 – K/W (1) PRQ-49 Thermal resistance junction to ambient, low-side switch RthJA(LS) – 32.5 – K/W (1) PRQ-529 (1) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with two inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TAMB = 105°C and Pdissipation = 1 W. Figure 5 Typical thermal impedance for T ambient = 85°C; Simulation with 1 W of power dissipation BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Absolute maximum ratings Datasheet 9 1.1 2020-11-20

4 Logic pins

The device has 3 digital pins for direct control of the device. The logic thresholds for "low" and "high" states are defined by parameters VDI(TH) and VDI(HYS). The relationship between these two values is shown in Figure 6. The voltage VIN needed to ensure an "high" state is always higher than the voltage needed to ensure a "low" state. The digital input pins are compatible with 3.3 V and 5 V micro-controllers. V DI(TH),MAX V DI(HYS) t V DI V DI(TH),MIN Internal channel activation signal t 0 x 1 x 0 V DI(TH) Figure 6 Input Threshold voltages and hysteresis

4.1 Input pin (IN)

The input pin IN activates either the low-side or the high-side output stage, in case the enable pin EN is set to "high" and no fault is present.

4.2 Enable pin (EN)

The Enable (EN) pin activates the device. When EN pin is set to "high" , the device is in Active mode. When it is set to "low" , the device goes into Sleep mode, with the output stage set to tri-state (low-side and high-side switches are set OFF). The protection latch is cleared by a "low" signal with a minimum length of tDELAY(LR) at the EN pin.

4.3 Diagnosis Enable pin (DEN)

The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is set to "high" , the diagnosis is enabled (see Chapter 8.2 for more details). When it is set to "low" , the diagnosis is disabled (IS pin is set to high impedance). The transition from "high" to "low" of DEN pin clears the protection latch of the channel depending on the logic state of EN pin and DEN pulse length (see Chapter 7.3 for more details). BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Logic pins Datasheet 10 1.1 2020-11-20

4.4 Electrical characteristics logic pins

Table 6 Electrical characteristics logic pins VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C; Digital Input (DI) pins = IN, DEN, EN; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Digital input voltage threshold VDI(TH) 0.8 1.3 2 V See Figure 6 PRQ-52 Digital input clamping voltage VDI(CLAMP1) – 7 – V (1) IDI = 1 mA PRQ-53 Digital input clamping voltage VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA PRQ-54 Digital input hysteresis VDI(HYS) – 0.25 – V (1) See Figure 6 PRQ-56 Digital input current ("high") IDI(H) 2 10 25 µA VDI = 2 V PRQ-57 Digital input current ("low") IDI(L) 2 10 25 µA VDI = 0.8 V PRQ-58 (1) Not subject to production test - specified by design BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Logic pins Datasheet 11 1.1 2020-11-20

5 Power supply

The BTN7030-1EPA is supplied by VS, which is used for the internal logic as well as supply for the power output stage. VS has an undervoltage detection circuit, which prevents the activation of the power output stage and diagnosis in case the applied voltage is below the undervoltage threshold.

5.1 Operation modes

BTN7030-1EPA has three operation modes, with the transition between the operation modes is determined according to these variables:

logic level at EN pin
logic level at DEN pin The state diagram including the operation modes and the possible transitions is shown in Figure 7. The behavior of BTN7030-1EPA as well as some parameters may change in dependence from the operation mode of the device. Furthermore, due to the undervoltage detection circuitry which monitors VS supply voltage, some changes within the same operation mode can be seen accordingly. In case of a fault, the BTN7030-1EPA will not go into sleep mode, unitl the latch is cleared. Sleep Active EN = „high“ EN = „low“ & DEN = „high“ Stand-by EN = „low“ & DEN = „low“ Power-up EN = „low“ & DEN = „high“ EN = „low“ & DEN = „low“ V S > V S(OP) Unsupplied EN = „high“ DEN = „high“ DEN = „low“ Figure 7 Operation mode state diagram

5.1.1 Unsupplied

In this state, the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the undervoltage threshold.

5.1.2 Power-up

The Power-up condition is entered when the supply voltage (VS) is applied to the device. The supply is rising until it is above the undervoltage threshold VS(OP) therefore the internal power-on signals are set.

5.1.3 Sleep mode

The device is in Sleep mode when all Digital Input pins (IN, DEN, EN) are set to "low" . When BTN7030-1EPA is in Sleep mode, both high-side and low-side power stages are OFF. The current consumption is minimum (see BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power supply Datasheet 12 1.1 2020-11-20

parameter IVS(SLEEP)_85_stdy). No Overtemperature or Overload protection mechanism is active when the device is in Sleep mode, only the InverseON protection for the low-side power output stage is active (see Chapter 6.3.1 for further details). In case of activation, the current consumption of the device is increased. The device can go in Sleep mode only if the protection is not active (latch = 0, see Chapter 7.3.1 for further details).

5.1.4 Stand-by mode

The device is in Stand-by mode as long as DEN pin is set to "high" while the EN pin is set to "low" . Both the high-side and low-side power stages are OFF, therefore only Open Load in OFF diagnosis is possible. Depending on the load condition, either a fault current IIS(FAUL T) or an Open Load in OFF current IIS(OLOFF) may be present at IS pin. In such a situation, the current consumption of the device is increased.

5.2 Undervoltage on VS

Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active mode) and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the output channel. As soon as the supply voltage VS is above the operative threshold VS(OP), the channel is switched ON again with a hysteresis of VS(HYS).

5.3 Electrical characteristics power supply

Table 7 Electrical characteristics power supply VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Power supply undervoltage shutdown VS(UV) 1.8 2.7 3.5 V VS decreasing EN = "high" From VDS ≤ 0.5 V to VDS = VS PRQ-63 Power supply minimum operating voltage VS(OP) 2.0 3.0 3.8 V VS increasing EN = "high" From VDS = VS to VDS ≤ 0.5 V PRQ-65 Power supply undervoltage shutdown hysteresis VS(HYS) – 0.3 – V (1) VS(OP) - VS(UV) PRQ-67 Power supply current consumption in sleep mode with loads at T J ≤ 85°C after settling time IVS(SLEEP)_85_stdy - 0.01 3 µA (1) VS = 18 V EN = IN = DEN = “low” OUT = “floating” steady state TJ ≤ 85 °C PRQ-70 BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power supply Datasheet 13 1.1 2020-11-20

Table 7 Electrical characteristics power supply (continued) VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Power supply current consumption in sleep mode with loads at T J = 150°C after settling time IVS(SLEEP)_150_stdy - 8 20 µA (1) VS = 18 V EN = IN = DEN = “low” OUT = “floating” steady state TJ = 150°C PRQ-72 Operating current in active mode (GND) IGND(ACTIVE) – 2 5 mA VS =18 V EN = IN = DEN = "high" PRQ-73 Operating current in active mode (VS) IVS(ACTIVE) – 2 5 mA VS =18 V IN = "low" EN = DEN = "high" fault-latch ≠ 0 PRQ-74 Operating current in stand- by mode/OLOFF IGND(STBY) – 1.2 1.8 mA VS = 18 V EN = IN = "low" DEN = "high" PRQ-76 Operating current during low-side inverseON activation IVS(INVON)(LS) – – 5 mA VS = 6 V IL = -200 mA EN = IN = "low" PRQ-77 (1) Not subject to production test - specified by design BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power supply Datasheet 14 1.1 2020-11-20

6 Power stages

The high-side power stage is built using a N-channel vertical Power MOSFET with charge pump, while the low-side power stage uses no charge pump.

6.1 Output ON-state resistance

The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 8 shows the variation of RDS(ON) across the whole TJ range. The value "2" on the y-axis corresponds to the maximum RDS(ON) measured at TJ = 150°C. 0,25 0,5 0,75 1,25 1,5 1,75 -40 0 40 80 120160 high- side RDS(ON)(HS)(mΩ) high- side RDS(ON)variation factor("1" = RDS(ON),typ@ 25°C) junction Temperature (° C) t y p . High-Side Switch 0,25 0,5 0,75 1,25 1,5 1,75 -40 0 40 80 120160 low- side RDS(ON)(LS)(mΩ) low- side RDS(ON)variation factor("1" = RDS(ON),typ@ 25°C) junction Temperature (° C) t y p . Low-Side Switch Figure 8 Typical R DS(ON) vs. junction temperature for low-side and high-side output stage

6.2 Switching loads

6.2.1 Switching times

When switching resistive loads, the switching times and slew rates shown in Figure 9 and Figure 10 can be considered. The switch energy values EON(xS) and EOFF(xS) are proportional to the load resistance and times tON(xS) and tOFF(xS). BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 15 1.1 2020-11-20

t VOUT VIN(TH) (dV/dt)ON(HS) VIN(HYS) PDMOS(HS) t t EON(HS) EOFF(HS) tON(HS) tDON(HS) tDOFF(HS) (dV/dt)OFF(HS) tOFF(HS) 10% of VS 90% of VS 70% of VS 30% of VS 30% of VS 70% of VS Figure 9 Switching a resistive load to ground (high-side), for EN="high" IN t VOUT VIN(TH) (dV/dt)ON(LS) VIN(HYS) PDMOS(LS) t t EON(LS) EOFF(LS) tON(LS) tDON(LS) tDOFF(LS) (dV/dt)OFF(LS) tOFF(LS) 10% of VS 90% of VS 70% of VS 30% of VS 30% of VS 70% of VS Figure 10 Switching a resistive load to supply voltage (low-side), for EN="high"

6.2.2 Output voltage limitation

To increase the current sense accuracy of the high-side output stage, VDS voltage is monitored. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 16 1.1 2020-11-20

When the output current IL decreases while the channel is diagnosed (DEN pin set to "high" - see Figure 11) bringing VDS equal or lower than VDS(SLC)(HS), the output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC)(HS) even for very small output currents. EN IN I L t t t DEN t sIS(ON) t sIS(OFF) t V DS V DS(SLC)(HS) V S Figure 11 Output voltage limitation activation during diagnosis, with EN="high" The VDS increase allows the current sensing circuitry to work more efficiently, providing better kILIS accuracy for output current in the low range.

6.3 Advanced switching characteristics

6.3.1 Inverse current behavior for the high-side switch

When VOUT > VS, a current IINV flows into the high-side power output transistor (see Figure 12). Similar for VOUT < GND (0 V), a current IINV flows into the low-side power output transistor. This condition is known as "Inverse Current" . If the channel is in OFF- state, the current flows through the intrinsic body diode generating high power losses therefore an increase of overall device temperature. If the channel is in ON- state, RDS(INV) can be expected and power dissipation in the output stage is comparable to normal operation in RDS(ON). With InverseON, it is possible to switch ON or OFF the high-side power output channel during inverse current condition. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 17 1.1 2020-11-20

VOUT, VDS(LS) I L VDS(CLAMP)_HS VS OUT VDS(HS) GND VSIS(CLAMP) RSENSE VDS(CLAMP)_LS IS L, RL Figure 12 Inverse current circuitry for low-side and high-side

6.3.2 Inverse current behavior for the low-side switch

With InverseON, the low-side power output channel is activated under all operational conditions for VOUT < VINV(LS), also in case of any fault to protect the low-side power output transistor. The circuitry is active in any operational condition, fault condition, stand-by or sleep mode. The power supply consumption for voltage monitoring, without activation of the power output stage, is included in Table 7. In case of activation of the low-side power output stage, when switched on by the protection circuitry, an operating supply current of IVS(INVON)(LS) is required during activation. When VOUT is small again, the low-side output-stage is switched according to the EN and IN pin. Note: No protection mechanism like Overtemperature or Overload protection is active during applied Inverse Currents for both low-side and high-side output transistor.

6.4 Electrical characteristics power stages

Table 8 Electrical characteristics power stages switching TJ = -40°C to +150°C; Rload = 3.3 Ω, single pulse, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. High-side switch timings Switch-ON delay, high-side switch tDON(HS) 30 60 110 μs VS =13.5 V VOUT = 10% VS See Figure 9 PRQ-146 Switch-OFF delay, high-side switch tDOFF(HS) 10 33 60 μs VS =13.5 V VOUT = 90% VS See Figure 9 PRQ-147 Switch-ON time, high-side switch tON(HS) 45 85 135 μs VS =13.5 V VOUT = 90% VS See Figure 9 PRQ-148 BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 18 1.1 2020-11-20

Table 8 Electrical characteristics power stages switching (continued) TJ = -40°C to +150°C; Rload = 3.3 Ω, single pulse, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Switch-OFF time, high-side switch tOFF(HS) 25 55 82 μs VS = 13.5 V VOUT = 10% VS See Figure 9 PRQ-149 Switch-ON/OFF matching tON-tOFF, high-side switch ΔtSW(HS) 0 35 70 μs VS = 13.5 V See Figure 9 PRQ-150 Blank time between switches activation HS to LS (to avoid cross-current) tBLANK(HS-LS) – 20 – μs VS = 13.5 V PRQ-528 Low-side switch timings Switch-ON delay, low-side switch tDON(LS) 50 90 130 μs VS = 13.5 V VOUT = 90% VS See Figure 10 PRQ-151 Switch-OFF delay, low-side switch tDOFF(LS) 10 33 60 μs VS = 13.5 V VOUT = 10% VS See Figure 10 PRQ-152 Switch-ON time, low-side switch tON(LS) 70 115 160 μs VS = 13.5 V VOUT = 10% VS See Figure 10 PRQ-153 Switch-OFF time, low-side switch tOFF(LS) 25 55 85 μs VS = 13.5 V VOUT = 90% VS See Figure 10 PRQ-154 Switch-ON/OFF matching tON-tOFF, low-side switch ΔtSW(LS) 25 60 95 μs VS = 13.5 V See Figure 10 PRQ-155 Blank time between switches activation LS to HS (to avoid cross-current) tBLANK(LS-HS) – 40 – μs VS = 13.5 V PRQ-156 High-side switch voltage slope Switch-ON slew rate, high- side switch (dV/dt)ON(HS) 0.35 0.6 0.9 V/μs VS = 13.5 V VOUT = 30% to 70% of VS PRQ-157 Switch-OFF slew rate, high- side switch -(dV/dt)OFF(HS) 0.35 0.6 0.9 V/μs VS = 13.5 V VOUT = 70% to 30% of VS PRQ-158 Low-side switch voltage slope Switch-ON slew rate, low- side switch -(dV/dt)ON(LS) 0.35 0.6 0.9 V/μs VS =13.5 V VOUT = 70% to 30% of VS PRQ-160 Switch-OFF slew rate, low- side switch (dV/dt)OFF(LS) 0.35 0.6 0.9 V/μs VS = 13.5 V VOUT = 30% to 70% of VS PRQ-161 High-side voltages BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 19 1.1 2020-11-20

Table 8 Electrical characteristics power stages switching (continued) TJ = -40°C to +150°C; Rload = 3.3 Ω, single pulse, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Output voltage drop limitation at small load currents VDS(SLC)(HS) 2 7 18 mV IOUT = IOUT(OL) = 20 mA IN=DEN=EN="high" PRQ-163 Table 9 Electrical characteristics - power output stages VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. 12 mΩ high-side Output characteristics ON-state resistance at T J = 25°C, high-side switch RDS(ON)_25(HS) – 12 – mΩ (1) TJ = 25 °C PRQ-164 ON-state resistance at T J = 150°C, high-side switch RDS(ON)_150(HS) – – 25.5 mΩ TJ = 150°C PRQ-165 ON-state resistance in inverse current at T J = 150°C, high-side switch RDS(INV)_150(HS) – – 26 mΩ TJ = 150°C VS = 13.5 V IL = -4 A See Figure 12 PRQ-168 Output leakage current at T J ≤ 85°C, high-side switch IL(OFF)_85(HS) – 0.01 1 μA (1) VOUT = 0 V EN = "low" TA ≤ 85°C PRQ-169 Output leakage current at T J = 150°C, high-side switch IL(OFF)_150(HS) – 16 43 μA VOUT = 0 V EN = "low" TA = 150°C PRQ-170 Voltages Drain source diode voltage at -40°C, high-side switch |VDS(DIODE)_-40(HS)| – 800 – mV (1) IL = -190 mA TJ = -40°C PRQ-536 Drain source diode voltage at 25°C, high-side switch |VDS(DIODE)_25(HS)| – 700 – mV (1) IL = -190 mA TJ = 25°C PRQ-537 Drain source diode voltage at 150°C, high-side switch |VDS(DIODE)_150(HS)| – 500 650 mV IL = -190 mA TJ = 150°C PRQ-172 Switching energy BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 20 1.1 2020-11-20

Table 9 Electrical characteristics - power output stages (continued) VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Switch-ON energy, high- side switch EON(HS) – 0.44 – mJ (1) VS = 18 V See Figure 9 PRQ-173 Switch-OFF energy, high- side switch EOFF(HS) – 0.49 – mJ (1) VS = 18 V See Figure 9 PRQ-174 20 mΩ low-side Output characteristics ON-state resistance at T J = 25°C, low-side switch RDS(ON)_25(LS) – 20 – mΩ (1) TJ = 25°C PRQ-175 ON-state resistance at T J = 150°C, low-side switch RDS(ON)_150(LS) – – 36.5 mΩ TJ = 150°C PRQ-176 ON-state resistance in inverse current at T J = 150°C, low-side switch RDS(INV)_150(LS) – – 40 mΩ TJ = 150°C VS = 13.5 V IL = -4 A See Figure 12 PRQ-179 Output leakage current at T J ≤ 85°C, low-side switch IL(OFF)_85(LS) – 0.05 5 μA (1) VOUT = VS EN = "low" TA ≤ 85°C PRQ-190 Output leakage current at T J = 150°C, low-side switch IL(OFF)_150(LS) – 2 117 μA VOUT = VS EN = "low" TA = 150°C PRQ-181 Voltages Drain source diode voltage at -40°C, low-side switch |VDS(DIODE)_-40(LS)| – 600 – mV (1) IL = -190 mA TJ = -40°C PRQ-539 Drain source diode voltage at 25°C, low-side switch |VDS(DIODE)_25(LS)| – 700 – mV (1) IL = -190 mA TJ = 25°C PRQ-538 Drain source diode voltage at 150°C, low-side switch |VDS(DIODE)_150(LS)| – 500 650 mV IL = -500 mA TJ = 150 °C PRQ-183 Voltage threshold for first inverse current low-side activation, low-side switch VINV(LS) – -300 – mV (1) EN = IN = DEN = “low” VS = 6 V IL = -200 mA PRQ-184 Switching energy BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Power stages Datasheet 21 1.1 2020-11-20

7 Protection

The BTN7030-1EPA is protected against overtemperature, overload and overvoltage. Overtemperature and overload protections are working when the device is not in sleep mode. Overvoltage protection works in all operation modes.

7.1 Overtemperature protection

An increase of the junction temperature TJ above the thresholds TJ(SD) switches OFF both the high-side and low-side output stages to prevent destruction. The channel remains switched OFF until the temperature has reached the "Restart" condition described in Table 10. The behavior is shown in Figure 13. From protection point of view, pins IN and EN are equivalent. IL(OVL0)(HS) IL t T J IIS DEN Internal latch T J(SD) t t t t EN IN t IL(NOM) IIS = I L / k ILIS IIS(FAUL T) Figure 13 Overtemperature protection, with EN = "high" and load to GND When the overtemperature protection circuitry allows the channel to be switched ON again, the Intelligent latch strategy described in Chapter 7.3.1 is followed. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Protection Datasheet 23 1.1 2020-11-20

7.2 Overload protection

The BTN7030-1EPA is protected in case of overload, short circuit to battery (low-side output stage) or short circuit to ground (high-side output stage). For the high-side output stage, two overload thresholds are defined (see Figure 14) and selected automatically depending on the voltage VDS across the power DMOS: Overload current thresholds variation with VDS for the high-side output stage

IL(OVL0) when VDS < 13 V
IL(OVL1) when VDS > 22 V Figure 14 Typical Overload current thresholds variation with VDS for the high-side output stage In order to allow a higher load inrush at low ambient temperature, the overload threshold for the high-side output stage is maximum at low temperature and decreases when TJ increases (see Figure 15). For the high-side output stage, IL(OVL0) typical value remains constant up to a junction temperature of +75°C. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Protection Datasheet 24 1.1 2020-11-20

When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1), in either the low-side or high-side output stages) the output stage is switched OFF (both low-side and high-side). The output stage is allowed to be reactivated according to the strategy described in Chapter 7.3.

7.3 Protection and diagnosis in case of fault

Any event that triggers a protection mechanism (either Overtemperature or Overload) has consequences:

the output stage switches OFF and the internal latch is set to "1"
if the diagnosis is active for the channel, a current IIS(FAUL T) is provided by IS pin (see Chapter 8.2.2 for further details) If all the "restart" conditions described in Table 10 are fullfilled, the latch can be reset, thus the output stage can be switched ON again. Furthermore, the device has the intelligent latch to protect itself against unwanted repetitive restart in fault condition. Table 10 Protection “restart” condition Fault condition Switch OFF event "Restart" Condition Overtemperature TJ ≥ TJ(SD) TJ < TJ(SD) – TJ(HYS) Overload IL ≥ IL(OVL) IL < 50 mA

7.3.1 Intelligent latch strategy (INTLAT)

When EN is set to "high" , the channel is switched ON. In case of fault condition the output stage latches OFF. There are two ways to de-latch the switch. With EN pin: It is necessary to set the pin to "low" for a time longer than tDELAY(LR) ("latch reset delay" time) to de-latch the channel. This is independent from the state of the IN pin. The channel can be allowed to restart only if the "restart" conditions for the protection mechanisms are fulfilled (see Table 10). During the "latch reset delay" time, if the pin is set to "high" the channel remains switched OFF and the timer tDELAY(LR) is reset and it is not started as long as the pin remains at "high" . It restarts as soon as the pin is set to "low" again. The intelligent latch strategy is shown in Figure 17. With DEN pin: It is possible to "force" a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge followed by a falling edge) to the DEN pin while EN pin is "low" . The pulse applied to DEN pin must have a duration longer than tDEN(LR) to ensure a reset of the internal latch. The timing is shown in Figure 18. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Protection Datasheet 26 1.1 2020-11-20

7.4 Additional protections

7.4.1 Overvoltage protection

The clamping structure limits the negative / positive output voltage so that VDS(xS) = VDS(CLAMP), for both the high-side and low-side output stage. The clamping structure protects the device in all operative modes listed in Chapter Chapter 6.1. In the case of supply voltages between VS(EXT ,UP) and VBAT(LD), the output transistor is still operational and follows the input pin. In addition, there is a clamp mechanism available for Overvoltage protection for the logic and the output channel, monitoring the voltage between VS and GND pins (VS(CLAMP)). BTN7xxx V S V OUT , V DS(LS) I L V DS(CLAMP)_HS VS OUT V DS(HS) GND V SIS(CLAMP) R SENSE V DS(CLAMP)_LS IS L , R L Figure 19 Output clamp concept

7.4.2 Cross current protection

In half-bridge applications it has to be assured that the high-side and low-side power output stages are not conducting at the same time, connecting directly the battery voltage to GND. This is assured by a circuit in the driver logic, generating a so called dead time between switching off one power output stages and switching on the other. This is ensured by monitoring the state of the MOSFETs.

7.5 Electrical characteristics protection

NovalithIC™ Lite – smart integrated half-bridge Protection Datasheet 28 1.1 2020-11-20

Table 11 Electrical characteristics protection VS = 6 V to 18 V, TJ = -40°C to +150°C; typical values: VS= 13.5 V, TJ = 25 °C; typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Thermal shutdown temperature TJ(SD) 150 175 200 °C (1) (2) See Figure 13 PRQ-191 Thermal shutdown hysteresis TJ(HYS) – 30 – K (3) See Figure 13 PRQ-193 Drain to source clamping voltage at T J = -40°C for HS and LS switches VDS(CLAMP)_-40 33 36.5 42 V IL = |5 mA| TJ = -40°C See Figure 19 PRQ-144 Drain to source clamping voltage at T J ≥ 25 °C for HS and LS switches VDS(CLAMP)_25 35 38 44 V (2) IL = |5 mA| TJ ≥ 25°C See Figure 19 PRQ-145 Power supply clamping voltage at T J = -40°C VS(CLAMP)_-40 33 36.5 42 V IVS = 5 mA TJ = -40°C See Figure 19 PRQ-197 Power supply clamping voltage at T J ≥ 25°C VS(CLAMP)_25 35 38 44 V (2) IVS = 5 mA TJ ≥ 25 °C See Figure 19 PRQ-198 Power supply voltage threshold for overcurrent threshold reduction in case of short circuit Setup acc. to AEC- Q100-012 PRQ-199 Protection timings Latch reset delay time after fault condition tDELAY(LR) 40 70 100 ms (1) PRQ-200 Minimum DEN Pulse duration for latch reset tDEN(LR) 50 100 150 µs (3) PRQ-201 Protection power output stage - 12 mΩ high-side Overload detection current at T J = -40°C, high-side switch IL(OVL0)_-40(HS) 17 21 25 A (1) TJ = -40°C dI/dt = 0.05 A/µs See Figure 15 PRQ-202 BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Protection Datasheet 29 1.1 2020-11-20

Table 11 Electrical characteristics protection (continued) VS = 6 V to 18 V, TJ = -40°C to +150°C; typical values: VS= 13.5 V, TJ = 25 °C; typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Overload detection current at T J= 25°C, high-side switch IL(OVL0)_25(HS) 17 21 25 A (1) TJ = 25°C dI/dt = 0.05 A/µs See Figure 15 PRQ-203 Overload detection current at T J= 125°C, high-side switch IL(OVL0)_125(HS) 15 – – A (3) TJ = 125°C dI/dt = 0.05 A/µs See Figure 15 PRQ-535 Overload detection current at T J = 150°C, high-side switch IL(OVL0)_150(HS) 14 16.5 19 A (3) TJ = 150°C dI/dt = 0.05 A/µs See Figure 15 PRQ-204 Overload detection current at high VDS, high-side switch IL(OVL1)(HS) – 15 – A (3) dI/dt= 0.05 A/µs TJ = 25°C See Figure 15 PRQ-205 Overload detection current - jump start condition, high- side switch IL(OVL_JS)(HS) – 15 – A (3) VS > VS(JS) dI/dt = 0.05 A/µs TJ = 25°C See Figure 16 PRQ-206 Protection power output stage - 20 mΩ low-side Overload detection current, low-side switch IL(OVL0)(LS) 16 21 28 A (1) dI/dt = 0.05 A/µs See Figure 15 PRQ-207 (1) Functional test only (2) Tested at TJ = 150°C only (3) Not subject to production test - specified by design BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Protection Datasheet 30 1.1 2020-11-20

8 Diagnosis

For diagnosis purpose, the BTN7030-1EPA provides a combination of digital and analog signals at pin IS. These signals are generically named SENSE and written IIS. In case of disabled diagnostic, IS pin becomes high impedance. A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is used. A typical value is RSENSE = 1.2 kΩ. Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS pin to the sense current output of other devices, if they are supplied by a different battery feed.

8.1 Overview

Table 12 gives a quick reference for the state of the IS pin during BTN7030-1EPA operation. Table 12 SENSE signal, function of application condition Application Condition Inputs Outputs Diagnostic Output (IS)EN IN DEN HSS LSS OUT (VOUT) Stand-by operation 0 X 1 OFF OFF _ 3) Z IIS(FAUL T) if latch ≠ 0 Open Load OFF OFF < VS - VDS(OLOFF) > VS - VDS(OLOFF) Z IIS(OLOFF) IIS(FAUL T) if latch ≠ 0 Inverse current on LSS OFF ON ~ VINV = VOUT < VINV(LS) Z IIS(FAUL T) if latch ≠ 0 Inverse current on HSS OFF OFF ~ VINV = VOUT > VS IIS(OLOFF) IIS(FAUL T) if latch ≠ 0 Normal operation 1 0 OFF ON ~ GND Z (= IIS(OFF))

1 ON OFF ~ VS IIS = IL / kILIS (> IIS(EN))

Overcurrent at HS or LS X OFF OFF _ 3) IIS(FAUL T) Short circuit to GND X OFF OFF ~ GND IIS(FAUL T) Short circuit to VS 0 OFF OFF ~ VS IIS(FAUL T) 1 ~ VS Z ~ GND IIS(FAUL T) Open Load 1 ON OFF ~ VS1) IIS(EN) Under load at HS (e.g. output voltage limitation condition)

1 ON OFF ~ VS2) IIS(EN) < IIS < IL(NOM) /

Overtemperature at HS or LS X OFF OFF Z IIS(FAUL T) Inverse current on HSS 1 ON OFF VOUT > VS IIS(EN) Inverse current on LSS X X X OFF ON ~ VINV = VOUT < VINV(LS) Undervoltage at VS X X X OFF OFF _ 3) Z Sleep Mode 0 0 0 OFF OFF Z Z All conditions X X 0 _ 3) Z BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 31 1.1 2020-11-20

Table 13 Signal value explanation Inputs (EN, IN, DEN) Switches (LSS, HSS) Diagnostic Output (IS) 0 = Logic "low" OFF = switched off Z = high Impedance 1 = Logic "high" ON = switched on X = "low" or "high" Sleep EN IN HSS LSS IS

0 X OFF OFF Z

V S < V UV(OFF) (decreasing) Power-up V S > V S(OP) Unsupplied IVS > I L(OVLx)(HS) EN = 1 V S > V S(OP) (increasing) T j < T J(SD) - T J(HYS) & reset fault DEN = 1 EN = 0 DEN = EN = 0 for t = t standby EN = 1 All states DEN = EN = 0 for t ≥ t standby V S < V S(UV) (decreasing) All states (except sleep) T J > T J(SD) T J > T J(SD) Normal operation EN IN HSS LSS IS 1 0 OFF ON Z 1 1 ON OFF CS IL < 50 mA & reset fault IL < 50 mA & reset fault IGND > I L(OVLx)(LS) Stand-by (OLOFF) EN IN HSS LSS IS

0 X OFF OFF IIS(OLOFF)

< V S - V DS(OLOFF) > V S - V DS(OLOFF) Overload LS EN IN HSS LSS IS 1 0 OFF OFF IIS(fault) 1 1 OFF OFF Z V OUT V S 1 1 OFF OFF IIS(fault) ~ GND

0 X OFF OFF IIS(fault)

X X OFF OFF IIS(fault) Overtemperature EN IN HSS LSS IS X X OFF OFF IIS(fault) All states All states (incl. Sleep) Low-side freewheeling EN IN HSS LSS V OUT X X OFF ON < ~0V Prev. states V OUT < ~0 V V OUT ≥ ~0 V Figure 20 Simplified State Diagram for DEN = "high" (unless otherwise specified)

Grey arrow: Transition caused by change of environmental conditions.
Black arrow: Possible transition by digital input pins (EN, DEN or IN pin).

8.2 Diagnosis in ON state

A current proportional to the load current through the high-side output stage (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions are fulfilled:

the power output stage is switched ON with VDS < 2 V
the diagnosis is enabled
no fault (as described in Chapter 7.3) is present or was present and not cleared yet (see Chapter 8.2.2 for further details) BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 32 1.1 2020-11-20

If a "hard" failure mode is present or was present and not cleared yet a current IIS(FAUL T) is provided at IS pin.

8.2.1 Current sense ( kILIS)

The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL output current through the high-side switch until IL reaches the overload detection current IL(OVLx). In case of open load at the output stage (IL close to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in Figure 21. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical product. An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple and oscillations (a minimum time constant of 1 µs for the RC filter is recommended). The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and manufacturing process. Tighter limits are possible (within a defined current window) with calibration:

a well-defined and precise current (IL(CAL)) is applied at the output during end of line test at customer side
the corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by ΔkILIS The derating of kILIS after calibration is calculated using the formulas in Current sense ΔkILIS calculation formulas and it is specified by ΔkILIS Current sense ΔkILIS calculation formulas ∆ kILIS, MIN = 100 * MIN kILIS @IL CAL _L kILIS @IL CAL − 1, kILIS @IL CAL H kILIS @IL CAL − 1 Equation 1 ∆ kILIS, MAX = 100 * MAX kILIS @IL CAL _L kILIS @IL CAL − 1, kILIS @IL CAL H kILIS @IL CAL − 1 Equation 2 I IS I LI L(OL) I IS(OL) I IS(EN) Figure 21 Current sense ratio in open load at ON condition BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 33 1.1 2020-11-20

The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift over temperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H.

8.2.2 Fault current ( IIS(FAUL T))

As soon as a protection event occurs, the value of the internal latch (see Chapter 7.3 for more details) is changed from 0 to 1, a current IIS(FAUL T) is provided by pin IS when DEN is set to "high"and both the high-side and low-side output stage of the affected channel are switched OFF. If the device is switched OFF by protection event and its EN pin is driven by PWM with pulse width < tDELAY(LR), the internal latch could not be reset, the current IIS(FAUL T) is provided each time the device diagnosis is activated by DEN. If the device is OFF and the internal latch is not in the reset state, the current IIS(FAUL T) is also provided each time the device diagnosis is checked. Figure 22 shows the relation between high-side current sense (IIS = IL / kILIS) and IIS(FAUL T). I IS I L I IS(FAUL T) I L / k ILIS I IS(FAUL T),max I L(OVL),maxI L(OVL),min I IS(FAUL T),min Figure 22 SENSE behavior - overview If present (EN = IN = DEN = 1, no fault present), the current sense signal can be differentiated from the fault current IIS(FAUL T), up to the max. possible load current IL(OVL0)_-40(HS),max.

8.3 Diagnosis in OFF state

When a power output stage is in OFF state, the BTN7030-1EPA can measure the output voltage and compare it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and a switchable pull-up current source) it is possible to detect if the load is missing or if there is a short circuit to battery. If a fault condition was detected by the device (the internal latch has a value different from the reset value, as described in Chapter 8.2.2) a current IIS(FAUL T) is provided by IS pin each time the channel diagnosis is checked also in OFF state.

8.3.1 Open load current ( IIS(OLOFF))

In OFF state, when DEN pin is set to "high" , the VDS voltage of the high-side switch is compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 34 1.1 2020-11-20

battery, VDS(HS) ~ VS therefore VDS(HS) > VDS(OLOFF). When the diagnosis is active and VDS(HS) ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Open Load in OFF detection is only possible for half-bridge configuration where the load is supposed to be connected between the OUT pin of the device and GND. Figure 23 shows the relationship between IIS(OLOFF) and IIS(FAUL T) as functions of VDS. The two currents don´t overlap making always possible to differentiate between open load in OFF and fault condition. I IS V DS I IS(OLOFF) V DS(OLOFF) I IS(FAUL T) Figure 23 IIS in OFF State It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the pin EN and the sensing at pin IS for open load in OFF diagnosis to allow the internal comparator to settle. In Figure 24 the timings for an open load detection are shown - the load is always disconnected. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 35 1.1 2020-11-20

t EN / IN t DEN V OUT ~ V S t IS(OLOFF)_D t I IS(OLOFF) I IS I IS(OL) V DS(OLOFF) t Load connected to GND Figure 24 Open load in OFF timings - load disconnected

8.4 SENSE timings

Figure 25 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load change). As a proper signal cannot be established before the load current is stable (therefore before tON): tsIS(DIAG) = tsIS(ON) + tON BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 36 1.1 2020-11-20

8.5 Electrical characteristics diagnosis

Table 14 Electrical characteristics diagnosis VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SENSE leakage current when disabled IIS(OFF) – 0.01 0.5 µA DEN = "low" IL ≥ IL(NOM) VIS = 0 V PRQ-209 SENSE leakage current when enabled at T J ≤ 85 °C IIS(EN)_85 – 0.2 1 µA (1) TJ ≤ 85°C DEN = "high" IL = 0 A See Figure 21 PRQ-210 SENSE leakage current when enabled at T J = 150 °C IIS(EN)_150 – 0.2 1 µA TJ = 150°C DEN = "high" IL = 0 A See Figure 21 PRQ-211 SENSE Signal Saturation Voltage for kILIS operation (VS-VIS) VSIS_k – 0.5 1 V (1) VS = 6 V EN = IN =DEN ="high" IL ≤ 1.5 * IL(NOM) PRQ-212 Power supply to IS pin clamping voltage at T J = -40°C VIS(CLAMP)_-40 33 36.5 42 V IIS = 1 mA TJ = -40 °C See Figure 19 PRQ-215 Power supply to IS pin clamping voltage at T J = 25°C VIS(CLAMP)_25 35 38 44 V (2) IIS = 1 mA TJ ≥ 25 °C See Figure 19 PRQ-216 Electrical characteristics diagnosis SENSE fault current IIS(FAUL T) 4.4 5.5 10 mA See Figure 22 and Figure 23 PRQ-217 SENSE open load in OFF current IIS(OLOFF) 1.9 2.5 3.5 mA See Figure 22 and Figure 23 PRQ-218 SENSE open load in OFF delay time tIS(OLOFF)_D 30 70 120 µs VDS < VOL(OFF) from EN falling edge to IIS = IS(OLOFF),MIN * 0.9 DEN = "high" latch = 0 See Figure 24 PRQ-219 Open load VDS detection threshold in OFF state VDS(OLOFF) 1.3 1.8 2.3 V See Figure 23 PRQ-221 BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 38 1.1 2020-11-20

Table 14 Electrical characteristics diagnosis (continued) VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SENSE settling time with nominal load current stable tsIS(ON) – 5 20 µs IL = IL(CAL) from DEN rising edge to IIS = IL / (kILIS,MAX @ IL) * 0.9 See Figure 25 PRQ-222 SENSE settling time with small load current stable tsIS(ON)_SLC – – 60 µs (1) IL = IL(CAL)_OL from DEN rising edge to IIS = IL / (kILIS,MAX @ IL) * 0.9 See Figure 26 PRQ-223 SENSE disable time tsIS(OFF) – 5 20 µs (1) From DEN falling edge to IIS = IIS(OFF) See Figure 25 PRQ-224 SENSE settling time after load change tsIS(LC) – 5 20 µs (1) From IL = IL(CAL)_L to IL = IL(CAL) (see ΔkILIS(NOM)) See Figure 25 PRQ-225 SENSE settling time after load change with small load current tsIS(LC)_SLC – 250 400 µs (1) DEN = "high" from Load Change to IIS = IL / (kILIS @ IL) from IL(CAL) to IL(CAL)_OL See Figure 26 PRQ-226 Diagnosis power output stage - 15 mΩ high-side Open load output current at IIS= 4 µA IL(OL)_4u 8 21 35 mA IIS = IIS(OL) = 4 µA See Figure 21 PRQ-227 Current sense ratio at IL=IL02 kILIS02 -50% 4300 +50% IL02 = 20 mA PRQ-232 Current sense ratio at IL=IL05 kILIS05 -42% 4300 +42% IL05 = 100 mA PRQ-235 Current sense ratio at IL=IL08 kILIS08 -40% 4300 +40% IL08 = 250 mA PRQ-238 Current sense ratio at IL=IL11 kILIS11 -25% 4300 +25% IL11 = 1 A PRQ-241 Current sense ratio at IL=IL14 kILIS14 -8% 4300 +8% IL14 = 2.8 A PRQ-244 Current sense ratio at IL=IL16 kILIS16 -6% 4300 +6% IL16 = 5.5 A PRQ-246 BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Diagnosis Datasheet 39 1.1 2020-11-20

9 Application information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

9.1 Application setup

M TREV BTN7030 RA/D RIS_PROT RDEN REN RIN GPIO GPIO CVS VS RSENSEDZ1 CSENSE RPD ROL Figure 27 BTN7030-1EPA application diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application.

9.2 External components

Table 15 Suggested component values Reference Value Purpose REN RIN RDEN 4.7 kΩ Protection of the microcontroller and device during overvoltage and during loss of ground. RPD 47 kΩ Output polarization (pull-down, optional) Allows to detect if the OUT pin is shorted to VS. ROL 1.5 kΩ Output polarization (pull-up, optional) Ensure polarization of BTN7030-1EPA output during open load in OFF diagnosis. COUT 100 nF Protection of BTN7030-1EPA output during ESD events and BCI. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge

Application information

Datasheet 41 1.1 2020-11-20

Table 15 Suggested component values (continued) T1 BC 807 Switch the battery voltage for open load in OFF diagnosis. (optional) CVS 100 nF Filtering of voltage spikes on the battery line. TREV - Protection of BTN7030-1EPA during reverse polarity. DZ2 33 V Z- Diode Suppressor diode Protection during overvoltage and in case of loss of battery while driving an inductive load. RSENSE 1.2 kΩ SENSE resistor RIS_PROT 4.7 kΩ Protection during overvoltage, reverse polarity, loss of ground. Value to be tuned according to microcontroller specifications, together with RA/D. DZ1 7 V Z- Diode Protection of the microcontroller during overvoltage. (Optional, depending on the microcontroller’s specification) RA/D 4.7 kΩ Protection of microcontroller ADC input during overvoltage, reverse polarity, loss of ground. Value to be tuned according to microcontroller specifications, together with RIS_PROT. CSENSE 220 pF Sense signal filtering A time constant (RA/D ⋅ CSENSE) longer than 1 µs is recommended. The stray inductances have to be minimized in the power bridge design as it is necessary in all switched high power bridges. Therefore it is recommended to ensure that the offset between the BTN7030-1EPA’s ground (GND pin) and the microcontroller’s (signal) ground is minimized. It is recommended to do the freewheeling in the high-side path until the load current is 0, to avoid reverse currents through the low-side power stage, thus minimizing power dissipation and avoid an unnecessary stress of the device. If used in full bridge configuration, it is strongly recommended to change the direction of a motor not before the motor fully stopped thus motor current is 0 A, in order to avoid overvoltage at OUT due to back EMF, e.g. in load dump situations. If the load also can provide power to the device, e.g. a motor or inductance in generator mode, it is recommended not to use only a diode for reverse polarity but to allow a current flow back to the supply Vbat, to prevent the device from overvoltage situations. In such a scenario, the capacitor CVS between VS and GND pin has to be dimensioned accordingly. Note: The suggested component values above are determined for typical applications. Based on the application circuit and the used components connected to BTN7030-1EPA, it could be necessary to adjust the values above to

9.3 Bidirectional loads and open load in OFF detection

A bidirectional load, like a motor or a solenoid, can be driven with two BTN7030-1EPA half-bridge in H-bridge configuration, as shown in Figure 28. In order to perform an open load in OFF detection, the high-side output stage of one half-bridge has to be switched on with IN = EN = "high" (right BTN7030-1EPA in Figure 28). As described in Chapter 8.3.1, and in combination with a pull-up resistor RPU (or alternatively a pull-down resistor RPD) the other half-bridge can check for open load condition. BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Datasheet 42 1.1 2020-11-20

M TREV BTN7030 IN EN DEN ISGND OUT VS BTN7030 CVS2 GPIO GPIO GPIO VDD GPIO GPIO GPIO ADC VSS R A/D R IS _P R O T R EN1 R DEN1 R IN1 R PD R EN2 R DEN2 R IN 2 R SENSE DZ1 DZ2 C OUT2 C OUT1 VS Figure 28 Application circuit: H-bridge with two BTN7030-1EPA Note This is a very simplified example of an application circuit. The function must be verified in the real application.

9.4 Further application information

Please contact us for information regarding the Pin FMEA
For further information you may contact http://www.infineon.com/ BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge

Datasheet 43 1.1 2020-11-20

1)DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.15 MAX. PER SIDE 2)DAMBAR PROTUSION SHALL BE MAXIMUM 0.1 MM TOTAL IN EXCESS OF LEAD WIDTH 1.15MAX. 14x 14x STANDOFF C 14x 1 7 14 8 MARKING SEATINGPLANE COPLANARITY 0.67±0.25 4.9±0.1 6±0.2 0°...8° 2.65±0.1

0.15 A-B

0.15 D

0.25 A-B C

0.2 D 0.65 0.25±0.05 7 1 8 14 BOTTOMVIEW 4±0.1 0.08 C 3.9±0.1 D A B 0.1 (0.2) 2x0.1 2x 0.25 (0.95) 0.05±0.05 GAUGE PLANE ALL DIMENSIONS ARE IN UNITS MM THE DRAWINGIS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1][ Figure 29 PG-TSDSO-14 (thin (slim) dual small outline 14 pins) package outline BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge Package dimensions Datasheet 44 1.1 2020-11-20

copper solder mask stencil apertures 0.65 0.45 1.31 2.85 2.65 0.65 0.45 1.31 2.85 1.85 2.65 1.075 2.85 2.85 ALL DIMENSIONS ARE IN UNITS MM Figure 30 PG-TSDSO-14 (thin (slim) dual small outline 14 pins) package pads and stencil To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

11 References

Revision history

1.0 2020-08-11 Initial release 1.1 2020-11-20 Chapter Open load current (IIS(OLOFF)): refined formulation for usage Chapter External components: refine explanation to RPD BTN7030-1EPA NovalithIC™ Lite – smart integrated half-bridge References Datasheet 45 1.1 2020-11-20

All referenced product or service names and trademarks are the property of their respective owners. Edition 2020-11-20 Published by Infineon Technologies AG

81726 Munich, Germany

© 2020 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-qsn1525101134268 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

Product Information

BTN7030-1EPA specifications and overview.

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NovalithIC??Lite ??smart integrated half-bridge v1.1 2020-11-20

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NovalithIC??Lite ??smart integrated half-bridge v1.1 2020-11-20

Source title BTN7030-1EPA Datasheet(PDF) - Infineon Technologies AG

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