BTHQ21605V-COG ETC2 | Alldatasheet
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Technical content
Datasheet sections
- 4.1 ELECTRICAL MAXIMUM RATINGS (Ta=25 qC)
- 4.2 ENVIRONMENTAL CONDITION
- 5.1 TYPICAL ELECTRICAL CHARACTERISTICS
- 5.2 TIMING SPECIFICATIONS
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 2 OF 11 DOCUMENT REVISION HISTORY 1: DOCUMENT REVISION F R O M T O DATE DESCRIPTION CHANGED BY CHECKED BY A 2003.10.16 First release. SUNNY LEE MICHAEL TSE
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 4 OF 11 Specification of LCD Module Type Model No.: COG-BTHQ21605-02 1. General Description x 16 characters (5 x 8 dots) x 2 lines FSTN Positive Black & White Reflective LCD Character module. x Driving scheme: 1:18 multiplexed drive, 1/4 bias. x Optimal view direction: 6 O’clock. x Driving IC: ‘PHILIPS’ PCF 2119RU/2/F2 COG form LCD controller/driver. x Data interface: I2C-bus. x RTV coating. 2. Mechanical Specifications The mechanical detail is shown in Fig. 2 and summarized in Table 1 below. Table 1 Parameter Specifications Unit Outline dimensions 67.00(W) x 27.8(H) x 2.80(D) (Excluded pins and epoxy) mm Viewing area 61.0(W) x 15.8(H) mm Active area 56.20(W) x 11.50(H) mm Display format 16 characters (5 x 8 dots) x 2 lines - Character size 2.95(W) x 5.553(H) mm Character spacing 0.60(W) x 0.394(H) mm Character pitch 3.55(W) x 5.947(H) mm Dot size 0.578(W) x 0.681(H) mm Dot spacing 0.015(W) x 0.015(H) mm Dot pitch 0.593(W) x 0.696(H) mm Weight Approx. 10.0 grams
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 5 OF 11 Figure 1 and Figure 2: Specification Drawing
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 6 OF 11 'PHILIPS' PCF2119RU/2/F2 (COG) LCD CONTROLLER/ DRIVER
2 LINES X 16 CHARACTERS
(5X8 DOTS) COG-BTHQ21605V LCD DISPLAY VDD VLCD VSS SDA SCL POR Figure 3: Block Diagram Figure 4: Reference Circuit
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 7 OF 11 3. Interface signals Table 2 Pin No. Symbol Description
1 VLCD LCD driver voltage
2 VSS Ground (0V)
3 VDD Power supply for logic. 4S D A I 2C serial data input/output 5 POR External power –on reset input. Active High. 6S C L I 2C serial clock input 4. Absolute Maximum Ratings
4.1 Electrical Maximum Ratings (Ta = 25 ºC)
Parameter Condition Symbol Min. Max. Unit Supply voltage range (Logic) - VDD - VSS -0.5 +4.0 V Input voltage range OSC,SCL,SDA Vi -0.5 VDD +0.5 V Input voltage range (LCD) V LCD -0.5 +6.5 V Note: The modules may be destroyed if they are used beyond the absolute maximum ratings. All voltage values are referenced to VSS = 0V .
4.2 Environmental Condition
(Topr) Storage Temperature (Tstg) Item Min. Max. Min. Max. Remark Ambient Temperature -10qC +50 qC- 2 0 qC +65 qC Dry Humidity 95% max. RH for Ta d 40 qC < 95% RH for Ta > 40qC no condensation Vibration (IEC 68-2-6) cells must be mounted on a suitable connector Frequency: 10 a 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. 3 directions Shock (IEC 68-2-27) Half-sine pulse shape Pulse duration : 11 ms Peak acceleration: 981 m/s2 = 100g Number of shocks : 3 shocks in 3 mutually perpendicular axes. 3 directions
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 8 OF 11 5. Electrical Specifications
5.1 Typical Electrical Characteristics
At Ta = 25 qC, VDD = 3Vr5%, VSS=0V . Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit Operating voltage (Logic) VDD-VSS 2.85 3.0 3.15 V Operating voltage for LCD (built-in) VLCD-VSS Note 1 5.0 5.3 5.6 V Input signal voltage low (SDA, SCL) Vil 0 - 0.3 VDD V Input signal voltage high (SDA, SCL) Vih 0.7 VDD - 5.5 V Character mode, VDD =3.0V - 0.17 0.26 mA Operating supply current I DD Checker board mode, VDD =3.0V - 0.18 0.27 mA Note (1) : There is tolerance in optimum LCD driving voltage during production and it will be within the specified range.
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 9 OF 11
5.2 Timing Specifications
Refer to Fig. 5, I2C Bus Timing Diagram of ‘PHILIPS’ PCF2119. Table 6 Parameters Symbol Min. Typ. Max. Unit LCD frame frequency (internal clock) (note 1) fFR 45 81 147 Hz Oscillator frequency(not available at any pin) f OSC 140 250 450 kHz External clock frequency f OSC(ext) tbf - 450 kHz Oscillator start-up time after power-down t OSCST - 200 300 Ps Timing characteristics: I2C-bus interface; (note 2) SCL clock frequency f SCL - - 400 kHz SCL clock LOW period t LOW 1.3 - - Ps SCL clock HIGH period t HIGH 0.6 - - Ps Data set-up time t SU;DAT 100 - - ns Data hold time t HD;DAT 0- - n s SCL and SDA rise time t r - - 300 ns SCL and SDA fall time t f - - 300 ns Capacitive bus line load C B 400 pF Set-up time for a repeated START condition t SU;STA 0.6 - - Ps START condition hold time t HD;STA 0.6 - - Ps Set-up time for STOP condition t SU;STO 0.6 - - Ps Tolerable spike width on bus t SW - - 50 ns Notes : 1. VDD=5.0V . 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V IL and VIH with an input voltage swing to VSS to VDD.
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 10 OF 11 Figure 5: I2C Bus Timing Diagram of ‘PHILIPS’ PCF2119.
VL-FS-COG-BTHQ21605-02 REV . A (BTHQ 21605V-FSRE-I2C-COG) OCT/2003 PAGE 11 OF 11 6. Character Set ‘R’ in CGROM