BTG70020A-1ESW

BTG70020A-1ESW INFINEON | Alldatasheet

Document overview

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Technical content

Features

• High-side switch with diagnosis and embedded protection
• Selectable integrated I2t function for wire harness protection
• Operating current < 60 µA for active supply in key-off mode
• IDL pin for microcontroller wake-up in idle mode
• Adjustable overcurrent threshold
• Capacitive load switching mode
• Sequential diagnosis for status readout
• Reverse ON for low power dissipation in reverse polarity
• Switch-on capability while inverse current condition (Inverse ON) Potential applications
• Replaces electromechanical relays, fuses and discrete circuits
• Protection of wire harness and system supply
• Main switch for ECU power supplies
• Switch for active power supplies in key-off mode
• Suitable for resistive, inductive and capacitive loads up to 21.5 A Product validation Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.

Description

The device is a smart power high-side switch, providing enhanced protection and diagnosis functions. Besides standard device protection functions it offers a selectable I2t protection, an adjustable overcurrent protection, an idle mode as well as a sequential diagnosis mode via IS pin. VBAT ZWIRE RGND CVS1 CVSGND Optional GND GND VS PROFETTM Wire Guard OCT I2t IN DEN IDL IS OUTRI2t ROCT RIN RDEN RIS_PROT RSENSE DZ1 RIDL RAD CSENSE Optional GPIO GPIO GPIO ADC VSS VCC RIDLPU Logic supply CVS2 Power GND Logic GND Chassis GND RPD GND Optional COUT GND ZWIREZLOAD* ROL Microcontroller DZ2 * See chapter 1 „potential applications“ Product type Package Marking BTG70020A-1ESW PG-TSDSO-24 70020A1W BTG70020A-1ESW Datasheet Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document Rev. 1.00 www.infineon.com 2023-12-07

Datasheet 2 Rev. 1.00 2023-12-07

Datasheet 3 Rev. 1.00 2023-12-07

Datasheet 4 Rev. 1.00 2023-12-07

1 Product description

1.1 Product summary

Minimum operating voltage VS(OP) 4.1 V Minimum operating voltage (cranking) VS(UV) 2.75 V Maximum operating voltage VS 28 V Minimum overvoltage protection (TJ = 25°C) VDS(CLAMP)_25 35 V Maximum current in sleep mode (TJ ≤ 85°C) IVS(SLEEP)_85 1.3 µA Operating current in idle mode (channel ON) IGND(IDLE) 60 µA Maximum operating current IGND(I2t_D) 7.4 mA Typical ON-state resistance (TJ = 25°C) RDS(ON)_25 2.2 mΩ Maximum ON-state resistance (TJ = 150°C) RDS(ON)_150 4.1 mΩ Nominal load current (TA = 85°C) IL(NOM)_85 21.5 A Highest configurable overcurrent detection threshold (TJ = -40°C, IOCT = 50 µA) IL(HOCT)_-40 142 A Typical current sense ratio at IL = IL(NOM)_85 kILIS 24500

1.2 Further features

Further features are named in detail as follows:

• Green product (RoHS compliant)
• Proportional load current sense
• Open load in ON and OFF state
• Short circuit protection to ground and battery
• Readout of I2t and overcurrent protection settings
• Readout of wire harness protection status
• Absolute and dynamic temperature limitation with intelligent latch
• Adjustable overcurrent protection (tripping) with intelligent latch
• Selectable I2t function for wire harness protection with intelligent latch
• Undervoltage shutdown
• Overvoltage protection with external components BTG70020A-1ESW Datasheet

Datasheet 5 Rev. 1.00 2023-12-07

2 Block diagram and terms

2.1 Block diagram

Sequential diagnosis output Channel Input logicON + diagnosis I2t + OCTprotection selection Internal reversepolarity protection GND circuitry IDL IS IN DEN I2t OCT GND Reverse ONInverse ON Gate control+chargepump Overtemperature Voltage sensor Driverlogic Capacitive load switching Overvoltage clamping Overcurrent protection I2t protection T VS OUT Load current sense Figure 1 Block diagram

2.2 Terms

Figure 2 shows all terms used in this datasheet, with associated convention for positive values. VDEN VS IVS IS VS VIN IIN IN I2t GND IGND OUT VIS IIS IDL OCT VOCT DEN IDEN VDS VOUT IL VI2t VIDL II2t IIDL IOCT Figure 2 Voltage and current convention BTG70020A-1ESW Datasheet Datasheet 6 Rev. 1.00 2023-12-07

3 Pin configuration

3.1 Pin assignment

6 GND

8 DEN

10 I2t

11 IDL

12 OCT 13 OUT

14 OUT

15 OUT

16 OUT

17 OUT

18 OUT

19 OUT

20 OUT

21 OUT

22 OUT

23 OUT

24 OUT

Figure 3 Pin configuration

3.2 Pin definitions and functions

EP VS (exposed pad) Supply voltage Battery voltage.

6 GND Ground

Ground connection for the internal logic.

7 IN Input channel

Digital signal to switch ON the channel (“high” active). If not used: connect with a 10 kΩ resistor either to GND pin or to module ground.

8 DEN Diagnostic enable

Digital signal to enable device diagnosis (“high” active) and to clear the protection latch of channel. If not used: connect with a 10 kΩ resistor either to GND pin or to module ground.

9 IS SENSE current output

Analog/digital signal for diagnosis. If not used: left open.

10 I2t Selectable I2t protection curve

A resistor RI2t needs to be connected between I2t pin and GND pin to select one of the available I2t protection curves. If not used: left open. Curve selection as described in Chapter 9.1. BTG70020A-1ESW Datasheet Datasheet 7 Rev. 1.00 2023-12-07

11 IDL Idle mode open drain output

Digital signal to inform / wake-up the microcontroller in case of idle mode ("high impedance" in idle/sleep mode; "low" in all other modes). If not used: left open.

12 OCT Adjustable overcurrent threshold

A resistor ROCT needs to be connected between OCT pin and GND pin to adjust the overcurrent threshold. If not used: left open. Threshold selection as described in Figure 27. 1-5 NC Not connected, internally not bonded. 13-24 OUT Output Protected high-side power output channel1). 1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. BTG70020A-1ESW Datasheet Datasheet 8 Rev. 1.00 2023-12-07

4 General product characteristics

4.1 Absolute maximum ratings

Table 2 Absolute maximum ratings TJ = -40°C to +150°C; all voltages and currents according to the voltage and current conventions, specified in Chapter 2.2 (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Supply pins Power supply voltage VS -0.3 – 28 V 1) PRQ-128 Load dump voltage VBAT(LD) – – 35 V 1) Suppressed load dump acc. to ISO16750-2 (2012) Ri = 2 Ω PRQ-130 Supply voltage for short circuit protection VBAT(SC) 0 – 24 V 1) Setup acc. to AEC- Q100-012 PRQ-132 Reverse polarity voltage VBAT(REV) -18 – – V 1) t ≤ 5 min TA = 25 °C Setup as described in Figure 54 PRQ-134 Current through GND pin IGND -50 – 50 mA 1) RGND according to Chapter 11 PRQ-138 Logic & control pins (digital input = DI) DI = IN, DEN Current through DI pin IDI -1 – 2 mA 1) 2) PRQ-141 Current through DI pin - reverse battery condition IDI(REV) -1 – 10 mA 1) 2) t ≤ 5 min PRQ-142 Analog & control pins (analog input = AI) AI = I2t, OCT Current through AI pin IAI -2 – 1 mA 1) 2) PRQ-359 Current through AI pin - reverse battery condition IAI(REV) -10 – 1 mA 1) 2) t ≤ 5 min PRQ-362 (table continues...) BTG70020A-1ESW Datasheet Datasheet 9 Rev. 1.00 2023-12-07

Table 2 (continued) Absolute maximum ratings TJ = -40°C to +150°C; all voltages and currents according to the voltage and current conventions, specified in Chapter 2.2 (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Logic & control pins (digital output = DO) DO = IDL Voltage at DO pin VDO -0.3 – 5.5 V 1) 2) PRQ-828 Current through DO pin IDO -1 – 2 mA 1) 2) PRQ-360 Current through DO pin - reverse battery condition IDO(REV) -1 – 10 mA 1) 2) t ≤ 5 min PRQ-361 IS pin Voltage at IS pin VIS -1.5 – VS V 1) IIS < IIS(OFF) PRQ-144 Current through IS pin IIS -25 – IIS(SAT), MAX mA 1) PRQ-146 Temperatures Junction temperature TJ -40 – 150 °C 1) PRQ-147 Storage temperature TSTG -55 – 150 °C 1) PRQ-148 ESD robustness ESD robustness all pins (HBM) VESD_HBM1 -2 – 2 kV 1) HBM3) PRQ-149 ESD robustness OUT vs. GND and VS connected (HBM) VESD_HBM2 -4 – 4 kV 1) HBM3) PRQ-150 ESD robustness all pins (CDM) VESD_CDM1 -500 – 500 V 1) CDM4) PRQ-151 ESD robustness corner pins (CDM) - (pins 1, 12, 13, 24) VESD_CDM2 -750 – 750 V 1) CDM4) PRQ-1178 1) Not subject to production test - specified by design. 2) Maximum VDI/VDO/VAI to be considered for latch-up tests: 5.5 V. 3) Human body model (HBM) robustness according to AEC - Q100-002. 4) Charged device model (CDM) robustness according to AEC - Q100-011 Rev-D; voltage level refers to test condition (TC) mentioned in the standard. BTG70020A-1ESW Datasheet Datasheet 10 Rev. 1.00 2023-12-07

Notes: 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 3 Absolute maximum ratings - power stages Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Load current |IL| – – IL(HOCT) ,MAX A 1) PRQ-157 Maximum energy dissipation - single pulse EAS – – 270 mJ 1) IL = 2⋅IL(NOM)_85 TJ(0) = 150°C VS = 28 V PRQ-1123 Maximum energy dissipation - repetitive pulse EAR – – 70 mJ 1) IL = IL(NOM)_85 TJ(0) = 85°C VS = 13.5 V 1M cycles PRQ-1124 1) Not subject to production test - specified by design. BTG70020A-1ESW Datasheet Datasheet 11 Rev. 1.00 2023-12-07

4.2 Functional range

VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Supply voltage range for normal operation VS(NOR) 5 13.5 20 V 1) PRQ-158 Lower extended supply voltage range for operation (normal) VS(EXT ,LOW) 2.75 – 5 V 1) 2) 3) 4) (Parameter deviations possible) PRQ-159 Upper extended supply voltage range for operation VS(EXT ,UP) 20 – 28 V 1) 4) (Parameter deviations possible) PRQ-160 Junction temperature TJ -40 – 150 °C 1) PRQ-161 1) Not subject to production test - specified by design. 2) In case of VS voltage decreasing refer to the maximum voltage of VS(UV). In case of VS voltage increasing refer to the maximum voltage of VS(OP). 3) Calculation of I2t protection curve with IL = 0 A for VS < 2.75 V (GND resistor voltage drop not included). 4) Device protection functions still operative.

4.3 Thermal resistance

Table 5 Thermal resistance This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Thermal characterization parameter junction to top ΨJTOP – 0.6 1.0 K/W 1) PRQ-1126 Thermal resistance junction to case RthJC – 0.9 1.5 K/W 1) Simulated at exposed pad PRQ-1127 Thermal resistance junction to ambient RthJA – 25.4 – K/W 1) PRQ-1128 1) Not subject to production test - specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip + package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C, PDISSIPATION = 1 W. BTG70020A-1ESW Datasheet Datasheet 12 Rev. 1.00 2023-12-07

4.4 PCB setup

70 µm modeled (traces, cooling area) 1,5 mm 70 µm, 5% metalization* *: means percentual Cu metalization on each layer Figure 4 1s0p PCB cross section 70 µm modeled (traces) 35 µm, 9 0% metalization* 1, 5 mm 70 µm, 5% metalization* 35 µm, 9 0% metalization* *: means percentual Cu metalization on each layer Figure 5 2s2p PCB cross section PCB 1s0p + 600 mm² cooling PCB 2s2p / 1s0p footprint Figure 6 PCB setup for thermal simulations Figure 7 Thermal vias on PCB for 2s2p PCB setup BTG70020A-1ESW Datasheet Datasheet 13 Rev. 1.00 2023-12-07

4.5 Thermal impedance

ZthJA[K/W] TA= 105°C Time [s] Z th J A - BTG70020A-1ESW JEDEC 2s2p JEDEC 1s0p - 600 mm² JEDEC 1s0p - 300 mm² JEDEC 1s0p - footprint Figure 8 Typical thermal impedance 0 100 200 300 400 500 600 RthJA[K/W] TA= 105°C Cooling area [mm²] RthJA-BTG70020A-1ESW JEDEC 1s0p Figure 9 Typical thermal resistance BTG70020A-1ESW Datasheet Datasheet 14 Rev. 1.00 2023-12-07

5 Logic pins

The device has two digital pins: One to control the output stage and the other one to control the diagnosis. Furthermore, there are two analog input pins for either selecting a generic I2t protection curve, or adjusting the overcurrent threshold; one open drain output pin for idle mode indication is available.

5.1 Latched input pin (IN)

The input pin IN activates the output channel. The input circuitry is compatible with 3.3 V and 5 V microcontrollers. The Latched Input feature activates an internal pull up current source in order to keep the input high after it’s activation. This feature is deactivated when the DEN pin is set to high. The electrical equivalent of the input circuitry is shown in Figure 10. Indicating the behavior of the digital input current at IN pin IIN(H) by the change of the DEN and IN pin. In case the pin is not used, it must be connected with a 10 kΩ resistor either to GND pin or module ground. The latched input feature allows the microcontroller to switch the GPIO controlling the IN pin into high impedance, while keeping the mode of the input status unchanged. The input latch maintains the last mode of the input status as long as:

• Either the IN pin is not actively driven above or below the input thresholds
• The DEN pin is kept low VS V S(CLAMP) DEN ESD V DI(CLAMP) IN I IN GND R G N D I GND V DI Figure 10 IN pin circuitry The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VIN(HYS). The relationship between these two values is shown in Figure 11. The voltage VIN needed to ensure a “high” state is always higher than the voltage needed to ensure a “low” state. BTG70020A-1ESW Datasheet

Datasheet 15 Rev. 1.00 2023-12-07

V DI(TH),MAX V IN(HYS) , V DEN(HYS) t V DI V DI(TH),MIN Internal channel activation signal t 0 x 1 x 0 V DI(TH) Figure 11 Input threshold voltages and hysteresis

5.2 Diagnosis pin (DEN)

The diagnosis enable (DEN) pin controls the diagnosis circuitry and can be used to reset the latched protection. The protection circuitry is not disabled by the DEN pin. When the DEN pin is set to “high” , the diagnosis is enabled (see Chapter 10.1.1 for more details) as well as the sequential diagnosis by applying a dedicated DEN "low" pulse (see Figure 42 for more details). When it is set to “low” , the diagnosis is disabled and the IS pin is set to high impedance. The latched protection is reset with a dedicated DEN "high" pulse (see Figure 32). ESDV DI(CLAMP) DEN I DEN GND R G N D I GND VS V S(CLAMP) V DI Figure 12 DEN pin circuitry When the device is in idle mode and the DEN pin is set to "high" , the diagnosis is enabled (change from idle mode either to I2t with diagnosis mode or active with diagnosis mode). When the DEN pin is set to "low" and all idle mode conditions are fulfilled, the device changes to idle mode. BTG70020A-1ESW Datasheet Datasheet 16 Rev. 1.00 2023-12-07

The protection latch is reset by applying a pulse (rising edge followed by a falling edge) at the DEN pin while the IN pin is "low" (see Chapter 8.3 and Figure 32 for more details).

5.3 I2t selection pin (I2t)

The I2t selection pin (I2t) is used to select one of the six available I2t protection curves. The selection is made by the value of the resistor connected between I2t pin and GND pin. V S(CLAMP) ESDV AI(CLAMP) V REF GND R G N D IGND I2t IAI V I2t R I2 t VS I2t p in s hort I2t p rotection c urve 1 I2t p rotection c urve 2 I2t p rotection c urve 3 I2t p rotection c urve 4 I2t p rotection c urve 5 I2t p rotection c urve 6 I2t p in o pen I2t decoder Figure 13 I2t selection circuitry The device recognizes an I2t pin short if the resistance between I2t pin and GND is lower than RI2t_SHORT. In this case the I2t protection changes to I2t protection curve 1 and additionally a sense current of IIS(I2t_SHORT) is sent out at the IS pin when the sequential diagnosis address #2 is selected. If the resistance between I2t pin and GND is higher than RI2t_OPEN an I2t pin open is detected by the device. In this case the I2t protection curve 1 is internally selected and additionally a sense current of IIS(I2t_OPEN) is sent out at the IS pin when the sequential diagnosis address #2 is selected. BTG70020A-1ESW Datasheet Datasheet 17 Rev. 1.00 2023-12-07

5.4 Overcurrent threshold pin (OCT)

The overcurrent threshold (OCT) pin is used for an analog adjustment of the overcurrent threshold by connecting a resistor between the OCT pin and GND pin. V S(CLAMP) ESDV AI(CLAMP) V REF OCT decoder I IS(OCT_SHORT) I IS(OCT_OPEN) I L(xOCT) GND R G N D I GND OCT I AI V OCT R O C T VS Figure 14 OCT adjustment circuitry The device recognizes an OCT pin short if the current between the OCT pin and GND is higher than IOCT_SHORT. In this case the overcurrent threshold is internally set to the highest configurable overcurrent threshold IL(HOCT). Additionally, a sense current of IIS(OCT_SHORT) is sent out at the IS pin when the sequential diagnosis address #4 is selected. If the current between the OCT pin and GND is lower than IOCT_OPEN an OCT pin open is detected by the device. In this case the overcurrent threshold is internally set to the highest configurable overcurrent threshold IL(HOCT). Additionally, a sense current of IIS(OCT_OPEN) is sent out at the IS pin when the sequential diagnosis address #4 is selected. BTG70020A-1ESW Datasheet Datasheet 18 Rev. 1.00 2023-12-07

5.5 Idle mode pin (IDL)

The idle mode output pin (IDL) is an open drain output. It is set to high impedance in case of idle mode and sleep mode, and it is pulled down in all other modes. V S(CLAMP) IDLE or SLEEP ESD V DO(CLAMP) IDL I DO V DO R G N D I GND VS GND Figure 15 Idle mode pin circuitry

5.6 Electrical characteristics logic pins

Table 6 Electrical characteristics - logic pins VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Digital input (DI) pins: IN, DEN Digital input voltage threshold VDI(TH) 0.8 1.3 2 V See Figure 10, Figure 11 and Figure 12 PRQ-168 Digital input clamping voltage VDI(CLAMP1) – 7 – V 1) IDI = 1 mA See Figure 10 and Figure PRQ-169 Digital input clamping voltage VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA See Figure 10 and Figure PRQ-170 Digital input hysteresis at IN pin VIN(HYS) 0.30 0.45 – V 1) See Figure 10, Figure 11 PRQ-172 (table continues...) BTG70020A-1ESW Datasheet Datasheet 19 Rev. 1.00 2023-12-07

Table 6 (continued) Electrical characteristics - logic pins VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Digital input hysteresis at DEN pin VDEN(HYS) 0.20 0.35 – V 1) See Figure 10, Figure 11 and Figure 12 PRQ-1244 Digital input current at IN pin ("high") IIN(H) 1 10 25 µA VDI = 2 V DEN = "high" See Figure 10 PRQ-173 Digital input current at IN pin ("high") IIN(H) -25 -8 -1 µA VDI = 1.4 V DEN = "low" See Figure 10 PRQ-930 Digital input current at IN pin ("low") IIN(L) 1 10 25 µA VDI = 0.8 V DEN = "high" See Figure 10 PRQ-174 Digital input current at DEN pin ("high") IDEN(H) 1 10 25 µA VDI = 2 V See Figure 12 PRQ-931 Digital input current at DEN pin ("low") IDEN(L) 1 10 25 µA VDI = 0.8 V See Figure 12 PRQ-932 Digital output (DO) pin: IDL Digital output clamping voltage VDO(CLAMP1) – 7 – V 1) IDO = 1 mA Sleep or idle mode (where IDL is highohmic) See Figure 15 PRQ-880 Digital output voltage ("low") VDO(L) 0 – 0.4 V IDO = 0.2 mA Not in sleep or idle mode (then IDL is low ohmic) PRQ-367 Analog input (AI) pin: I2t, OCT Analog input clamping voltage VAI(CLAMP1) – 6.5 – V 1) IAI = -1 mA See Figure 13 and Figure PRQ-881 Maximum analog input current IAI_MAX 100 300 500 µA – PRQ-371 OCT pin reference voltage VOCT 0.44 0.50 0.55 V IOCT_MIN ≤ IOCT ≤ IOCT_MAX PRQ-891 (table continues...) BTG70020A-1ESW Datasheet Datasheet 20 Rev. 1.00 2023-12-07

Table 6 (continued) Electrical characteristics - logic pins VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. I2t pin reference voltage VI2t 0.48 0.59 0.69 V RI2t_MIN ≤ RI2t ≤ RI2t_MAX PRQ-892 1) Not subject to production test - specified by design. BTG70020A-1ESW Datasheet Datasheet 21 Rev. 1.00 2023-12-07

6 Power supply

The device is supplied by VS, which is used for the internal logic as well as supply for the power output stage. VS has an undervoltage detection circuit, which prevents the activation of the power output stage and diagnosis in case the applied voltage is below the undervoltage threshold (VS < VS(UV)). During power up, the internal power-on signal is set when supply voltage (VS) exceeds the minimum operating voltage (VS > VS(OP)).

6.1 Operation modes

The device has the following operation modes in case of VS > VS(OP):

• Sleep mode
• I2t mode
• I2t with diagnosis mode
• Inactive with diagnosis mode
• Idle mode
• Active with diagnosis
• Capacitive load switching (CLS) mode
• Capacitive load switching (CLS) with diagnosis mode
• Inactive mode The transition between operation modes is determined according to these variables:
• Logic level at IN pin
• PWM signal at IN pin
• Logic level at DEN pin
• Internal protection latch
• Load current IL level
• VDS voltage level
• Junction temperature
• Status of the selected I2t protection curve CLS Idle I2t Inactive with diagnosis I2t with diagnosis Sleep Unsupplied Inactive pwrup slp_iwdiwd_slp iwd_i2twd i2twd_iwd cls_ina idle_awd idle_ina idle_i2t i2t_idle i2t_ina ina_i2t slp_i2t ina_slp iwd_ina cls_i2ti2t_cls i2t_i2twdi2twd_i2t ina_iwdawd_idle awd_i2twd awd_iwd Active with diagnosis pwrdw CLS with diagnosis cls_clswd clswd_cls clswd_i2twd i2twd_clswd clswd_iwd Figure 16 Operation mode state diagram A more detailed description of the transitions, including the transition conditions and duration times are provided in the following table. BTG70020A-1ESW Datasheet

Datasheet 22 Rev. 1.00 2023-12-07

Table 7 Transition descriptions Name Start state End state Transition condition Duration time pwrdw Sleep Unsupplied VVS < VVS(UV) n.a. pwrup Unsupplied Sleep VVS > VVS(UV) n.a. iwd_slp Inactive with diagnosis Sleep DEN = "low" AND SI2t_A < (SI2t_I - SI2t_HYST) tT(iwd_slp) ina_slp Inactive Sleep SI2t_A < (SI2t_I - SI2t_HYST) tT(F10u) slp_i2t Sleep I2t IN = "high" tON cls_i2t CLS I2t (IN = "high" OR VDS < VDS(OLOFF)) AND DEN = "low" tT(CLS_I2t) idle_I2t Idle I2t IL > IL(IDLE) tT(IDLE_I2t) i2twd_i2t I2t with diagnosis I2t DEN = "low" tT(F10u) ina_i2t Inactive I2t IN = "high" tON i2t_cls I2t CLS IN = "pwm" AND VDS > VDS(OLOFF) tT(I2t_CLS) clswd_cls CLS with diagnosis CLS DEN = "low" tT(F10u) i2t_idle I2t Idle IL < (IL(IDLE) - IL(IDLE_HYST)) AND SI2t_A < (SI2t_I - SI2t_HYST) tT(I2t_IDLE) awd_idle Active with diagnosis Idle DEN = "low" tT(AWD_IDLE) idle_awd Idle Active with diagnosis DEN = "high" tT(F10u) i2t_i2twd I2t I2t with diagnosis DEN = "high" tsIS(ON15) awd_i2twd Active with diagnosis I2t with diagnosis IL > IL(IDLE) tsIS(ON15) clswd_i2twd CLS with diagnosis I2t with diagnosis IN = "high" OR VDS < VDS(OLOFF) tT(CLS_I2t) iwd_i2twd Inactive with diagnosis I2t with diagnosis IN = "high" tON cls_clswd CLS CLS with diagnosis DEN = "high" tsIS(ON234) i2twd_clswd I2t with diagnosis CLS with diagnosis IN = "pwm" AND VDS > VDS(OLOFF) tT(I2t_CLS) slp_iwd Sleep Inactive with diagnosis DEN = "high" tsIS(ON234) awd_iwd Active with diagnosis Inactive with diagnosis IN = "low" tOFF i2twd_iwd I2t with diagnosis Inactive with diagnosis IN = "low" tOFF (table continues...) BTG70020A-1ESW Datasheet Datasheet 23 Rev. 1.00 2023-12-07

Table 7 (continued) Transition descriptions Name Start state End state Transition condition Duration time clswd_iwd CLS with diagnosis Inactive with diagnosis IN = "low" tOFF ina_iwd Inactive Inactive with diagnosis DEN = "high" tsIS(ON234) i2t_ina I2t Inactive IN = "low" tOFF cls_ina CLS Inactive IN = "low" tOFF idle_ina Idle Inactive IN = "low" tOFF iwd_ina Inactive with diagnosis Inactive DEN = "low" tT(F10u)

6.1.1 Unsupplied

In this state the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the undervoltage threshold.

6.1.2 Power-up

The power-up condition is entered when the supply voltage (VS) is applied to the device. The supply is rising until it is above the minimum operating output voltage VS(OP), therefore the internal power-on signals are set.

6.1.3 Sleep mode

The device is in sleep mode when all digital input pins (IN, DEN) are set to “low” and the I2t status calculation is below the initial status SI2t_I minus the I2t status hysteresis SI2t_HYST. When the device is in sleep mode, the output is OFF. The current consumption is minimum (see parameter IVS(SLEEP)). No overtemperature or overcurrent protection mechanism is active when the device is in sleep mode. If a protection was previously triggered and has not been reset, the device will not enter sleep mode (see Chapter 8.3.1 for further details).

6.1.4 I2t mode

The I2t mode is entered as soon as the IN pin is set to “high” . The device is calculating the I2t status SI2t and switches the channel OFF as soon as the I2t protection function (selected curve) is triggered. A detailed explanation of the I2t status calculation can be found in Chapter 9.1. The current consumption is specified with IGND(I2t_D) (measured at GND pin because the current at VS pin includes the load current). Overcurrent, overtemperature and overvoltage protections are active. Since the DEN pin is set to "low" the diagnosis is not available.

6.1.5 Inactive with diagnosis mode

The device is in inactive with diagnosis mode as long as DEN pin is set to “high” while input pin is set to “low” . The channel is OFF. The initial I2t status value for the I2t status calculation depends on the actual I2t status. A detailed explanation of the I2t status calculation can be found in Chapter 9.1. The current consumption is specified by the parameter operating current in inactive with diagnosis mode IGND(INACT_D). Additionally, the sequential diagnosis is enabled and depending on the address the selected setting is present at the IS pin (for further information see Figure 42).

6.1.6 I2t with diagnosis mode

The device enters I2t with diagnosis mode as soon as the IN and DEN pin are set to “high” . Similar to I2t mode the device is calculating the I2t status SI2t and switches the channel OFF as soon as the I2t protection function (selected curve) is triggered. A detailed explanation of the I2t status calculation can be found in Chapter 9.1. The current BTG70020A-1ESW Datasheet Datasheet 24 Rev. 1.00 2023-12-07

consumption is specified with IGND(I2t_D) (measured at GND pin because the current at VS pin includes the load current). Overcurrent, overtemperature and overvoltage protections are active. Additionally, the sequential diagnosis is enabled and depending on the address the selected setting is present at the IS pin (for further information see Figure 42).

6.1.7 Idle mode

Idle mode is the low power mode of the device where the current consumption is reduced to IGND(IDLE) while the output channel stays ON. Idle mode is entered automatically when the device fulfills the following idle mode entry conditions:

• IN pin is set to "high"
• Load current level is below IL(IDLE) - IL(IDLE_HYST)
• DEN pin is set to "low"
• I2t protection status calculation S I2t_A < (SI2t_I - SI2t_HYST) The idle mode is left when the device fulfills one of the following idle mode exit conditions:
• IN pin is set to "low"
• Load current level is above IL(IDLE)
• DEN pin is set to "high" During idle mode the I2t protection as well as the temperature protection and sequential diagnosis function is not active.

6.1.8 Active with diagnosis

The active with diagnosis state is entered out of idle mode when the DEN pin is set to “high” and IL < IL(IDLE). The transition time from active with diagnosis to idle is defined by tT(awd_idle). During this state the I2t calculation is not active since IL < IL(IDLE) and no IL(I2t_I) is applied. The current consumption is specified with IGND(I2t_D) (measured at GND pin because the current at VS pin includes the load current). Overcurrent, overtemperature and overvoltage protections are active. Additionally, the sequential diagnosis is enabled and depending on the address the selected setting is present at the IS pin (for further information see Figure 42).

6.1.9 CLS mode

The device has a capacitive load switching (CLS) mode implemented to charge capacitive loads. To enter the CLS mode an input frequency of fVIN(CLS) with the duty cycle of DCVIN(CLS) has to be applied at the input pin (for more details see Chapter 7.2.3). The device current consumption in CLS mode is specified by the parameter IGND(I2t_D).

6.1.10 CLS with diagnosis mode

The CLS with diagnosis mode is entered as soon as the pwm signal for CLS mode (fVIN(CLS) and DCVIN(CLS)) is applied at the IN pin and the DEN pin is set to "high" . The device calculates the I2t status SI2t (with IL=0 A). Overcurrent, overtemperature and overvoltage protections are active. Additionally, the sequential diagnosis is enabled. Depending on the address several settings are present at the IS pin (for further information see Figure 42). The device current consumption is specified by the parameter IGND(I2t_D).

6.1.11 Inactive mode

The inactive mode is a transition mode between I2t mode to sleep mode or idle mode to sleep mode. The device enters inactive mode as soon as the IN pin is set to “low” while the DEN pin is “low” . The device stays in this mode until the I2t status calculation has reached a value below the I2t hysteresis curve. The channel is OFF and the current consumption is specified by the parameter IGND(I2t_D).

6.1.12 Fault mode

The device is in fault mode as soon as a device protection or I2t protection event happen. The output then switches off. In fault mode, with IN="high" and DEN="high" , IIS(FAUL T) is present and no sequential diagnosis is available at the IS pin. With IN = "low" and DEN = "high" sequential diagnosis is available (for details see Chapter 10) at the IS pin. BTG70020A-1ESW Datasheet Datasheet 25 Rev. 1.00 2023-12-07

6.2 Undervoltage on VS

The undervoltage mechanism is triggered below VS(UV) or VS(UV_IDLE). If the device is operative (in I2t mode, I2t with diagnosis mode, CLS mode, CLS with diagnosis mode, inactive mode or inactive with diagnosis mode, active with diagnosis mode) and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the output channel and the I2t calculation is reset. The power supply undervoltage shutdown in idle mode is triggered when the supply voltage drops below VS(UV_IDLE) during idle mode, resulting in the switch OFF of the output channel. t V S(OP) V S(UV) V S(HYS) t V OUT V S IN t V S(UV_IDLE) Operation mode I2t IDLE I2tI2tUnsupplied Unsupplied Figure 17 VS undervoltage behavior

6.3 Electrical characteristics power supply

Table 8 Electrical characteristics - power supply TJ = -40°C to +150°C Unless otherwise specified typical values: TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. VS pin Power supply undervoltage shutdown (normal) VS(UV) 2.0 2.4 2.75 V VS decreasing IN = "high" From VDS ≤ 0.5 V to VDS = VS PRQ-186 Power supply undervoltage shutdown in idle VS(UV_IDLE) 2.3 2.6 2.9 V VS decreasing Idle mode IN = "high" From VDS ≤ 0.5 V to VDS = VS PRQ-1434 (table continues...) BTG70020A-1ESW Datasheet Datasheet 26 Rev. 1.00 2023-12-07

Table 8 (continued) Electrical characteristics - power supply TJ = -40°C to +150°C Unless otherwise specified typical values: TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Power supply minimum operating voltage VS(OP) 2.2 3.1 4.1 V VS increasing IN = "high" From VDS = VS to VDS ≤ 0.5 V PRQ-188 Power supply undervoltage shutdown hysteresis VS(HYS) – 0.75 – V 1) VS(OP) - VS(UV) PRQ-190 1) Not subject to production test - specified by design.

6.3.1 Electrical characteristics - power supply

VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Transition times Transition time for fast transition tT(F10u) – 15 25 µs 1) PRQ-1377 Transition time cls mode to I2t mode tT(CLS_I2t) – 40 80 µs 1) PRQ-1376 Transition time idle mode to I2t mode tT(IDLE_I2t) 9 15.5 24 µs 1) PRQ-1378 Transition time active with diagnosis mode to idle mode tT(AWD_IDLE) 210 280 350 µs 1) PRQ-1379 Transition time I2t mode to cls mode tT(I2t_CLS) 30 70 140 µs 1) PRQ-1380 Transition time inactive with diagnosis mode to sleep mode tT(iwd_slp) 150 210 300 μs 1) PRQ-1410 (table continues...) BTG70020A-1ESW Datasheet Datasheet 27 Rev. 1.00 2023-12-07

Table 9 (continued) Power supply VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Current consumption Supply current consumption in sleep mode with loads at T J ≤ 85°C IVS(SLEEP)_85 – 0.1 1.3 μA 1) VS = 20 V VOUT = VI2t = VOCT = 0 V IN = DEN = “low” TJ ≤ 85°C PRQ-1129 Supply current consumption in sleep mode with loads at T J = 150°C IVS(SLEEP)_150 – 1.5 38 μA VS = 20 V VOUT = VI2t = VOCT = 0 V IN = DEN = “low” TJ = 150°C PRQ-1130 Operating current in inactive with diagnosis mode IGND(INACT_D) – 1.5 2.3 mA VS = 20 V IN = “low” DEN = “high” PRQ-197 Operating current in I2t with diagnosis mode (channel ON) IGND(I2t_D) – 5 7.4 mA VS = 20 V IN = DEN = “high” PRQ-195 Operating current in idle mode (channel ON) IGND(IDLE) – 50 60 μA VS = 20 V IN = "high" DEN = "low" IL < IL(IDLE) PRQ-355 Idle currents Load current hysteresis for idle mode entry IL(IDLE_HYST) – 0.055 – A 1) See Chapter 6.1.7 PRQ-1461 Load current threshold for idle mode exit IL(IDLE) 1.6 4.3 7 A See Chapter 6.1.7 PRQ-1132 1) Not subject to production test - specified by design. BTG70020A-1ESW Datasheet Datasheet 28 Rev. 1.00 2023-12-07

7 Power stages

The high-side power stage is built using an N-channel vertical power MOSFET with charge pump.

7.1 Output ON-state resistance

The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 18 shows the variation of RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured at TJ = 150°C. Figure 18 RDS(ON) variation factor The behavior in reverse polarity is described in Chapter 8.4.1.

7.2 Switching loads

7.2.1 Switching resistive loads

When switching resistive loads, the switching times and slew rates shown in Figure 19 can be considered. The switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF. BTG70020A-1ESW Datasheet Datasheet 29 Rev. 1.00 2023-12-07

VDI(TH) (dV/dt)ON VDI(HYS) PDMOS t t EON EOFF tON tON(DELAY) tOFF(DELAY) tOFF 90% of VS 70% of VS 30% of VS 10% of VS (dV/dt)OFF 70% of VS 30% of VS Figure 19 Switching a resistive load

7.2.2 Switching inductive loads

When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential because the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative output voltage so that VDS = VDS(CLAMP). Figure 20 shows a concept drawing of the implementation. The clamping structure is available in all operation modes listed in Chapter 6.1. All clamping structures (VIS(CLAMP), VS(CLAMP), VDS(CLAMP)) are implemented with respect to VS supply. VS GND V S(CLAMP) V SIS(CLAMP) IS R G N D R S E N S E V S V DS I L V OUT I L R L High - side channel V DS(CLAMP) OUT Figure 20 Output clamp concept During demagnetization of inductive loads, energy has to be dissipated in the device. The energy can be calculated using: E = VDS(CLAMP) · VS − VDS(CLAMP) RL

• ln 1 − RL · IL VS − VDS(CLAMP) + IL · L RL (1) BTG70020A-1ESW Datasheet

Datasheet 30 Rev. 1.00 2023-12-07

The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design of the component. Please refer to Table 3 for the maximum allowed values of EAS (single pulse energy) and EAR (repetitive energy).

7.2.3 Capacitive load switching

When switching a resistive load with the capacitive load switching (CLS) mode the switching times as well as the slew rate will change to tON_CLS, tON_CLS(DELAY), (dV/dt)ON_CLS as shown in Figure 21. The CLS mode is entered by applying a PWM signal at the IN pin with a frequency of fVIN(CLS) and a duty cycle of DCVIN(CLS). IN t VOUT VDI(TH) (d V/dt)ON_CLS VDI(HYS) t tON_CLS 90% of VS tON_CLS(DELAY) tCLS t nACT nCLS_ACT = 1 fVIN(CLS) 70% of VS 30% of VS 10% of VS Figure 21 Capacitive load switching timings During this mode the dynamic thermal shut down temperature is reduced to TJ_CLS(DYN) and the device is set to auto- restart. The CLS mode and CLS with diagnosis mode has to be left after a maximum time of tCLS by setting the input to "high" or "low" state. The highest configurable overcurrent detection threshold IL(HOCT) (for IOCT = 50 µA) is enabled and the overtemperature protections are active (see Figure 29). The device calculates the I2t status SI2t (with IL= 0 A). BTG70020A-1ESW Datasheet Datasheet 31 Rev. 1.00 2023-12-07

t t IL t nCLS_ACT = 1 tCLS nACT t VOUT t Operation mode VDS(OLOFF) I2tCLS t IL(HOCT) IL(OCT) Figure 22 Capacitive load switching activations A transition from the CLS mode to the ON mode is automatically done when VDS < VDS(OLOFF). Before changing from CLS mode (IN = ”pwm”) to I2t mode (IN = ”high”), it must be ensured that there is no short circuit at the output. To distinguish between short circuit and normal load, a current sense measurement must be performed before leaving CLS mode. If the current measurement delivers an expected value, the transition from CLS mode to normal mode is possible. If the current measurement delivers an open load value (no output current), it has to be assumed that there is either an open load or a short circuit at the output. Additionally, a short circuit condition can be excluded by an external voltage measurement at the output.

7.3 Advanced switching characteristics

7.3.1 Inverse current behavior

If VOUT > VS, a current IL(INV) flows into the power output transistor (see Figure 23). This condition is known as “inverse current” . If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses. Therefore, the overall device temperature increases. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output stage is comparable to normal operation in RDS(ON). During Inverse ON condition, the channel remains in ON or OFF state as long as |-IL| < |-IL(INV)|. It is possible to switch ON the channel during inverse current condition as long as |-IL| < |-IL(INV)| (see Figure 24). BTG70020A-1ESW Datasheet Datasheet 32 Rev. 1.00 2023-12-07

Comp. GND OUT V S V S -I L V OUT > V S R G N D Figure 23 Inverse current circuitry OFF OFF CASE 2 : Switch is OFFIN t IL t DMOS state t INVERSE NORMALNORMAL ON INVERSE NORMAL IL t DMOS state t ON CASE 1 : Switch is ONIN t NORMAL OFF ON CASE 4 : Switch OFF into inverse c urrent IN t IL t DMOS state t INVERSE NORMALNORMAL ON INVERSE NORMAL IL t DMOS state t OFF CASE 3 : Switch ON into i n verse c urrent IN t NORMAL OFF ON ON OFF Figure 24 Inverse ON - channel behavior in case of applied inverse current BTG70020A-1ESW Datasheet Datasheet 33 Rev. 1.00 2023-12-07

No protection mechanism like overtemperature or overcurrent protection is active during applied inverse currents.

7.4 Electrical characteristics power stages

Table 10 Electrical characteristics power stages VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Voltages Drain to source clamping voltage at T J = -40°C VDS(CLAMP)_-40 33 36.5 42 V IL = 5 mA TJ = -40°C See Figure 20 PRQ-203 Drain to source clamping voltage at T J ≥ 25°C VDS(CLAMP)_25 35 38 44 V 1) IL = 5 mA TJ ≥ 25°C See Figure 20 PRQ-204 Timings Switch-ON delay tON(DELAY) 10 50 90 μs VS = 13.5 V VOUT = 10% VS See Figure 19 PRQ-205 Switch-ON delay in CLS tON_CLS(DELAY) 150 500 850 µs VS = 13.5 V VOUT = 10% VS See Figure 21 PRQ-591 Switch-OFF delay tOFF(DELAY) 10 75 140 μs VS = 13.5 V VOUT = 90% VS See Figure 19 PRQ-206 Switch-ON time tON 40 100 160 μs VS = 13.5 V VOUT = 90% VS See Figure 19 PRQ-207 Switch-ON time in CLS tON_CLS 350 1075 1800 µs VS = 13.5 V VOUT = 90% VS See Figure 21 PRQ-592 Switch-OFF time tOFF 50 120 190 μs VS = 13.5 V VOUT = 10% VS See Figure 19 PRQ-208 Switch-ON/OFF matching (tON - tOFF) ΔtSW -90 -20 50 μs VS = 13.5 V PRQ-209 (table continues...) BTG70020A-1ESW Datasheet Datasheet 34 Rev. 1.00 2023-12-07

Table 10 (continued) Electrical characteristics power stages VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Input frequency for capacitive load switching mode fVIN(CLS) 22 30 38 kHz 2) DCVIN(CLS) = 50% PRQ-588 Duty cycle for capacitive load switching DCVIN(CLS) 30% 50% 70% – 2) fVIN(CLS) = 30 kHz PRQ-589 Voltage slope Switch-ON slew rate (dV/dt)ON 0.16 0.27 0.39 V/μs VS = 13.5 V VOUT = 30% VS to 70% VS See Figure 19 PRQ-210 Switch-ON slew rate in CLS (dV/dt)ON_CLS 0.012 0.023 0.037 V/µs VS = 13.5 V VOUT = 30% VS to 70% VS See Figure 21 PRQ-590 Switch-OFF slew rate (dV/dt)OFF -0.39 -0.27 -0.16 V/μs VS = 13.5 V VOUT = 70% VS to 30% VS See Figure 19 PRQ-211 Slew rate matching (dV/dt)ON - (dV/dt)OFF Δ(dV/dt)SW -0.15 0 0.15 V/μs VS = 13.5 V PRQ-212 CLS Maximum time in CLS mode tCLS – – 100 ms 2) See Figure 21 PRQ-872 Maximum number of CLS mode activations nCLS_ACT – – 50 kcycles 2) See Figure 21 PRQ-873 Thermal shut down temperature in CLS (dynamic) TJ_CLS(DYN) – 20 – K 2) PRQ-874 Output characteristics ON-state resistance at T J = 25°C RDS(ON)_25 – 2.2 – mΩ 2) TJ = 25°C PRQ-1133 ON-state resistance at T J = 150°C RDS(ON)_150 – – 4.1 mΩ TJ = 150°C PRQ-1134 ON-state resistance in cranking RDS(ON)_CRANK – – 4.7 mΩ TJ = 150°C VS = 3.1 V PRQ-1135 (table continues...) BTG70020A-1ESW Datasheet Datasheet 35 Rev. 1.00 2023-12-07

Table 10 (continued) Electrical characteristics power stages VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. ON-state resistance in idle mode at T J = 150°C RDS(ON)_IDLE – 4.7 – mΩ TJ = 150°C PRQ-1136 ON-state resistance in inverse current at T J = 25°C RDS(INV)_25 – 2.3 – mΩ 2) TJ = 25°C VS = 13.5 V IL = -10 A DEN = “low” See Figure 24 PRQ-1137 ON-state resistance in inverse current at T J = 150°C RDS(INV)_150 – – 4.7 mΩ TJ = 150°C VS = 13.5 V IL = -10 A DEN = “low” See Figure 24 PRQ-1138 ON-state resistance in reverse polarity at T J = 25°C RDS(REV)_25 – 4.7 – mΩ 2) TJ = 25°C VS = -13.5 V IL = -10 A See Figure 34 PRQ-1139 ON-state resistance in reverse polarity at T J = 150°C RDS(REV)_150 – – 6.3 mΩ 2) TJ = 150°C VS = -13.5 V IL = -10 A PRQ-1140 Nominal load current IL(NOM)_85 – 21.5 – A 2) TA = 85°C TJ ≤ 150°C PRQ-1141 Output leakage current at T J ≤ 85°C IL(OFF)_85 – 0.1 1.3 μA 2) VOUT = 0 V VIN = "low" TJ ≤ 85°C PRQ-1142 Output leakage current at T J = 150°C IL(OFF)_150 – – 38 μA VOUT = 0 V VIN = "low" TJ = 150°C PRQ-1143 (table continues...) BTG70020A-1ESW Datasheet Datasheet 36 Rev. 1.00 2023-12-07

Table 10 (continued) Electrical characteristics power stages VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Inverse current capability IL(INV) – -21.5 – A 2) VS < VOUT IN = "high" See Figure 24 PRQ-1144 Voltages Drain source diode voltage |VDS(DIODE)| – 550 700 mV IL = -190 mA TJ = 150°C PRQ-224 Switching energy Switch-ON energy EON – 1.5 – mJ 2) VS = 20 V See Figure 19 PRQ-225 Switch-OFF energy EOFF – 1.65 – mJ 2) VS = 20 V See Figure 19 PRQ-226 1) Tested at TJ = 150°C. 2) Not subject to production test - specified by design. BTG70020A-1ESW Datasheet Datasheet 37 Rev. 1.00 2023-12-07

8 Device protection

The device is protected against overtemperature, overcurrent, reverse battery (with Reverse ON) and overvoltage. Overtemperature and overcurrent protections are disabled when the device is in sleep mode. When the device is in idle mode the overtemperature protection is disabled and the overcurrent protection is enabled. Overtemperature and overcurrent protections are not active during inverse current and in reverse battery condition. Overvoltage protection works in all operation modes. Reverse battery protection works when the GND and VS pins are reverse supplied.

8.1 Overtemperature protection

The device incorporates an absolute (TJ(ABS)) as well as a dynamic (TJ(DYN)) temperature protection circuitry for the channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)) switches OFF the overheated channel to prevent destruction. The channel remains switched OFF until the junction temperature has reached the “reactivation” condition and a reset was applied as described in Table 11. The behavior is shown in Figure 25 and Figure 26. TJ(REF) is the reference temperature used for dynamic temperature protection. IL t T J DEN Internal latch t t t t IN t IL(NOM) IL(OCT) T J(ABS) IIS IIS = I L /k ILIS IIS(FAUL T) Figure 25 Overtemperature protection (absolute) BTG70020A-1ESW Datasheet Datasheet 38 Rev. 1.00 2023-12-07

t T DEN Internal latch t t t t IN t IL(OCT) T J(ABS) IIS IIS = I L /k ILIS IIS(FAUL T) T J(DYN) T J T J(REF) Figure 26 Overtemperature protection (dynamic) When the overtemperature protection circuitry allows the channel to be switched ON again, the intelligent latch strategy described in Chapter 8.3 is followed.

8.2 Overcurrent threshold protection

The device is protected in case of overload or short circuit to ground by the overcurrent protection IL(OCT). Furthermore, the overcurrent threshold IL(OCT) can be adjusted from the lowest configurable overcurrent detection threshold IL(LOCT) to the highest configurable overcurrent detection threshold IL(HOCT) by connecting a resistor between the OCT pin and the GND pin of the device. The adjustment of the overcurrent threshold (without considering the VDS reduction) could be done according to formula: IL OCT _TJ A = IOCT μA − 7 . 5 μA · kOCT A/μA + IL LOCT _ −40 A · TJ °C + 40 °C · kTJ · 10−3 + 1 (2) BTG70020A-1ESW Datasheet Datasheet 39 Rev. 1.00 2023-12-07

To select the proper resistor value ROCT connected between the OCT pin and device ground, the following equation can be considered: IOCT = VOCT ROCT (3) I OCT I L IOCT_SHORT I L(LOCT) I L(HOCT) IOCT_MAXIOCT_MIN IOCT_OPEN Figure 27 Overcurrent threshold adjustment by IOCT In case of an open or short detection of the OCT adjustment current IOCT at the pin the device changes to the highest configurable overcurrent detection threshold IL(HOCT). The overcurrent thresholds are depending on the voltage VDS across the power DMOS. If an overcurrent threshold adjustment current IOCT < 30 µA (Typical value) is selected no reduction of the IL(OCT) over VDS takes place (see Figure 28). I L(xOCT) variation factor V DS(LOCT) V DS 1.0 0.7 I L(xOCT) with I OCT = 50µA I L(xOCT) with I OCT = 40µA I L(xOCT) with I OCT = 25µA V DS(HOCT) 0.8 0.5 Figure 28 Adjustable overcurrent threshold variation with VDS In order to allow a higher load inrush current at low ambient temperature, the overcurrent threshold is maximum at low temperature and decreases when TJ increases (see Figure 29). Overcurrent detection threshold decreases linearly with increasing temperature. BTG70020A-1ESW Datasheet Datasheet 40 Rev. 1.00 2023-12-07

I L(OCT) variation factor 1.0 I L(OCT) with I OCT = 50µA I L(OCT) with I OCT = 45µA I L(OCT) with I OCT = 30µA 0.9 0.6 T J Figure 29 Adjustable overcurrent threshold variation with TJ Power supply voltage VS can increase above 18 V for short time, for instance in load dump or in jump start condition. Whenever VS ≥ VS(JS) during switch ON, the overcurrent detection current is set to IL(OCT_JS). If an overcurrent threshold adjustment current IOCT < 30 µA (Typical value) is selected no reduction of the IL(OCT) with VS takes place (see Figure 30). V S I L(OCT_JS) 1.0 0.8 0.5 V S(JS) I L(OCT) variation factor 0.7 I L(OCT) with I OCT = 50µA I L(OCT) with I OCT = 40µA I L(OCT) with I OCT = 25µA Figure 30 Adjustable overcurrent with VS voltage When IL ≥ IL(OCT) the channel is switched OFF. The channel is allowed to be reactivated according to the intelligent latch strategy described in Chapter 8.3. BTG70020A-1ESW Datasheet Datasheet 41 Rev. 1.00 2023-12-07

8.3 Device protection and diagnosis in case of fault

Any fault event (either overtemperature or overcurrent) that triggers a device protection mechanism has two consequences:

• The channel switches OFF and remains latched OFF (internal latch set to "1")
• If the sequential diagnosis is active for the channel, the current IIS(FAUL T) is provided in case of IN = "high" (see Chapter 10.1.1) and for IN = "low" the current IIS(DEVOFF) is provided at address #1 (see Chapter 10.1.2 for further details) The channel can be switched ON again if all the protection mechanisms fulfill the "reactivation" conditions described in Table 11 and a reset by DEN or IN was applied. Furthermore, the device has the intelligent latch to protect itself against unwanted repetitive reactivation in fault condition. Table 11 Protection "reactivation" condition Fault condition Switch OFF event “Reactivation” condition Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN) TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN) (including hysteresis)Overcurrent IL ≥ IL(OCT)

8.3.1 Intelligent latch reset strategy after device protection triggered

In normal condition, when IN is set to “high” , the channel is switched ON. In case the device protection is triggered, the output stage is switched OFF. It remains OFF until the channel is reset. There are two ways to reset the channel: With IN pin: By setting the input pin to “low” for a time longer than tDELAY(LR) (“latch reset delay” time), the channel is reset if the “reactivation” conditions for the protection mechanisms are fulfilled (see Table 11). If the input is set to “high” during the “latch reset delay” time the channel remains switched OFF and the timer tDELAY(LR) is reset. The timer tDELAY(LR) restarts as soon as the input pin is set to “low” again. With DEN pin: It is possible to “force” a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge followed by a falling edge) to the DEN pin while IN pin is “low” . The pulse applied to DEN pin must have a duration longer than tDEN(LR) to ensure a reset of the internal latch. Intelligent latch reset strategy after device protection triggered is shown in Figure 31, Figure 32 and Figure 33. t IN IL t t DEN t IIS IIS(FAUL T) IIS(FAUL T) t Short circuit to ground Internal latch t 0 10 t DELAY(LR) tsIS(DIAG) t ON Figure 31 Intelligent latch timing diagram for IN reset in case of triggered device protection BTG70020A-1ESW Datasheet Datasheet 42 Rev. 1.00 2023-12-07

t IN I L t t DEN t I IS I IS(FAUL T) I IS(FAUL T) I IS(FAUL T) t Short circuit to ground Internal latch t t sIS(DIAG) t < t DEN(LR) t > t DEN(LR) 0 110 t sIS(DIAG) t sIS(DIAG) Figure 32 Intelligent latch timing diagram for DEN reset in case of triggered device protection BTG70020A-1ESW Datasheet Datasheet 43 Rev. 1.00 2023-12-07

Latch = 1 Yes Reactivation condition fulfilled ( TJ and/or Δ T/ and/or overload) No Yes Switch channel ON Fault (overtemperature or overload) No Yes Switch channel OFF Latch = 1 Wait until IN is low then start counting for t DELAY(LR) Yes IN is low De - latching with DEN Yes Continue latching for t DELAY(LR) No tDELAY(LR) elapsed Latch = 0 Yes No No Latch = 0 DEN pulse > t DEN(LR) Yes Wait until DEN pulse > t DEN(LR) Set DEN to high No Yes Figure 33 Intelligent latch flowchart in case of triggered device protection BTG70020A-1ESW Datasheet Datasheet 44 Rev. 1.00 2023-12-07

8.4 Additional protections

8.4.1 Reverse polarity protection

In reverse polarity condition (also known as reverse battery), the output stage is switched ON (see parameter RDS(REV)) because of the Reverse ON feature, which limits the power dissipation in the output stage. Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output stage must be limited by the connected load. The current through digital input pins has to be limited as well by an external resistor (please refer to the absolute maximum ratings listed in Table 2 and to application information in Chapter 11). Figure 34 shows a typical application including a device with Reverse ON. A current flowing into GND pin (-IGND) during reverse polarity condition is necessary to activate Reverse ON, therefore a resistive path between module ground and device GND pin must be present. Reverse ON OUT VS AI DO DI High -side channel IS GND RDI RDO IDI IDO R A I IA I R S E N S E R G N D -I IS - IGND L, C, R -IL Microcontroller DO DI GND -VBAT(REV) Figure 34 Reverse battery protection (application example)

8.4.2 Overvoltage protection

In case of supply voltages between VS(EXT ,UP) and VBAT(LD), the output transistor is still operational and follows the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there is a clamp mechanism available for overvoltage protection for the logic circuit and the output channels, monitoring the voltage between VS and GND pins (VS(CLAMP)).

8.5 Protection against loss of connection

8.5.1 Loss of battery and loss of load

The loss of connection to battery or load has no influence on device robustness when load and wire harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be handled. PROFET™ Wire Guard devices handle the inductivity of the wire harness up to 10 µH with IL(NOM)_85. In case of applications where currents and / or the aforementioned inductivity are exceeded, an external suppressor diode (like diode DZ2 shown in Chapter 11) is recommended to handle the energy and to provide a well-defined path to the load current. BTG70020A-1ESW Datasheet Datasheet 45 Rev. 1.00 2023-12-07

8.5.2 Loss of ground

In case of loss of device ground, it is recommended to have a resistor connected between any digital input pin and the microcontroller to ensure a channel switch OFF (as described in Chapter 11). Note: In case that any digital input pin is pulled to ground (either by a resistor or active) a parasitic ground path is available, which could keep the device operational during loss of device ground.

8.6 Electrical characteristics device protection

Table 12 Electrical characteristics device protection VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Thermal Thermal shutdown temperature (absolute) TJ(ABS) 150 175 200 °C 1) 2) See Figure 25 PRQ-246 Thermal shutdown hysteresis (absolute) THYS(ABS) – 30 – K 3) PRQ-247 Thermal shutdown temperature (dynamic) TJ(DYN) – 80 – K 3) See Figure 26 PRQ-248 Voltages Power supply clamping voltage at T J = -40°C VS(CLAMP)_-40 33 36.5 42 V IVS = 10 mA TJ = -40°C See Figure 20 PRQ-251 Power supply clamping voltage at T J ≥ 25°C VS(CLAMP)_25 35 38 44 V 2) IVS = 10 mA TJ ≥ 25°C See Figure 20 PRQ-252 Low level of overcurrent threshold depending on drain source voltage VDS(LOCT) 13.5 15.0 16.5 V 3) PRQ-1248 High level of overcurrent threshold depending on drain source voltage VDS(HOCT) 18 20 22 V 3) PRQ-1249 (table continues...) BTG70020A-1ESW Datasheet Datasheet 46 Rev. 1.00 2023-12-07

Table 12 (continued) Electrical characteristics device protection VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Power supply voltage threshold for overcurrent threshold reduction in case of short circuit VS(JS) 20.5 22.5 24.5 V 3) Setup acc. to AEC- Q100-012 PRQ-253 Timings Latch reset delay time after fault condition tDELAY(LR) 40 70 100 ms 1) See Figure 31 PRQ-254 Minimum DEN pulse duration for latch reset tDEN(LR) 50 100 150 μs 3) See Figure 32 PRQ-255 1) Functional test only. 2) Tested at TJ = 150°C only. 3) Not subject to production test - specified by design. Table 13 Electrical characteristics protection - power output stages VS = 5 V to 20 V, TJ = -40 °C to +150 °C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Highest configurable overcurrent detection threshold at T J = -40°C IL(HOCT)_-40 142 168 193 A 1) TJ = -40°C dI/dt = 0.4 A/µs IOCT = 50 µA PRQ-1145 Highest configurable overcurrent detection threshold at T J = 25°C IL(HOCT)_25 129 151.5 174 A 1) 2) TJ = 25°C dI/dt = 0.4 A/µs IOCT = 50 µA PRQ-1146 Highest configurable overcurrent detection threshold at T J = 150°C IL(HOCT)_150 108 125 142 A 1) 2) TJ = 150°C dI/dt = 0.4 A/µs IOCT = 50 µA PRQ-1147 (table continues...) BTG70020A-1ESW Datasheet Datasheet 47 Rev. 1.00 2023-12-07

Table 13 (continued) Electrical characteristics protection - power output stages VS = 5 V to 20 V, TJ = -40 °C to +150 °C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Overcurrent detection at high VDS IL(OCT_VDS) – 94 – A 1) 2) IOCT = 50 µA VDS > VDS(HOCT) See Figure 28 PRQ-1148 Overcurrent detection - jump start condition IL(OCT_JS) – 94 – A 1) 2) VS > VS(JS) IOCT = 50 µA See Figure 30 PRQ-1149 Lowest configurable overcurrent detection threshold IL(LOCT)_-40 15 27.5 40 A 1) TJ = -40°C dI/dt = 0.15 A/µs IOCT = 7.5 µA PRQ-1151 Overcurrent threshold ratio at T J = -40°C TJ = -40°C PRQ-1319 OCT current threshold for short detection IOCT_SHORT 83.3 – – µA – PRQ-885 OCT adjustment current IOCT 7.2 – 52.6 µA – PRQ-599 OCT current threshold for open detection IOCT_OPEN – – 3.8 µA – PRQ-886 Overcurrent threshold temperature coefficient kT J – -1.347 – – 2) PRQ-1500 1) Functional test only. 2) Not subject to production test - specified by design. BTG70020A-1ESW Datasheet Datasheet 48 Rev. 1.00 2023-12-07

9 System protection

9.1 I2t protection

The integrated I2t protection supports the protection of the system including the wire harness and the PCB traces. The I2t protection function is active in I2t mode and I2t with diagnosis mode. While the I2t status calculation (with IL = 0 A) is as well present in Inactive mode, Inactive with diagnosis mode, CLS mode and CLS with diagnosis mode. The I2t protection feature calculates an I2t status SI2t, which is based on the load current IL, the time constant of all I2t protection curves τI2t and the dedicated IDC of the I2t protection curve IL(I2t_x). The channel is switched off as soon as the I2t status SI2t calculation reaches 100% (see Figure 35). Operation mode t I2t SleepFaultSleepI2t t IN I L t tI2t_x_RESET t 100% S I2t_x I L(I2t_x) tI2t_x_TRIG t > tDELAY(LR) Inactive S I2t_I S I2t_HYST S I2t_A Figure 35 I2t protection timing When the power stage is switched off due to an I2t protection event, the channel is latched off and the I2t status is further calculated with IL = 0 A. The dedicated trigger time of the I2t protection curve depends on the actual I2t status SI2t_A and can be calculated for constant load currents by: tI2t_x_TRIG = ∞ for IL ≤ IL I2t_x τI2t · ln IL 2 − IL I2t_x 2 · SI2t_A IL 2 − IL I2t_x 2 for constant IL > IL I2t_x (4) The steady state value of the actual I2t status SI2t_A can be calculated with the actual steady state current IL_A by: SI2t_A = IL_A IL_ I2t_x 2 (5) The initial value of the I2t status calculation depends on the mode transition and the actual I2t status SI2t_A. In case the I2t status calculation is resumed from a value lower than the initial status SI2t_I minus the I2t status hysteresis SI2t_HYST (for instance the I2t mode is entered for the first time) the I2t calculation is pre-loaded with the initial status value SI2t_I. In case the I2t status calculation is resumed from a value higher than the initial status SI2t_I minus the I2t status hysteresis SI2t_HYST, the I2t status SI2t calculation will be resumed from the actual I2t status SI2t_A. The initial status value SI2t_I is preloaded for the following transition conditions slp_i2t, slp_iwd, idle_i2t, idle_ina, awd_i2twd and awd_iwd (see Figure 16). In all other transition conditions, the I2t status calculation is resumed from the actual SI2t_A value. BTG70020A-1ESW Datasheet Datasheet 49 Rev. 1.00 2023-12-07

In case the actual I2t status SI2t_A is preloaded by the initial I2t status SI2t_I it has to be replaced in equation 3 (dedicated trigger time of the I2t protection curve) by the initial I2t status SI2t_I which can be calculated by: SI2t_I = IL I2t_I IL_ I2t_x 2 (6) To enter sleep mode after the I2t protection feature was triggered the I2t status calculation has to be below the initial status SI2t_I minus the I2t status hysteresis SI2t_HYST (see Figure 35). This transition time tI2t_x_RESET is given by the following formula (assuming IL= 0 A): tI2t_x_RESET = τI2t · ln IL I2t_x IL I2t_I − IL I2t_HYST 2 (7) As the ambient temperature and the PCB layout influences the thermal behavior of the device, the overtemperature protection might be triggered before tI2t_x_TRIG is reached (see Figure 36) ). Therefore, the maximum time for a given current is potentially limited by the thermal design of the component. For more information, refer to Table 5. The device has six different I2t protection curves IL(I2t_x) implemented (see Figure 36). The I2t protection curves IL(I2t_x) can be selected by placing the corresponding selection resistor RI2t_x. The resistor must be connected between the I2t pin and the ground pin of the device. See Table 14 for detailed information. In case of an open or short of the selection resistor the device selects the I2t protection curve 1. tI2t _x _ TRIG I L(I2t_ 6 ) t IL I2t protection curve 1 I2t protection curve 2 I2t protection curve 3 I2t protection curve 4 I2t protection curve 5 I2t protection curve 6 Thermal device protection Figure 36 Energy graph of I2t protection curves Note: This is a very simplified overview of the implemented system protection function. For detailed trigger behavior, refer to Table 14. The synchronization time tSYNC(RI2t) for I2t programming resistor setting is a time at which the device internally updates the I2t protection curve setting. During inverse current operation the I2t calculation assumes no load current flowing. In reverse battery condition the I2t calculation is reset and disabled. BTG70020A-1ESW Datasheet Datasheet 50 Rev. 1.00 2023-12-07

9.1.1 I2t protection and idle mode

In idle mode as well as in active with diagnosis mode, the I2t protection calculation is disabled. To change from I2t mode to idle mode the idle mode entry conditions have to be fulfilled (see Chapter 6.1.7). The minimum transition time from I2t mode to idle mode for IL = 0 A could be calculated by: tT I2t_IDLE = τI2t · ln IL I2t_I IL I2t_I − IL I2t_HYST 2 (8) When the device changes from idle mode into I2t mode, I2t with diagnosis mode (over active with diagnosis mode) and inactive mode, the initial value of the I2t status calculation becomes again pre-loaded with the initial current for I2t protection value IL(I2t_I) (see Figure 37). t IN I L t t S I2t IL(IDLE) t T(I2t_IDLE) Operation mode t I2t SleepIdle I2t Idle Inactive S I2t_I S I2t_HYST Figure 37 Idle mode timing

9.1.2 Intelligent latch reset strategy after I2t protection triggered

Any fault event that triggers the I2t protection mechanism has the following consequences:

• The channel switches OFF and remains latched OFF (internal latch set to "1")
• The calculation of I2t protection curve will be continued
• If the diagnosis is active for the channel, depending on the sequential diagnosis address and IN status, different IIS currents are provided at the IS pin (for further details see Figure 44) - Address #1 & IN = "high" - the IIS(FAUL T) current is provided showing that the channel is switched OFF - Address #1 & IN = "low" - the IIS(I2tOFF) current is provided showing that the channel is switched OFF due to triggered I2t protection - Address #2 - #5 & IN = "low" - the IIS currents are provided as described in Figure 44 The intelligent latch can be reset by IN or DEN at any time of the I2t status calculation. After the reset the channel can be switched ON again and the I2t status will be further calculated. With IN pin: By setting the input pin to “low” for a time longer than tDELAY(LR) (“latch reset delay” time) the channel is reset. If the input is set to “high” during the “latch reset delay” time, the channel remains switched OFF and the timer tDELAY(LR) is reset. The timer tDELAY(LR) restarts as soon as the input pin is set to “low” again (see Figure 38). BTG70020A-1ESW Datasheet

Datasheet 51 Rev. 1.00 2023-12-07

t IN I L t t DEN t I IS I IS(FAUL T) I IS(FAUL T) Internal latch t 0 10 t DELAY(LR) S I2t 100% I S = I L / k ILIS I IS(I2tOFF) I S = I L / k ILIS t Figure 38 Intelligent latch timing diagram for IN reset in case of triggered I2t protection With DEN pin: It is possible to “force” a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge followed by a falling edge) to the DEN pin while IN pin is “low” . The pulse applied to DEN pin must have a duration longer than tDEN(LR) to ensure a reset of the internal latch (see Figure 39). t IN I L t t DEN t I IS I IS(FAUL T) I IS(FAUL T) Internal latch t 0 10 S I2t 100% I S = I L / k ILIS I IS(I2tOFF) I S = I L / k ILIS t t > t DEN(LR) I IS(I2tOFF) tDEN(SD_AH) = t Figure 39 Intelligent latch timing diagram for DEN reset in case of triggered I2t protection The intelligent latch strategy in case of device protection triggering is shown in Figure 40. BTG70020A-1ESW Datasheet Datasheet 52 Rev. 1.00 2023-12-07

Latch = 1 Yes Yes Switch channel OFF Latch = 1 Wait until IN is low then start counting for t DELAY(LR) Yes IN is low Reset with DEN Yes Continue latching for t DELAY(LR) No t DELAY(LR) elapsed Latch = 0 Yes No No Latch = 0 DEN pulse > t DEN(LR) Yes Wait until DEN pulse > t DEN(LR) Set DEN to high No Yes Switch channel ON No I2t Protection Triggered No Figure 40 Intelligent latch flowchart in case of triggered I2t protection BTG70020A-1ESW Datasheet Datasheet 53 Rev. 1.00 2023-12-07

9.2 Electrical characteristics protection

Table 14 Electrical characteristics I2t protection VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. I2t resistor threshold for short detection RI2t_SHORT – – 6 kΩ 1) PRQ-890 Selection resistor for I2t protection curve 1 RI2t_1 9.31 9.76 10.20 kΩ – PRQ-573 Selection resistor for I2t protection curve 2 RI2t_2 14.06 14.70 15.30 kΩ – PRQ-574 Selection resistor for I2t protection curve 3 RI2t_3 20.74 21.50 22.46 kΩ – PRQ-575 Selection resistor for I2t protection curve 4 RI2t_4 30.91 32.40 33.66 kΩ – PRQ-576 Selection resistor for I2t protection curve 5 RI2t_5 44.39 46.40 48.09 kΩ – PRQ-577 Selection resistor for I2t protection curve 6 RI2t_6 65.38 68.10 70.82 kΩ – PRQ-578 I2t resistor threshold for open detection RI2t_OPEN 130 – – kΩ 1) PRQ-889 Synchronization time of selection resistor for I2t protection curve setting tSYNC(RI2t) 12.8 19.2 25.6 µs 1) PRQ-944 Time constant of all I2t protection curves τI2t 14.0 20.0 26.0 s 1) PRQ-1152 IDC of I2t protection curve 1 IL(I2t_1) 21.5 23.9 26.3 A 1) 2) PRQ-1153 IDC of I2t protection curve 2 IL(I2t_2) 19.4 21.5 23.7 A 1) 2) PRQ-1154 IDC of I2t protection curve 3 IL(I2t_3) 17.4 19.4 21.3 A 1) 2) PRQ-1155 IDC of I2t protection curve 4 IL(I2t_4) 15.7 17.4 19.2 A 1) 2) PRQ-1156 IDC of I2t protection curve 5 IL(I2t_5) 14.1 15.7 17.2 A 1) 2) PRQ-1157 IDC of I2t protection curve 6 IL(I2t_6) 12.7 14.1 15.5 A 1) 2) PRQ-1158 (table continues...) BTG70020A-1ESW Datasheet Datasheet 54 Rev. 1.00 2023-12-07

Table 14 (continued) Electrical characteristics I2t protection VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. IDC of I2t Hysteresis Curve IL(I2t_HYST) 0.24 0.3 0.36 A 1) 2) PRQ-1314 Initial current for I2t protection IL(I2t_I) 4.8 5.5 6.2 A 1) 2) PRQ-1159 Transition times Transition time I2t to idle tT(I2t_IDLE) 1.7 2.24 2.8 s 1) IL < 10 mA PRQ-1131 1) Not subject to production test - specified by design. 2) I2t DC trigger level specified for times longer than 200s. BTG70020A-1ESW Datasheet Datasheet 55 Rev. 1.00 2023-12-07

10 Diagnosis

For diagnosis purposes the device provides a sense current signal (IIS) at IS pin. In case of disabled diagnostics (DEN pin set to “low”), IS pin becomes high impedance. A sense resistor RSENSE must be connected between IS pin and module ground if the diagnosis is used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central reverse battery protection is externally present on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ. Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS pin to the sense current output of other devices if they are supplied by a different battery feed. See Figure 41 for details as an overview. IS p in c ontrol logic Overload p rotection IN DEN Overtemperature p rotection VS IS Output c hannel T I2t OCT I2t p rotection iDAC II S(FAUL T) II S( I2t ) II S( I2t_STATUS ) II S( OCT ) II S( OLOFF ) I IS( KILIS ) I IS( x ) R S E N S E OUT IIS(VER) IIS(KILDIS) Figure 41 Diagnosis block diagram Table 15 gives a reference to the state of the IS pin during the operation of the device. Table 15 SENSE signal, function of application condition Application condition Input level DEN level VOUT Diagnostic input Normal operation and short circuit to GND IIS(DEVOFF), IIS(I2tOFF) if latch ≠ 0 #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS(VER) Overtemperature Z #1: IIS(DEVOFF) (table continues...) BTG70020A-1ESW Datasheet Datasheet 56 Rev. 1.00 2023-12-07

Table 15 (continued) SENSE signal, function of application condition Application condition Input level DEN level VOUT Diagnostic input #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS(VER) Short circuit to VS VS #1: IIS(OLOFF) IIS(DEVOFF), IIS(I2tOFF) if latch ≠ 0 #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS(VER) Open load < VS - VDS(OLOFF)1) #1: Z > VS - VDS(OLOFF)1) #1: IIS(OLOFF) (in both cases IIS(DEVOFF)) IIS(I2tOFF) if latch ≠ 0) #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS(VER) Inverse current ~ VINV = VOUT > VS #1: IIS(OLOFF) IIS(DEVOFF), IIS(I2tOFF) if latch ≠ 0 #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS(VER) Normal operation "high" ~VS #1: IIS = IL / kILIS #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS = IL / kILDIS Overload < VS #1: IIS(FAUL T) Short circuit to GND ∼GND #1: IIS(FAUL T) Overtemperature Z #1: IIS(FAUL T) Short circuit to VS VS #1: IIS < IL / kILIS (table continues...) BTG70020A-1ESW Datasheet Datasheet 57 Rev. 1.00 2023-12-07

Table 15 (continued) SENSE signal, function of application condition Application condition Input level DEN level VOUT Diagnostic input #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS = IL / kILDIS Open load ∼VS2) #1: IIS = IIS(EN) #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS = IIS(EN) Inverse current ~ VINV = VOUT > VS #1: IIS = IIS(EN) #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: IIS = IIS(EN) CLS mode "pwm" "high" < VS - VDS(OLOFF) #1: Z #2: IIS(I2t) #3: IIS(STATUS_I2t) #4: IIS(OCT) #5: Z All conditions n.a. "low" n.a. Z 1) With additional pull-up resistor 2) The output current has to be smaller than IL(OL).

10.1 Sequential diagnosis

In ON and OFF state the device differentiates between the following diagnosis functions: Address IN Function #1 "high" Current sense #1 "low" Open load in OFF #2 "x" I2t setting #3 "x" I2t status #4 "x" OCT setting #5 "high" Digital current sense #5 "low" Sense verification current BTG70020A-1ESW Datasheet Datasheet 58 Rev. 1.00 2023-12-07

To sequentially change to the next diagnosis address (for example, "current sense" to "I2t setting") a pulse at the DEN pin (falling edge followed by a rising edge) has to be applied for a time of tDEN(SD_AC) ("DEN pulse duration for sequential diagnosis address change"). If the pulse is shorter than tDEN(SD_AH) (“DEN pulse duration for sequential diagnosis address hold)” no address change is performed. The timing and modes are shown in Figure 42. After sweeping through the last diagnosis address the device starts again at the first diagnosis address. t DEN Current sense I2t status OCT setting t Address #1 Address #2 Address #3 Address #4 Address #1 IS IN= high I2t setting I2t status OCT setting t IS IN= low I2t setting Open load in OFF Current sense Open load in OFF Digital current sense Address #5 Sense verification current t DEN(SD_AC) t DEN(SD_AC) t DEN(SD_AC) t DEN(SD_AC) t DEN(SD_AC) Figure 42 Sequential diagnosis function If the pulse applied at the DEN pin is "low" for a duration longer than the DEN pulse duration for sequential diagnosis timeout tDEN(SD_TO), the actual diagnosis address is reset (see Figure 43). With the next DEN pin "high" signal the sequential diagnosis starts at the first diagnosis address (depending on the IN pin set to "high" or "low"). t DEN t t < t DEN(SD_AH) t > t DEN(SD_TO) t DEN(SD_AC) I2t status Address # 2 Address # 2 Address #1 Address #2 Address #3 I2t setting IS IN= high I2t setting t IN= low I2t setting I2t status I2t setting I2t setting I2t setting Open load in OFF Current sense IS t DEN(SD_AC) Figure 43 Sequential diagnosis timing The PWM signal (fVIN(CLS) with DCVIN(CLS)) which needs to be applied at the input pin in order to enter the CLS mode will be decoded from the diagnosis as IN equal to "high" . The states as well as the corresponding sense currents of the sequential diagnosis function are depicted in Figure 44. BTG70020A-1ESW Datasheet Datasheet 59 Rev. 1.00 2023-12-07

#1: Current sense k ILIS or I IS(FAUL T) #2: I2t setting IIS(I2t) #1: Open load in OFF IIS(OLOFF) , IIS(DEVOFF) or I IS(I2tOFF) cs_i2tset olio_i2tset octset_dcs octset_isver i2tsta_octset i2tset_i2tsta dcs_cs i2tset_cs i2tset_olio i2tsta_olio octset_olio isver_olio #3: I2t status IIS(STATUS_I2t) #4: OCT setting IIS(OCT) #5: Sense verification current IIS(VER) cs_olio olio_cs dcs_isver isver_dcs #5: Digital current sense k ILDIS octset_cs i2tsta_cs fault 1 1) Address #1 (current sense) locked in case of fault condition Figure 44 Sequential diagnosis modes A more detailed description of the transitions, including the transition conditions and duration times are provided in the following table. Table 16 Transition descriptions Name Start state End state Transition condition Duration time olio_cs Open load in OFF Current sense IN = "high" 1) tsIS(DIAG) i2tset_cs I2t setting Current sense (DEN = "low" for tDEN(SD_TO) OR FAUL T) AND IN = "high" 1) tsIS(ON15) i2tsta_cs I2t status Current sense (DEN = "low" for tDEN(SD_TO) OR FAUL T) AND IN = "high" 1) tsIS(ON15) octset_cs OCT setting Current sense (DEN = "low" for tDEN(SD_TO) OR FAUL T) AND IN = "high" 1) tsIS(ON15) dcs_cs Digital current sense Current sense (DEN = "low" for (tDEN(SD_AC) OR tDEN(SD _TO)) OR FAUL T) AND IN = "high" tsIS(ON15) cs_olio Current sense Open load in OFF IN = "low" tsIS(ON234) i2tset_olio I2t setting Open load in OFF (DEN = "low" for tDEN(SD_TO)) AND IN = "low" tsIS(ON234) (table continues...) BTG70020A-1ESW Datasheet Datasheet 60 Rev. 1.00 2023-12-07

Table 16 (continued) Transition descriptions Name Start state End state Transition condition Duration time i2tsta_olio I2t status Open load in OFF (DEN = "low" for tDEN(SD_TO)) AND IN = "low" tsIS(ON234) octset_olio OCT setting Open load in OFF (DEN = "low" for tDEN(SD_TO)) AND IN = "low" tsIS(ON234) isver_olio Sense verification current Open load in OFF (DEN = "low" for (tDEN(SD_AC) OR tDEN(SD _TO))) AND IN = "low" tsIS(ON234) cs_i2tset Current sense I2t setting DEN = "low" for tDEN(SD_AC) tsIS(ON234) olio_i2tset Open load in OFF I2t setting DEN = "low" for tDEN(SD_AC) tsIS(ON234) i2tset_i2tsta I2t setting I2t status DEN = "low" for tDEN(SD_AC) tsIS(ON234) i2tsta_octset I2t status OCT setting DEN = "low" for tDEN(SD_AC) tsIS(ON234) octset_dcs OCT setting Digital current sense (DEN = "low" for tDEN(SD_AC)) AND IN = "high" 1) tsIS(ON15) isver_dcs Sense verification current Digital current sense IN = "high" 1) tsIS(DIAG) octset_isver OCT setting Sense verification current (DEN = "low" for tDEN(SD_AC)) AND IN = "low" 1) tsIS(ON234) dcs_isver Digital current sense Sense verification current IN = "low" tsIS(ON234) 1) CLS mode with IN = “pwm“ are decoded as IN = “high“

10.1.1 Current sense (address #1 - IN=high)

A current proportional to the load current according to kILIS = IL IIS (9) is provided at IS pin when the following conditions are fulfilled:

• Address #1 and IN = "high"
• The diagnosis (current sense) is enabled with VDS < VDS(OLOFF)
• No fault (as described in Chapter 8.3) is present or was latched (see Figure 46 for further details) A fault current IIS(FAUL T) is provided at the IS pin when a fault is present or was latched. BTG70020A-1ESW Datasheet

Datasheet 61 Rev. 1.00 2023-12-07

The accuracy of the sense current IIS depends on the load current IL. The sense current IIS increases linearly with IL output current until it reaches the saturation current IIS(SAT). In case of open load at the output stage (IL close to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in Figure 45. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical product. An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce the signal ripple and oscillations (a minimum time constant of 1 μs for the RC filter is recommended). The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and manufacturing process. Tighter limits are possible (within a defined current window) with calibration:

• A well-defined and precise current ( IL(CAL)) is applied at the output during end-of-line test at customer side
• The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
• Within the current range going to IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by ΔkILIS The derating of kILIS after calibration is specified by ΔkILIS, calculated using the following formulas: ∆ kILIS, MAX = 100 · MAX kILIS @ IL CAL _L kILIS @ IL CAL − 1, kILIS @ IL CAL _H kILIS @ IL CAL − 1 ∆ kILIS, MIN = 100 · MIN kILIS @ IL CAL _L kILIS @ IL CAL − 1, kILIS @ IL CAL _H kILIS @ IL CAL − 1 (10) The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift over temperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H. IIS ILIL(OL) IIS(OL) IIS(EN) Figure 45 Current sense ratio in open load at ON condition As soon as a protection event occurs the device is switched OFF and a fault current IIS(FAUL T) is provided by the IS pin if DEN is set to high (see Chapter 8.3 for more details). In fault condition the current IIS(FAUL T) is provided each time the device diagnosis is activated by DEN = "high" . Figure 46 shows the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAUL T). BTG70020A-1ESW Datasheet

Datasheet 62 Rev. 1.00 2023-12-07

I L(HOCT)_150 I IS(FAUL T).min I L(HOCT)_-40 I IS(FAUL T).max Fault Current sense Figure 46 Current sense behavior - overview

10.1.2 Open load in OFF (address #1 - IN = low)

When the input signal is "low" and the address #1 is selected, the device will measure the drain-source voltage and compare it with the open load VDS detection threshold in OFF state VDS(OLOFF). By the use of external components (see Figure 54), it is possible to detect if the load is missing or if there is a short circuit to battery. If a fault condition was detected by the device either the device protection fault current IIS(DEVOFF) or the I2t protection fault current IIS(I2tOFF) is provided by the IS pin each time the channel diagnosis is checked in OFF state. See Figure 47 for further details. In OFF state, when DEN pin is set to “high” the VDS voltage is compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). When the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Figure 47 shows the relationship between IIS(OLOFF), IIS(DEVOFF) and IIS(I2tOFF) as functions of VDS. By the fact that the three currents do not overlap, it is always possible to differentiate between open load in OFF, I2t protection and device protection triggered. Furthermore, the first and highest prioritization has the I2t protection fault current IIS(I2tOFF), second has the device protection fault current IIS(DEVOFF) and third has the open load in OFF current IIS(OLOFF). I IS V DS I IS(OLOFF) I IS(DEVOFF) I IS(I2tOFF) V DS(OLOFF) Figure 47 IIS in OFF state BTG70020A-1ESW Datasheet Datasheet 63 Rev. 1.00 2023-12-07

It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at IS pin for open load in OFF diagnosis to allow the internal comparator to settle. In Figure 48 the timings for an open load detection are shown - the load is always disconnected. t IN t DEN V OUT ~ V S t IS(OLOFF)_D t I IS(OLOFF) I IS I IS(OL) V DS(OLOFF) t Load connected Figure 48 Open load in OFF timings - load disconnected

10.1.3 I2t setting (address #2 - IN = x)

The device provides for each I2t protection curve setting a corresponding sense current IIS(I2t_x) at the IS pin in case of setting the sequential diagnosis mode to address #2. The I2t settings are set by the resistor at the I2t pin (see Figure 49). The device offers an open and short detection of the I2t pin at the IS pin. In this case a pin short current IIS(I2t_SHORT) or a pin open current IIS(I2t_OPEN) will be distributed during the diagnosis of the I2t setting. R I2t I IS R I2t_1 R I2t_3 R I2t_4 R I2t_5 R I2t_6R I2t_2R I2t_ SHORT R I2t_ OPEN I IS(I2t_ OPEN ) I IS(I2t_6) I IS(I2t_5) I IS(I2t_4) I IS(I2t_3) I IS(I2t_2) I IS(I2t_1) I IS(I2t_ SHORT ) Figure 49 Diagnosis of I2t setting BTG70020A-1ESW Datasheet Datasheet 64 Rev. 1.00 2023-12-07

10.1.4 I2t status (address #3 - IN = x)

A current proportional to the actual I2t status SI2t_A according to IIS STATUS_I2t_x = SI2t_A · IIS I2t_x_100 % (11) is provided at the IS pin depending on the selected I2t protection curve (see Figure 50). When the I2t protection curve status has reached 100% the IIS(STATUS_I2t_x) is equal to IIS(I2t_x_100%) . I IS I IS(I2t_6_100%) Actual I2t status S I2t_A [%] 100 I IS(I2t_5_100%) I IS(I2t_4_100%) I IS(I2t_3_100%) I IS(I2t_2_100%) I IS(I2t_1_100%) Figure 50 Diagnosis of I2t status calculation

10.1.5 OCT setting (address #4 - IN = x)

IIS(OCT) A = 54 . 5 · IOCT A (12) is provided at the IS pin depending on the selected OCT setting during readout of sequential diagnosis address #4 (see Figure 51). The IOCT range is limited by IOCT ,MAX and IOCT ,MIN for highest and and lowest configurable overcurrent threshold respectively. The device offers an open and short detection of the OCT pin at the IS pin. In this case a pin short current IIS(OCT_SHORT) or a pin open current IIS(OCT_OPEN) will be distributed during the diagnosis of the OCT setting. BTG70020A-1ESW Datasheet Datasheet 65 Rev. 1.00 2023-12-07

IOCT_SHORT IIS(OCT_OPEN) IIS(LOCT) IIS(HOCT) IIS(OCT_SHORT) IOCT_MIN IOCT_MAXIOCT_OPEN Figure 51 Diagnosis of overcurrent threshold setting

10.1.6 Digital current sense (address #5 - IN = high)

A current proportional to the load current according to kILDIS = IL IDIS (13) is provided at IS pin when the following conditions are fulfilled:

• Address #5 and IN = "high"
• The diagnosis (current sense) is enabled with VDS < VDS(OLOFF)
• No fault (as described in Chapter 8.3) is present or was latched (see Figure 46 for further details) BIT IL 128 256 k ILDIS IS

1 LSB

2 LSB

4 LSB

Figure 52 Digital current sense behavior - overview BTG70020A-1ESW Datasheet Datasheet 66 Rev. 1.00 2023-12-07

The digital current sense settling time for an infinite fast current ramp is determined by: tDIS_SET = IL ≤ 64 · LSB, IL LSB · tCON 65 · LSB < IL ≤ 128 · LSB, 64 + IL − 64 · LSB 2LSB · tCON 129 · LSB < IL ≤ 256 · LSB, 96 + IL − 128 · LSB 4LSB · tCON (14)

10.1.7 Sense verification current (address #5 - IN = low)

To verify the function of the current sensing path in OFF state, the device offers a sense verification adress. In this mode a predefined current IIS(VER) is provided at the current sense pin independent of the load condition.

10.2 SENSE timings

Figure 53 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load change). As a proper signal cannot be established before the load current is stable (therefore before tON), the SENSE settling time after start-up is defined by tsIS(DIAG). t t t IL IIS t ONOFF OFF IN t sIS( DIAG) t sIS( LC) t sIS(OFF)t sIS(ON15)t sIS(OFF) Address #1 / #5 Address #1 / #5 Address #2 / #3 / #4 DEN t sIS(ON234) Figure 53 SENSE settling/disabling timing BTG70020A-1ESW Datasheet Datasheet 67 Rev. 1.00 2023-12-07

10.3 Electrical characteristics diagnosis

Table 17 Electrical characteristics diagnosis VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SENSE fault current IIS(FAUL T) 4.4 5.5 10 mA IN = "high" Device or I2t protection triggered Address #1 VS = 6 V PRQ-287 Device protection fault current IIS(DEVOFF) 4.4 6.1 10 mA IN = "low" Device protection triggered Address #1 VS = 6 V PRQ-893 I2t protection fault current IIS(I2tOFF) 2.56 3.20 3.84 mA 1) IN = "low" I2t protection triggered Address #1 PRQ-631 SENSE open load in OFF current IIS(OLOFF) 0.8 1.15 1.5 mA IN = "low" Address #1 PRQ-288 Sense verification current IIS(VER) 400 500 600 µA IN = "low" Address #5 PRQ-1333 SENSE open load in OFF delay time (from ON to OFF) tIS(OLOFF)_D – 5 20 µs VDS < VOL(OFF) from IN falling edge to VIS = RSENSE ⋅ 0.9 ⋅ IIS(OLOFF),MIN DEN = “high” Address #1 PRQ-290 Open load VDS detection threshold in OFF state VDS(OLOFF) 1.3 1.8 2.3 V IN="low" Address #1 PRQ-292 SENSE settling time with nominal load current stable tsIS(ON15) – 5 40 µs IL = IL(NOM)_85 DEN from “low” to “high” IN = "high" Address #1, #5 PRQ-293 (table continues...) BTG70020A-1ESW Datasheet Datasheet 68 Rev. 1.00 2023-12-07

Table 17 (continued) Electrical characteristics diagnosis VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SENSE settling time with nominal load current stable after startup tsIS(DIAG) – 400 750 µs 1) IL = IL(NOM)_85 IN, DEN from “low” to “high” Address #1, #5 PRQ-276 SENSE settling time for sequential diagnosis tsIS(ON234) – 5 20 µs 1) DEN from “low” to “high” IN = "high" Address #2, #3, #4 IN = "low" Address #1, #2, #3, #4, #5 PRQ-1201 SENSE disable time tsIS(OFF) – 5 20 µs 1) From DEN falling edge to IIS = IIS(OFF) See Figure 53 IN="high" Address #1 PRQ-295 SENSE settling time after load change tsIS(LC) – 5 20 µs 1) From 10% IL(NOM)_85 to IL(NOM)_85 See Figure 53 IN="high" Address #1 PRQ-296 Load jump duration in Address 5 tsIS(LC_Address5) 22 29 36 µs 1) From 10% IL(NOM)_85 to IL(NOM)_ 85*x for x=1,2,3,4. See Figure 53 IN="high" Address #5 PRQ-1491 Digital SENSE conversion time tCON 720 800 880 ns 1) PRQ-1455 (table continues...) BTG70020A-1ESW Datasheet Datasheet 69 Rev. 1.00 2023-12-07

Table 17 (continued) Electrical characteristics diagnosis VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. DEN pulse duration for sequential diagnosis address change tDEN(SD_AC) 25 50 75 µs 1) PRQ-610 DEN pulse duration for sequential diagnosis timeout tDEN(SD_TO) 150 – – µs 1) PRQ-937 DEN pulse duration for sequential diagnosis address hold tDEN(SD_AH) 0 5 10 µs 1) PRQ-1468 1) Not subject to production test - specified by design. Table 18 Electrical characteristics diagnosis VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SENSE saturation current IIS(SAT) 4.4 – 15 mA 1) VSIS = VS - VIS ≥ 2 V See Figure 46 PRQ-277 SENSE leakage current when disabled IIS(OFF) – 0.01 0.5 µA DEN = "low" VIS = 0 V PRQ-279 SENSE leakage current when enabled at T J ≤ 85°C IIS(EN)_85 – 0.2 1 µA 1) TJ ≤ 85°C DEN = "high" IL = 0 A See Figure 45 PRQ-280 SENSE leakage current when enabled at T J = 150°C IIS(EN)_150 – 0.2 1 µA TJ = 150°C DEN = "high" IL = 0 A See Figure 45 PRQ-281 (table continues...) BTG70020A-1ESW Datasheet Datasheet 70 Rev. 1.00 2023-12-07

Table 18 (continued) Electrical characteristics diagnosis VS = 5 V to 20 V, TJ = -40°C to +150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Saturation voltage in kILIS operation - (VS - VIS) VSIS_k – 0.5 1 V 1) VS = 5 V IN = DEN = "high" IL ≤ 1.2 * IL(NOM)_85 PRQ-282 Saturation voltage in open load at OFF diagnosis - (VS - VIS) VSIS_OL – 0.5 1 V 1) VS = 5 V IIS = IIS(OLOFF)_Min IN = "low" DEN = "high" PRQ-283 Saturation voltage in fault diagnosis - (VS - VIS) VSIS_F – 0.5 1 V 1) VS = 5 V IIS = IIS(FAUL T)_Min IN = "low" DEN = "high" latch ≠ 0 -40°C < TJ ≤ 150°C PRQ-284 Saturation voltage in sequential diagnosis - (VS - VIS) VSIS_SD – 0.5 1 V 1) VS = 5 V IN = DEN = "high" Address #2: RI2t = 10 kΩ Address #3: IIS(I2t_1_100%) Address #4: IOCT = 50 µA Address #5: IL ≤ 1.2 * IL(NOM)_85 PRQ-1453 Power supply to IS pin clamping voltage at T J = -40°C VSIS(CLAMP)_-40 33 36.5 42 V IIS = 1 mA TJ = -40°C See Figure 20 PRQ-285 Power supply to IS pin clamping voltage at T J ≥ 25°C VSIS(CLAMP)_25 35 38 44 V 2) IIS = 1 mA TJ ≥ 25°C See Figure 20 PRQ-286 1) Not subject to production test - specified by design. 2) Tested at TJ = 150°C. BTG70020A-1ESW Datasheet Datasheet 71 Rev. 1.00 2023-12-07

10.3.1 Electrical characteristics diagnosis - power output stages

Table 19 Diagnosis power output stage VS = 5 V to 20 V, TJ = -40°C to 150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Open load output current Open load output current at IIS = 4 µA IL(OL)_4u 17 114 211 mA IN = "high" Address #1 IIS = IIS(OL) = 4 µA PRQ-1161 Current sense ratio Current sense ratio at - IL = IL04 kILIS04 -85% 33500 +85% – IL04 = 150 mA IN = "high" Address #1 PRQ-1162 Current sense ratio at - IL = IL08 kILIS08 -30% 25400 +30% – IL08 = 500 mA IN = "high" Address #1 PRQ-1163 Current sense ratio at - IL = IL10 kILIS10 -20% 25000 +20% – IL10 = 1 A IN = "high" Address #1 PRQ-1164 Current sense ratio at - IL = IL13 kILIS13 -15% 24500 +15% – IL13 = 5 A IN = "high" Address #1 PRQ-1165 Current sense ratio at - IL = IL15 kILIS15 -8% 24500 +8% – IL15 = 10 A IN = "high" Address #1 PRQ-1166 Current sense ratio at - IL = IL16 kILIS16 -8% 24500 +8% – IL16 = 15 A IN = "high" Address #1 PRQ-1167 Current sense ratio at - IL = IL18 kILIS18 -8% 24500 +8% – 1) IL18 = 25 A IN = "high" Address #1 PRQ-1168 (table continues...) BTG70020A-1ESW Datasheet Datasheet 72 Rev. 1.00 2023-12-07

Table 19 (continued) Diagnosis power output stage VS = 5 V to 20 V, TJ = -40°C to 150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SENSE current derating SENSE current derating with nominal current calibration ΔkILIS(NOM) -4 0 4 % 1) IL(CAL) = IL16 IL(CAL)_H = IL18 IL(CAL)_L = IL15 TA(CAL) = 25°C PRQ-1195 I2t setting Diagnosis of I2t pin short IIS(I2t_SHORT) 3.40 3.68 3.97 mA Address #2 VS = 6 V RI2t = RI2t_SHORT See Figure 49 PRQ-613 Diagnosis of I2t_1 setting IIS(I2t_1) 2.57 2.83 3.09 mA Address #2 RI2t = RI2t_1 See Figure 49 PRQ-614 Diagnosis of I2t_2 setting IIS(I2t_2) 1.95 2.14 2.33 mA Address #2 RI2t = RI2t_2 See Figure 49 PRQ-615 Diagnosis of I2t_3 setting IIS(I2t_3) 1.43 1.58 1.74 mA Address #2 RI2t = RI2t_3 See Figure 49 PRQ-616 Diagnosis of I2t_4 setting IIS(I2t_4) 1.01 1.13 1.26 mA Address #2 RI2t = RI2t_4 See Figure 49 PRQ-617 Diagnosis of I2t_5 setting IIS(I2t_5) 0.70 0.78 0.87 mA Address #2 RI2t = RI2t_5 See Figure 49 PRQ-618 Diagnosis of I2t_6 setting IIS(I2t_6) 0.39 0.47 0.55 mA Address #2 RI2t = RI2t_6 See Figure 49 PRQ-619 Diagnosis of I2t pin open IIS(I2t_OPEN) 0.08 0.15 0.21 mA Address #2 RI2t = RI2t_OPEN See Figure 49 PRQ-620 (table continues...) BTG70020A-1ESW Datasheet Datasheet 73 Rev. 1.00 2023-12-07

Table 19 (continued) Diagnosis power output stage VS = 5 V to 20 V, TJ = -40°C to 150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. I2t status 100% Status of I2t_1 IIS(I2t_1_100%) 2.86 3.30 3.73 mA 1) Address #3 See Figure 50 PRQ-1384 100% Status of I2t_2 IIS(I2t_2_100%) 2.31 2.66 3.01 mA 1) Address #3 See Figure 50 PRQ-1390 100% Status of I2t_3 IIS(I2t_3_100%) 1.88 2.16 2.45 mA 1) Address #3 See Figure 50 PRQ-1397 100% Status of I2t_4 IIS(I2t_4_100%) 1.52 1.75 1.98 mA 1) Address #3 See Figure 50 PRQ-1401 100% Status of I2t_5 IIS(I2t_5_100%) 1.23 1.42 1.61 mA 1) Address #3 See Figure 50 PRQ-1404 100% Status of I2t_6 IIS(I2t_6_100%) 0.98 1.14 1.29 mA 1) Address #3 See Figure 50 PRQ-1407 OCT setting Diagnosis of OCT pin short IIS(OCT_SHORT) 3.33 3.64 3.94 mA Address #4 VS = 6 V IOCT = 83.3 µA See Figure 51 PRQ-627 Diagnosis of HOCT setting IIS(HOCT) 2.45 2.72 2.99 mA Address #4 IOCT = 50 µA See Figure 51 PRQ-628 Diagnosis of LOCT setting IIS(LOCT) 0.33 0.43 0.52 mA Address #4 IOCT = 7.5 µA See Figure 51 PRQ-629 Diagnosis of OCT pin open IIS(OCT_OPEN) 0.08 0.15 0.21 mA Address #4 IOCT = 3.8 µA See Figure 51 PRQ-630 (table continues...) BTG70020A-1ESW Datasheet Datasheet 74 Rev. 1.00 2023-12-07

Table 19 (continued) Diagnosis power output stage VS = 5 V to 20 V, TJ = -40°C to 150°C Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 2.1 Ω Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Digital current sense ratio LSB for KILDIS conversion LSB 416 490 564 mA 1) PRQ-1460 Digital current sense ratio at - IL = IL13 kILDIS13 -20% 24100 +20% – IL13 = 5 A IN = "high" Address #5 PRQ-1346 Digital current sense ratio at - IL = IL15 kILDIS15 -17.5% 24100 +17.5 – IL15 = 10 A IN = "high" Address #5 PRQ-1347 Digital current sense ratio at - IL = IL16 kILDIS16 -15% 24100 +15% – IL16 = 15 A IN = "high" Address #5 PRQ-1348 Digital current sense ratio at - IL = IL18 kILDIS18 -15% 24100 +15% – 1) IL18 = 25 A IN = "high" Address #5 PRQ-1349 1) Not subject to production test - specified by design. BTG70020A-1ESW Datasheet Datasheet 75 Rev. 1.00 2023-12-07

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

11.1 Application setup

RIS_PROT RSENSE DZ1 RIDL RAD CSENSE Optional GPIO GPIO GPIO ADC VSS VCC RIDLPU Logic supply CVS2 Power GND Logic GND Chassis GND RPD GND Optional COUT GND ZWIREZLOAD* ROL Microcontroller DZ2 * See chapter 1 „potential applications“ Figure 54 PROFET ™ Wire Guard - application diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application.

11.2 External components

RIN 4.7 kΩ Protection of the microcontroller during overvoltage and reverse polarity. Necessary to switch OFF the device output during loss of ground RDEN 4.7 kΩ Protection of the microcontroller during overvoltage and reverse polarity. Necessary to switch OFF the device output during loss of ground RI2t 10...68 kΩ Selection of the I2t protection curve. Protection of the device during overvoltage and reverse polarity ROCT 10...68 kΩ Selection of the OCT threshold. Protection of the device during overvoltage and reverse polarity RIDL 4.7 kΩ Protection of the microcontroller during overvoltage and reverse polarity RIDLPU 47 kΩ Pull-up resistor for idle mode diagnosis at microcontroller BTG70020A-1ESW Datasheet Datasheet 76 Rev. 1.00 2023-12-07

RPD 47 kΩ Output polarization (pull-down). Ensures polarization of the device output to distinguish between open load and short to VS in OFF diagnosis ROL 1.5 kΩ Output polarization (pull-up). Ensures polarization of the device output during open load in OFF diagnosis COUT 10 nF Protection of the device output during ESD events and BCI T1 BC 807 Switches the battery voltage for open load in OFF diagnosis CVS1 100 nF Filtering of voltage spikes on the battery line CVS2 – Filtering / buffer capacitor located at VBAT connector CVSGND 22 nF Buffer capacitor for fast transients. Recommended in case no battery voltage oscillation filter is present DZ2 33 V Z-Diode Suppressor diode. Protection during overvoltage and in case of loss of battery while driving an inductive load RSENSE 1.2 kΩ SENSE resistor RIS_PROT 4.7 kΩ Protection during overvoltage, reverse polarity, loss of ground. Value to be tuned according to microcontroller specifications DZ1 7 V Z-Diode Protection of microcontroller during overvoltage RAD 4.7 kΩ Protection of microcontroller ADC input during overvoltage, reverse polarity, loss of ground. Value to be tuned according to microcontroller specifications CSENSE 220 pF Sense signal filtering. A time constant (RAD + RIS_PROT) * CSENSE longer than 1 μs is recommended RGND 47 Ω Protection in case of overvoltage and loss of battery while driving inductive loads

11.3 Further application information

• Please contact us for information regarding the pin behavior assessment
• For further information you may contact http://www.infineon.com/ BTG70020A-1ESW Datasheet Datasheet 77 Rev. 1.00 2023-12-07

Figure 55 PG-TSDSO-24 (thin (slim) dual small outline 24 pins) package outline BTG70020A-1ESW Datasheet Datasheet 78 Rev. 1.00 2023-12-07

Figure 56 PG-TSDSO-24 (thin (slim) dual small outline 24 pins) package pads and stencil To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). BTG70020A-1ESW Datasheet Datasheet 79 Rev. 1.00 2023-12-07

Date of release Description of changes Rev. 1.00 2023-12-07 Datasheet available BTG70020A-1ESW Datasheet Datasheet 80 Rev. 1.00 2023-12-07

All referenced product or service names and trademarks are the property of their respective owners. Edition 2023-12-07 Published by Infineon Technologies AG

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© 2023 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-lxc1615989989163 Important notice The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Warnings Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.