BT817AKPF

BT819A ETC | Alldatasheet

Document overview

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• PDF pages: 110

Technical content

• Single-Chip Composite/S-Video NTSC/PAL to YCrCb Digitizer
• On-Chip Ultralock TM
• Square Pixel and CCIR601 Resolu- tion for NTSC and PAL
• Chroma Comb Filtering
• Arbitrary Horizontal Scaling and Vertical Scaling (using line store)
• Arbitrary Temporal Decimation for a Reduced Frame-Rate Video Sequence
• Programmable Hue, Brightness, Saturation, and Contrast
• User-Programmable Cropping of the Video Window
• 2x Oversampling to Simplify External Analog Filtering
• Two-Wire I C Bus Interface
• On-Chip 40-Pixel-Deep Asynchronous Output FIFO
• 8- or 16-Bit Pixel Interface
• YCrCb (4:2:2) Output Format
• Software Selectable Three-Input Analog Mux
• Auto NTSC/PAL Format Detect
• Automatic Gain Control
• IEEE 1149.1 (JTAG) Interface
• 100-Pin PQFP and TQFP Packages

Related Products

• Bt812, Bt858, Bt855, Bt856, Bt857
• Bt851

Applications

• Multimedia
• Image Processing
• Desktop Video
• Video Phone
• Teleconferencing
• Interactive Video Bt819A – Video Capture Processor for TV/VCR Analog Input Bt817A – Composite Video and S-Video Decoder Bt815A – Composite Video Decoder The Bt819A, Bt817A and Bt815A VideoStream Decoders are a family of single- chip, pin and register compatible, composite NTSC/PAL video and S-video decoders. Low operating power consumption and power down capability make them ideal low-cost solutions for PC video capture applications on both desktop and portable system platforms. They support square pixel and CCIR601 resolu- tions for both NTSC and PAL. They have a flexible pixel port which supports a variety of system interface configurations, and they are offered in both a 100-pin PQFP and 100-pin TQFP. Functional Block Diagram ADC U LTRALOCK TM AND C LOCK MUX0 MUX1 MUXOUT SYNCDET REFOUT YREF+ YIN D ECIMATION LPF O UTPUT L UMA HROMA S EPARATION AND C HROMA O UTPUT V IDEO YREF– FIFO AND O UTPUT F ORMATTING A NALOG M UX ADC CREF+ CIN CREF– AGC T IMING C ONTROL D ATA I C JTAG D EMODULATION S PATIAL AND T EMPORAL S CALING V IDEO T IMING U NIT G ENERATION XT0 XT1 40 MH Z 40 MH Z MUX2 VideoStream™ Decoders Bt819A/817A/815A

Copyright © 1996 Rockwell Semiconductor Systems. All rights reserved. Print date: September, 1996 Rockwell reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Rockwell Semiconductor Systems is believed to be accurate and reliable. However, no responsibility is assumed by Rockwell Semiconductor Systems for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Rockwell Semiconductor Systems. Rockwell products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Rockwell product can reasonably be expected to result in personal injury or death. Rockwell customers using or selling Rockwell products for use in such applications do so at their own risk and agree to fully indemnify Rockwell for any damages resulting from such improper use or sale. Bt is a registered trademark of Rockwell Semiconductor Systems. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. Specifications are subject to change without notice. PRINTED IN THE UNITED STATES OF AMERICA Model Number Package Ambient Temperature Range Bt819AKPF 100-pin PQFP 0˚C to +70˚C Bt819AKTF 100-pin TQFP 0˚C to +70˚C Bt817AKPF 100-pin PQFP 0˚C to +70˚C Bt817AKTF 100-pin TQFP 0˚C to +70˚C Bt815AKPF 100-pin PQFP 0˚C to +70˚C

Ordering Information

T ABLE OF C ONTENTS List of Figures List of Tables Functional Description Functional Overview UltraLock Ô I Pin Descriptions Pin Assignments UltraLock Y/C Separation and Chroma Demodulation Video Scaling, Cropping, and Temporal Decimation Video Adjustments

I C Interface JTAG Interface PC Board Layout Considerations Schematics

v Bt819A/7A/5A Control Register Definitions 0x00 — Device Status Register (STATUS) 0x01 — Input Format Register (IFORM) 0x02 — Temporal Decimation Register (TDEC) 0x03 — MSB Cropping Register (CROP) 0x04 — Vertical Delay Register, Lower Byte (VDELAY_LO) 0x05 — Vertical Active Register, Lower Byte (VACTIVE_LO) 0x06 — Horizontal Delay Register, Lower Byte (HDELAY_LO) 0x07 — Horizontal Active Register, Lower Byte (HACTIVE_LO) 0x08 — Horizontal Scaling Register, Upper Byte (HSCALE_HI) 0x09 — Horizontal Scaling Register, Lower Byte (HSCALE_LO) 0x0A — Brightness Control Register (BRIGHT) 0x0B — Miscellaneous Control Register (CONTROL) 0x0C — Luma Gain Register, Lower Byte (CONTRAST_LO) 0x0D — Chroma (U) Gain Register, Lower Byte (SAT_U_LO) 0x0E — Chroma (V) Gain Register, Lower Byte (SAT_V_LO) 0x0F — Hue Control Register (HUE) 0x10 — Reserved 0x11 — Reserved 0x12 — Output Format Register (OFORM) 0x13 — Vertical Scaling Register, Upper Byte (VSCALE_HI) 0x14 — Vertical Scaling Register, Lower Byte (VSCALE_LO) 0x15 — Test Control Register (TEST) 0x16 — Video Timing Polarity Register (VPOLE) 0x17 — ID Code Register (IDCODE) 0x18 — AGC Delay Register (ADELAY) 0x19 — Burst Delay Register (BDELAY) 0x1A — ADC Interface Register (ADC) 0x1B to 0x1E — Reserved Registers 0x1F — Software Reset Register (SRESET)

Package Mechanical Drawings Datasheet Revision History

Table 11. Example I

video stream supporting a variety of video formats, resolutions and frame rates. only, and there is no output FIFO option. line dropping, and there is no output FIFO option. See Table 1 for a comparison of Bt819A, Bt817A and Bt815A features. Table 1. VideoStream Feature Options

Functional Overview Bt819A/7A/5A The Synchronous Pixel Interface (non-FIFOed output) is common to all three pin-compatible devices, which enables a single system hardware design to be used for all three. Similarly, a common I 2C register set allows a single piece of driver code to be written for software control of all three options. Bt819A Architecture and Partitioning The Bt819A has been developed to provide the most cost-effective, high-quality video input solution for low-cost multimedia subsystems that integrate both graph- ics display and video capabilities. The feature set of the Bt819A supports a vid- eo/graphics system partitioning which optimizes the total cost of a system configured both with and without video capture capabilities. This enables system vendors to easily offer products with various levels of video support using a single base-system design. As graphics chip vendors move from graphics-only to video/graphics coproces- sors and eventually to single-chip video/graphics processor implementations, the ability to efficiently use silicon and package pins to support both graphics acceler- ation, video playback acceleration and video capture becomes critical. This prob- lem becomes more acute as the race towards higher performance graphics requires more and more package pins to be consumed for wide 64-bit memory interfaces and glueless local bus interfaces. The Bt819A minimizes the cost of the video capture function integration in a number of ways. Recognizing that YCrCb to RGB color space conversion is be- coming a required feature of multimedia controllers for acceleration of digital vid- eo playback, the Bt819A avoids redundant functionality and allows the downstream controller to perform this task. Secondly, the Bt819A integrates the FIFO which would otherwise be dedicated to feeding a live video stream to the di- rect memory access engine (DMA) in a video controller. Finally, the Bt819A can minimize the number of interface pins required by a downstream multimedia con- troller in order to keep package costs to a minimum. Controller systems that are designed to take advantage of these features enable video capture capability to be added to the base system in a modular fashion using only a single Integrated Circuit (IC). The Bt817A and Bt815A are targeted at system configurations using stand-alone video controllers or CODECs which typically integrate the scaling and video FIFO functions. UltraLockÔ The Bt819A, Bt817A and Bt815A employ a proprietary technique known as Ul- traLock to lock to the incoming analog video signal. It will always generate the re- quired number of pixels per line from an analog source in which the line length can vary by as much as a few microseconds. UltraLock’s digital locking circuitry en- ables the VideoStream decoders to quickly and accurately lock on to video signals, regardless of their source. Since the technique is completely digital, UltraLock can recognize unstable signals caused by VCR headswitches or any other deviation and adapt the locking mechanism to accommodate the source. UltraLock uses non- linear techniques which are difficult, if not impossible, to implement in genlock systems. And unlike linear techniques, it adapts the locking mechanism automati- cally.

Functional OverviewBt819A/7A/5A Scaling and Cropping The Bt819A can reduce the video image size in both horizontal and vertical direc- tions independently using arbitrarily selected scaling ratios. The X and Y dimen- sions can be scaled down to one-fourteenth of the full resolution. Horizontal scaling is implemented with a six-tap interpolation filter while two-tap interpola- tion is used for vertical scaling with a line store. The Bt817A and Bt815A support vertical scaling by line-dropping. The video image can be arbitrarily cropped by programming the ACTIVE flag to reduce the number of active scan lines and active horizontal pixels per line. The Bt819A, Bt817A and Bt815A also support a temporal decimation feature that reduces video bandwidth by allowing frames or fields to be dropped from a video sequence at regular but arbitrarily selected intervals. Input Interface Analog video signals are input to the Bt819A/7A/5A via a three-input multiplexer that can select between three composite source inputs or between two composite and a single S-video input source. When an S-video source is input to the Bt819A, the luma component is fed through the input analog multiplexer, and the chroma component is fed directly into the C input pin (the Bt815A does not support S-vid- eo input). An automatic gain control circuit enables the Bt819A/7A/5A to compen- sate for reduced amplitude in the analog signal input. The clock signal interface consists of two pairs of pins for crystal connection and two clock output pins. One pair of crystal pins is for connection to a 28.64 MHz (8*NTSC Fsc) crystal which is selected for NTSC operation. The other is for PAL operation with a 35.47 MHz (8*PAL Fsc) crystal. Either of the two crystal frequencies can be selected to generate CLKX1 and CLKX2 output signals. CLKX2 operates at the full crystal frequency (8*Fsc) whereas CLKX1 operates at half the crystal frequency (4*Fsc). Either fundamental or third harmonic crystals may be used. Alternatively, CMOS oscillators may be used. Output Interface The Bt819A’s output interface can be set up to support two different configura- tions: the Synchronous Pixel Interface (SPI) and the Asynchronous Pixel Interface (API). The Bt817A and Bt815A support the Synchronous Pixel Interface only. Both the SPI and the API can support a YCrCb 4:2:2 data stream over a 16-bit- wide path. The SPI also supports an 8-bit path. When the pixel output port is con- figured to operate 8 bits wide, 8 bits of chrominance data are output on the first clock cycle followed by 8 bits of luminance data on the next clock cycle for each pixel. Two clocks are required to output one pixel in this mode, thus a 2x clock is used to output the data. In SPI mode, the Bt819A/7A/5A output interface is similar to the Bt812 inter- face. The Bt819A/7A/5A outputs all horizontal and vertical blanking pixels in ad- dition to the active pixels synchronous with CLKX1 (16-bit mode) or CLKX2 (8-bit mode). It is also possible to insert control codes into the pixel stream using chrominance and luminance values that are outside the allowable chroma and luma ranges. These control codes can be used to flag video events such as ACTIVE, HRESET, and VRESET. Decoding these video events downstream enables the vid-

Functional Overview Bt819A/7A/5A eo controller to do away with pins required for the corresponding video control signals. In the API mode, the Bt819A outputs only the active pixels and control codes at a rate asynchronous with the sample clock. A 40-pixel-deep FIFO buffers the pixel output port and enables the system to burst pixels out of the Bt819A at rates up to 35 Mpixels/sec. An input clock must be provided on CLKIN for operation in this mode. The Bt819A outputs the DV ALID, AEF and AFF flags to provide the system information on the status of the FIFO. I 2C Interface The Bt819A/7A/5A registers are accessed via a two-wire Inter-Integrated Circuit (I2C) interface. The Bt819A/7A/5A operates as a slave device. Serial clock and data lines, SCL and SDA, are used to transfer data from the bus master at a rate of 100 Kbits/s. Chip select and reset signals are also available to select one of two possible Bt819A/7A/5A devices in the same system and to set the registers to their default values.

Figure 1. Bt819A/7A/5A Detailed Block Diagram

40 PIXEL FIFO

Pins with alternate definitions on the Bt817A or Bt815A are indicated by shading (e.g., see pin number 67). Table 2. Pin Descriptions Grouped By Pin Function (1 of 6) between three composite sources or two composite and one S-video source.

45 I MUX2

53 O MUXOUT The analog video output of the 3 to 1 multiplexer. Connected to the YIN pin. 52 I YIN The analog composite or luma input to theY -ADC. 67 I CIN The analog chroma input to the C-ADC. bleeder resistor should be connected to ground. 43 O REFOUT Output of the AGC which drives the YREF+ and CREF+ pins. AGND/CREF+ May be connected to either AGND or REFOUT. G AGND Ground for analog circuitry on Bt815A.

50 A YDBIAS

63 A CDBIAS

19 I SCL The I 2C Serial Clock Line. 18 I/O SDA The I 2C Serial Data Line.

15 I RST

eight XTAL cycles will leave the device in an undetermined state. Table 2. Pin Descriptions Grouped By Pin Function

edge of this output indicates the beginning of a new scan line of video. In API mode: this signal is one clock cycle wide and is output relative to CLKIN. In API mode, it immediately follows the last active pixel of a line. Note: The polarity of this pin is programmable through the VPOLE register. next active pixel is the first active pixel of the next field. Note: The polarity of this pin is programmable through the VPOLE register. Note: The polarity of this pin is programmable through the VPOLE register. G GND Ground for digital circuitry on Bt817A and Bt815A. tion of the QCLK pin functions. even field is being digitized. Note: The polarity of this pin is programmable through the VPOLE register. bus contains Cb chroma information. Note: The polarity of this pin is programmable through the VPOLE register. Table 2. Pin Descriptions Grouped By Pin Function (3 of 6)

the bus in 16-bit mode. VD8 is the least significant bit of the bus in 8-bit mode. and VRESET are always inserted into the data stream. 84 O DVALID Data Valid Output (TTL Compatible). In SPI mode: this pin indicates if a valid pixel is being output onto the data bus. valid pixel data is being output. Note: The polarity of this pin is programmable through the VPOLE register. Figure 28 for a recommended circuit. NC No Connect on Bt817A and Bt815A. also be programmed to signal a half full condition (with 20 locations full). Note: The polarity of this pin is programmable through the VPOLE register. NC No Connect on Bt817A and Bt815A. or CLKX1 outputs of the Bt819A can be tied to this pin. SPI mode, CLKIN must be pulled low. G GND Ground for digital circuitry on Bt817A and Bt815A. P VDD Power supply for digital circuitry on Bt817A and Bt815A. Table 2. Pin Descriptions Grouped By Pin Function (4 of 6)

be tied directly to these pins, or a single-ended oscillator can be connected to XT0I.

13 A XT0O

be tied directly to these pins, or a single-ended oscillator can be connected to XT1I.

17 A XT1O

MHz for NTSC or 17.734475 MHz for PAL). MHz for NTSC, or 35.46895 MHz for PAL). JTAG operations are not being performed, this pin must be driven to a logical low. performed, this pin must be left floating or tied high. operations are not being performed, this pin must be left floating or tied high. and will be three-stated at all other times.

35 I TRST

each group of VDD pins and the ground plane as close to the device as possible. as close to the device as possible.

Figure 2. Bt819A Pinout

Figure 3. Bt817A Pinout

Figure 4. Bt815A Pinout

The Challenge The line length (the interval between the midpoints of succeeding horizontal sync pulses) of analog video sources is not constant. For a stable source such as studio quality source or test signal generators, this variation is very small: –2 ns. Howev- er, for an unstable source such as a VCR, laser disk player, or TV tuner, line length variation is as much as a few microseconds. Digital display systems require a fixed number of pixels per line despite these variations. The Bt819A employs a technique known as UltraLock to implement locking to the horizontal sync and the subcarrier of the incoming analog video sig- nal by generating the required number of pixels per line. Operation Principles of UltraLock UltraLock is based on sampling using a fixed-frequency stable clock. Since the video line length will vary, the number of samples generated using a fixed-frequen- cy sample clock will also vary from line to line. If the number of generated samples per line is always greater than the number of samples per line required by the par- ticular video format, the number of acquired samples can be reduced to fit the re- quired number of pixels per line. The Bt819A requires an 8*Fsc (28.64 MHz for NTSC and 35.47 MHz for PAL) crystal or oscillator input signal source. The 8*Fsc clock signal, or CLKx2, is di- vided down to CLKx1 internally (14.32 MHz for NTSC and 17.73 MHz for PAL). Both CLKx2 and CLKx1 are made available to the system. UltraLock operates at CLKx1 although the input waveform is sampled at CLKx2 then low pass filtered and decimated to CLKx1 sample rate. At a 4*Fsc (CLKx1) sample rate there are 910 pixels for NTSC and 1,135 pixels for PAL within a nominal line time interval (63.5 ms for NTSC and 64 ms for PAL). For square pixel NTSC and PAL formats there should only be 780 and 944 pixels per video line, respectively. This is because the square pixel clock rates are slower UltraLock accommodates line length variations from nominal in the incoming video by always acquiring more samples, at an effective 4*Fsc rate, than are re- quired by the particular video format and outputting the correct number of pixels per line. UltraLock then interpolates the required number of pixels in a way that maintains the stability of the original image despite variation in the line length of the incoming analog waveform. The example illustrated in Figure 5 shows three successive lines of video being decoded for square pixel NTSC output. The first line is shorter than the nominal NTSC line time interval of 63.5 ms. On this first line, a line time of 63.2 ms sampled at 4*Fsc (14.32 MHz) generates only 905 pixels. The second line matches the nominal line time of 63.5 ms and provides the expected 910 pixels. Finally, the

cases, UltraLock sends only 780 pixels through the output FIFO. please see the Output Interface section in the Electrical Interfaces chapter. Figure 5. UltraLock Behavior for NTSC Square Pixel Output

can be controlled independently. Figure 9. Optional Luma 3 MHz Low Pass Filter Response

zontal high-frequency spectrum in the luminance signal. The Bt819A implements horizontal scaling through poly-phase interpolation. The Bt819A uses 32 different phases to accurately interpolate the value of a pixel. This provides an effective pixel jitter of 6 ns. dropping for vertical scaling. Figure 12. Filtering and Scaling

6 TAP , 32 PHASE

768 X 8

2 TAP , 32 PHASE

3 MH Z

Video Scaling, Cropping, and Temporal Decimation Bt819A/7A/5A Chrominance Scaling A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chrominance. Vertical scaling of chrominance is implemented through simple decimation or line dropping, followed by chrominance comb filtering using a 768x8-bit line store. Scaling Registers The Horizontal Scaling Ratio Register (HSCALE) is programmed with the hor- izontal scaling ratio. When outputting unscaled video (in NTSC), the Bt819A will output 910 pixels per line. This corresponds to the pixel rate at f CLKx1 (4*Fsc). This register is the control for scaling the video to the desired size. For example, square pixel NTSC requires 780 samples per line, while CCIR601 requires 858 samples per line. HSCALE_HI and HSCALE_LO are two 8-bit registers that, when concatenated, form the 16-bit HSCALE register. The method below uses pixel ratios to determine the scaling ratio. As such, no floating point math is involved. This is an advantage in certain applications, such as when the scaling is being dynamically controlled by the user with a mouse. The following formula should be used to determine the scaling ratio to be entered into the 16-bit register: For example, to scale PAL input to square pixel QCIF, the total number of horizon- tal pixels is 236: An alternative method for determining the HSCALE value uses the ratio of the scaled active region to the unscaled active region as shown below: In this equation, the HACTIVE value cannot be cropped; it represents the total ac- tive region of the video line. This equation produces roughly the same result as us- ing the full line length ratio shown in the first example. However, due to truncation, the HSCALE values determined using the active pixel ratio will be slightly differ- ent than those obtained using the total line length pixel ratio. The values in Table 3 were calculated using the full line length ratio. NTSC: HSCALE = [ ( 910/P desired ) – 1] * 4096 PAL: HSCALE = [ ( 1135/P desired ) – 1] * 4096 where: Pdesired = Desired number of pixels per line of video, includ- ing active, sync and blanking. HSCALE = [ ( 1135/236 ) – 1 ] * 4096 = 15602 = 0x3CF2 NTSC: HSCALE = [ (754 / HACTIVE) – 1] * 4096 PAL: HSCALE = [ (922 / HACTIVE) – 1] * 4096 where: HACTIVE = Desired number of pixels per line of video, not in- cluding sync or blanking.

Video Scaling, Cropping, and Temporal DecimationBt819A/7A/5A The Vertical Scaling Ratio Register (VSCALE) is programmed with the ver- tical scaling ratio. It defines the number of vertical lines output by the Bt819A. The following formula should be used to determine the value to be entered into this 13-bit register. The loaded value is a two’s-complement, negative value. For example, to scale PAL input to square pixel QCIF, the total number of vertical lines is 156: Note that only the 13 least significant bits of the VSCALE value are used. The five LSB’s of VSCALE_HI and the 8-bit VSCALE_LO register form the 13-bit VSCALE register. The three MSB’s of VSCALE_HI are used to control other functions. The user must take care not to alter the values of the three most significant bits when writing a vertical scaling value. The following C-code fragment illustrates changing the vertical scaling value: #define BYTE unsigned char #define WORD unsigned int #define VSCALE_HI 0x13 #define VSCALE_LO 0x14 BYTE ReadFromBt819A( BYTE regAddress ); void WriteToBt819A( BYTE regAddress, BYTE regValue ); void SetBt819AVScaling( WORD VSCALE ) BYTE oldVscaleMSByte, newVscaleMSByte; /* get existing VscaleMSByte value from */ /* Bt819A VSCALE_HI register */ oldVscaleMSByte = ReadFromBt819A( VSCALE_HI ); /* create a new VscaleMSByte, preserving top 3 bits */ newVscaleMSByte = (oldVscaleMSByte & 0xE0) | (VSCALE >> 8); /* send the new VscaleMSByte to the VSCALE_HI reg */ WriteToBt819A( VSCALE_HI, newVscaleMSByte ); /* send the new VscaleLSByte to the VSCALE_LO reg */ WriteToBt819A( VSCALE_LO, (BYTE) VSCALE ); VSCALE = ( 0x10000 – { [ ( scaling_ratio ) – 1] * 512 } ) & 0x1FFF VSCALE = ( 0x10000 – { [ ( 4/1 ) - 1 ] * 512 } ) & 0x1FFF = 0x1A00 where: & = bitwise AND | = bitwise OR >> = bit shift, MSB to LSB

ues locally, the READ operation can be eliminated. the register values required. cropped image as illustrated in Figure 13. Table 3. Scaling Ratios for Popular Formats Using Frequency Values

Figure 13. Effect of the Cropping and Active Registers

Video Scaling, Cropping, and Temporal Decimation Bt819A/7A/5A Cropping Registers The Horizontal Delay Register (HDELAY) is programmed with the delay be- tween the falling edge of HRESET and the rising edge of ACTIVE. The count is programmed with respect to the scaled frequency clock. Note that HDELAY should always be an even number. The Horizontal Active Register (HACTIVE) is programmed with the actual number of active pixels per line of video. This is equivalent to the number of scaled pixels that the Bt819A should generate on a line. For example, if this register con- tained 90, and HSCALE was programmed to downscale by 4:1, then 90 active pix- els would be output. The 90 pixels would be a 4:1 scaled image of the 360 pixels (at CLKx1) starting at count HDELAY . HACTIVE is restricted in the following manner: HACTIVE + HDELAY £ Total Number of Scaled Pixels. For example, in the NTSC square pixel format, there is a total of 780 pixels, in- cluding blanking, sync and active regions. Therefore: HACTIVE + HDELAY £ 780. When scaled by 2:1 for CIF, the total number of active pixels is 390. Therefore: HACTIVE +HDELAY £ 390. The HDELAY register is programmed with the number of scaled pixels be- tween HRESET and the first active pixel. Because the front porch is defined as the distance between the last active pixel and the next horizontal sync, the video line can be considered in three components: HDELAY , HACTIVE and the front porch. See Figure 14. When cropping is not implemented, the number of clocks at the 4x sample rate (the CLKx1 rate) in each of these regions is shown below: The value for HDELAY is calculated using the following formula: HDELAY = [(CLKx1_HDELAY / CLKx1_HACTIVE) * HACTIVE] & 0x3FE CLKx1_HDELAY and CLKx1_HACTIVE are constant values, so the equation becomes: NTSC: HDELAY = [(135 / 754) * HACTIVE] & 0x3FE PAL: HDELAY = [(186 / 922) * HACTIVE] & 0x3FE CLKx1 Front Porch CLKx1 HDELAY CLKx1 HACTIVE CLKx1 Total NTSC 21 135 754 910 PAL 27 186 922 1135

the number of lines to skip at the beginning of a frame. number of vertical lines output. HACTIVE are programmed with respect to the scaled pixels defined by HSCALE. lines before scaling (before VSCALE is applied). hard disk transfer rates or system bus bandwidth may limit the frame capture rate. Figure 14. Regions of the Video Signal

Video Scaling, Cropping, and Temporal Decimation Bt819A/7A/5A Examples: When changing the programming in the temporal decimation register, 0x00 should be loaded first, and then the decimation value. This will ensure that the decimation counter is reset to zero. If zero is not first loaded, the decimation may start on any field or frame in the sequence of 60 (or 50 for PAL). On power-up, this preload is not necessary because the counter is internally reset. When decimating fields, The Bt819A/7A/5A does not guarantee starting on an even or odd field. TDEC = 0x02 Decimation is performed by frames. Two frames are skipped per 60 frames of video, assuming NTSC decoding. Frames 1–29 are output normally, then ACTIVE remains low for one frame. Frames 30–59 are then output followed by another frame of inactive video. TDEC = 0x9E Decimation is performed by fields. Thirty fields are output per 60 fields of video, assuming NTSC decoding. This value outputs every other field (every odd field) of video starting with field one in frame one. TDEC = 0x01 Decimation is performed by frames. One frame is skipped per 50 frames of video, assuming PAL decoding. TDEC = 0x00 Decimation is not performed. Full frame rate video is output by the Bt819A.

Video AdjustmentsBt819A/7A/5A Video Adjustments The Bt819A provides programmable hue, contrast, saturation, and brightness. The Hue Adjust Register (HUE) The Hue Adjust Register is used to offset the hue of the decoded signal. In NTSC, the hue of the video signal is defined as the phase of the subcarrier with reference to the burst. The value programmed in this register is added or subtracted from the phase of the subcarrier, which effectively changes the hue of the video. The hue can be shifted by plus or minus 90 degrees. Because of the nature of PAL encoding, hue adjustments can not be made when decoding PAL. The Contrast Adjust Register (CONTRAST) The Contrast Adjust Register (also called the luma gain) provides the ability to change the contrast from approximately 0% to 200% of the original value. The de- coded luma value is multiplied by the 9-bit coefficient loaded into this register. The Saturation Adjust Registers (SAT_U, SAT_V) The Saturation Adjust Registers are additional color adjustment registers. It is a multiplicative gain of the U and V signals. The value programmed in these regis- ters are the coefficients for the multiplication. The saturation range is from approx- imately 0% to 200% of the original value. The Brightness Register (BRIGHT) The Brightness Register is simply an offset for the decoded luma value. The pro- grammed value is added or subtracted from the original luma value which changes the brightness of the video output. The luma output is in the range of 0 to 255. Brightness adjustment can be made over a range of –64 to +63.

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Analog Signal Selection The Bt819A contains an on-chip 3:1 mux. This mux can be used to switch between three composite sources or two composite sources and one S-video source. In the first configuration, connect the inputs of the mux (MUX0, MUX1 and MUX2) to the three composite sources. In the second configuration, connect two inputs to the composite sources and the other input to the luma component of the S-video con- nector. In both configurations the output of the mux (MUXOUT) should be con- nected to the input to the luma A/D (YIN) and the input to the sync detection circuitry (SYNCDET). When implementing S-video, the input to the chroma A/D (CIN) should be connected to the chroma signal of the S-video connector. Use of the multiplexer is not a requirement for operation. If digitization of only one video source is required, the source may be connected directly to YIN and SYNCDET. Multiplexer Considerations The multiplexer is not a break-before-make design. Therefore, during the multi- plexer switching time it is possible for the input video signals to be momentarily connected together through the equivalent of 200 ohms. The multiplexers cannot be switched on a real-time pixel-by-pixel basis. Autodetection of NTSC or PAL Video If the Bt819A is configured to decode both NTSC and PAL, the Bt819A can be programmed to automatically detect which format is being input to the chip. Au- todetection will select the proper clock source for the format detected, (if NTSC is detected then XTAL0 is selected, if PAL is detected XTAL1 is selected.) Alterna- tively, the decoding configuration can be programmed by writing to the Input For- mat Register (0x01). The Bt819A determines the video source input to the chip by counting the num- ber of lines in a frame. The result of this is indicated in bit NUML in the STATUS register. Based on this bit, the format of the video is determined, and XT0 or XT1 is selected for the clock source. Automatic format detection will select the clock source, but it will not program the required registers. The scaling and cropping reg- isters (VSCALE, HSCALE, VDELAY , HDELAY , V ACTIVE, and HACTIVE) as well as the burst delay and AGC delay registers (BDELAY and ADELAY) must be programmed accordingly.

the internal resistor ladder. ma A/D pins are not available on the Bt815A. clamping is automatically performed. Figure 15. In this configuration, the Bt819A controls the voltage for the top of the gramming the ADC Interface Register (0x1A). PAL video and must be configured with a 35.46895 MHz source.

• 28.636363 MHz or 35.468950 MHz
• Third overtone
• Parallel resonant
• 30 pF load capacitance
• 50 ppm
• Series resistance 40 W or less

Input InterfaceBt819A/7A/5A The following crystals are recommended for use with the Bt819A: 1 Standard : This vendor will support very short lead times. (818) 443-2121 2BAK28M636363GLE30A 2BAK35M468950GLE30A

2 MMD

(714) 444-1402 A30AA3-28.63636MHZ A30AA3-35.46895MHZ

3 GED

(619) 591-4170 PKHC49-28.63636-.030-005-40R, 3rd overtone crystal PKHC49-35.46895-.030-005-40R, 3rd overtone crystal

4 M-Tron

(800) 762-8800 MP-1 28.63636, 3rd overtone crystal MP-1 35.46895, 3rd overtone crystal

5 Monitor

(619) 433-4510 MM49X3C3A-28.63636, 3rd overtone crystal MM49X3C3A-35.46895, 3rd overtone crystal

6 CTS

(815) 786-8411 R3B55A30-28.63636, 3rd overtone crystal R3B55A30-35.46895, 3rd overtone crystal

7 Fox

(813) 693-0099 HC49U-28.63636, 3rd overtone crystal HC49U-35.46895, 3rd overtone crystal The two clock sources may be configured with either single-ended oscillators, fundamental cut crystals or third overtone mode crystals, parallel resonant. If sin- gle-ended oscillators are used they must be connected to XT0I and XT1I. The clock source options and circuit requirements are shown in Figure 16. The clock source tolerance should be 50 parts-per-million (ppm) or less. Devices that output CMOS voltage levels are required. The load capacitance in the crystal configurations may vary depending on the magnitude of board parasitic ca- pacitance. The Bt819A is dynamic, and, to ensure proper operation, the clocks must be always running, with a minimum frequency of 28.64 MHz. The CLKx1 and CLKx2 outputs from the Bt819A are generated from XT0 and XT1 clock sources. CLKx2 operates at the crystal frequency (8xFsc) while CLKx1 operates at half the crystal frequency (4xFsc).

Figure 15. Typical External Circuitry

75 W330 pF 330 pF

75 W Termination

Figure 16. Clock Options

35.46895 MHz

28.63636 MHz

1 MW 1 MW

band limited to 14 MHz. The suggested filters to do this are shown in Figure 15. pass filter provides additional bandwidth reduction to limit the video to 6 MHz. Figure 17. Luma & Chroma 2X Oversampling Filter

YCrCb 4:2:2 data streams, API supports a 16-bit data stream. duced pin interface (ByteStreamÔ ). and, when programmed, are coded onto the data stream. to SPI mode 1, 16 bits wide. recommendation as illustrated in Figure 19. Figure 18. Output Mode Summary (API Mode Only for Bt819A)

be implemented in only 9 pins: one for CLKx2 and eight for data. value is a control code, and the CbFlag is low (Cr pixel). from a VCR. As a result, VRESET can occur during either a Cb or a Cr pixel. Figure 22 demonstrates coded control for SPI mode 2 (ByteStream). RANGE=0, and code 0 when RANGE=1. Table 7 provides a summary of the control sifnal functions for the SPI modes. Table 5. Description of the Control Codes in the Pixel Stream

only mandatory requirement is that 0 and 255 be reserved for timing information. Table 6. Data Output Ranges Figure 22. Data Output in SPI Mode 2 (ByteStream)

• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • • XFF 0 X02 C B YC R Y FIRST ACTIVE PIXEL OF THE LINE INVALID PIXEL DURING ACTIVE VIDEO LAST VALID PIXEL WAS A CB PIXEL C B Y0 XFF 0 X00 C R Y C B Y0 XFE 0 X01 XX XX LAST PIXEL OF THE LINE (CB PIXEL) LAST PIXEL CODE (CR PIXEL) C R PIXEL VRESET ; AN ODD FIELD FOLLOWS XX XX 0 XFE 0 X06 XX XX ACTIVE PIXEL OF THE LINE N EXT PIXEL IS FIRST

Table 7. Synchronous Pixel Interface (SPI) Control Signals ning of a new video line. See Figure 23 and Figure 24. cating a valid pixel outside the programmed ACTIVE region. value of the last valid pixel. when low it indicates that an odd field (field 1) is being output. VD[15:0] The digital output pins for the video data stream. output during control codes when using SPI mode 2.

Figure 23. Video Timing in SPI Modes 1 and 2

1. ACTIVE, HRESET, VRESET and FIELD are shown here with their default polarity. The polarity is program-

mable via the VPOLE register.

1. FIELD transitions with the end of horizontal active video defined by HDELAY and HACTIVE.

Figure 24. Horizontal Timing Signals in the SPI Modes

64 CLOCK CYCLES AT FCLK X1

than the effective write rate to the FIFO. Figure 25 illustrates the basic interface. RDEN, the user can be assured that the FIFO never overflows. Figure 25. Asynchronous Pixel Interface (API)

Output Interface Bt819A/7A/5A In mode A CLKIN must be connected to CLKx1. Data will be present at the VD outputs whenever valid data are in the FIFO. There are two indicators of the status of the data present at the FIFO output. One is the DV ALID pin. Although this signal is connected internally to the RDEN pin, the signal is still present at the DV ALID pin itself. DV ALID will go high one CLKIN cycle before valid data is present. The second indicator of valid data is the QCLK signal. This pin provides a qualified clock output, based upon CLKIN, and gated by the presence of readable data in the FIFO. QCLK may be used as a load clock for capturing data from the FIFO. These timing relationships are shown in Figure 26 and Figure 27. While DV ALID indicates there is data in the FIFO, ACTIVE or QCLK must be used to differentiate between pixel information and control codes. DV ALID indicates the presence of both while ACTIVE and QCLK indicate the presence of only active valid pixels. After the last pixel is read from the FIFO, the data bus and control signals are undefined. Mode B: FIFO Controlled by System (Bt819A Only) API mode B is similar to mode A. The only difference is that the DV ALID signal is not connected internally to RDEN. The user must monitor the Almost Full Flag (AFF), and the Almost Empty Flag (AEF), and control RDEN manually. In API mode B, QCLK is continuous, and not gated (effectively a delayed output of CLKIN). The timing relationships for API mode B are shown in Figure 28. In ad- dition, Figure 28 shows an external circuit that can be used to control RDEN using the AEF and AFF flags. Note: In API mode B, the FIFO should not be emptied while active video data is being written into the FIFO. If the FIFO is emptied during the active video line, the last two or three pixels read out of the FIFO will be corrupted. To avoid this, simply use the AEF and AFF flags to control RDEN as shown in Figure 28.

timing interface is also available, and defined in Table 9. Figure 28. Basic Timing Relationships for API Mode B

32 OR 20 PIXELS

Table 8. Operation of Timing Signals, API (both modes A and B) 1 1 1 1 A Last pixel of old line. (2) End of video line (Code 01FF or 01FE). 1 1 1 1 A First pixel of new line. 0 0 X X X Stop reading from FIFO. 1 1 1 1 A Last pixel in last line of field Z. (2) End of video line (Code 01FF or 01FE). 10 1 0 V (2) Field transition (Code 05FF for example). 1 1 1 1 A First pixel in first line of field Z+1. 00 1 0 V (2) Field transition (Code 06FF for example). Notes: (1). “A” indicates active pixel data.

Table 9. Asynchronous Pixel Interface Control Signals, Bt819A Only (1 of 2) chroma data is being output. high when the FIFO holds 32 pixels. AEF Almost Empty Flag. Indicates that the FIFO is about to empty. empty. See Figure 28 for a recommended circuit.

VD[15:0] The digital output pins for the video data stream. the FIFO, a positive edge on CLKIN outputs a pixel on VD[15:0]. (effectively a delayed output of CLKIN). Table 9. Asynchronous Pixel Interface Control Signals, Bt819A Only (2 of 2)

Bt819A, the master transmits a stop pulse and ends the cycle. mand, or transfer another 8 bits to be loaded into the next location. fer the contents of the register pointed to by its internal address register, MSB first. The master should acknowledge the receipt of the data and pull the SDA line low. knowledge is received, the Bt819A will proceed to transfer the next register. should execute a write cycle, setting the address register to the desired location. Table 10. Bt819A Address Matrix

2C cycle. This process is illustrated in Table 11 and Figure 31. Table 11. Example I2C Data Transactions I2C Start ——> Master sends Bt819A chip address, i.e. 0x88 or 0x8A. ACK Bt819A generates ACK on successful receipt of chip address. Sub-address ——> Master sends sub-address to Bt819A. ACK Bt819A generates ACK on successful receipt of sub-address. Data(0) ——> Master sends first data byte to Bt819A. ACK(0) Bt819A generates ACK on successful receipt of 1st data byte. Data(n) ——> Master sends nth data byte to Bt819A. ACK(n) Bt819A generates ACK on successful receipt of nth data byte. 2C Stop Master generates STOP to end transfer. I2C Start ——> Master sends Bt819A chip address, i.e. 0x89 or 0x8B. ACK Bt819A generates ACK on successful receipt of chip address. <—— Data(0) Bt819A sends first data byte to Master. ACK(0) Master generates ACK on successful receipt of 1st data byte. <—— Data(n-1) Bt819A sends (n-1)th data byte to Master. ACK(n-1) Master generates ACK on successful receipt of (n-1)th data byte. <—— Data(n) Bt819A sends nth data byte to Master. NO ACK Master does not acknowledge nth data byte. 2C Stop Master generates STOP to end transfer. Sub-address= the 8-bit sub-address of the Bt819A register, MSB first.

subaddress 0x1F. A read of this location will return an undefined value. Figure 31. I2C Protocol Diagram

8 BITS

JTAG Interface Bt819A/7A/5A JTAG Interface Need for Functional Verification As the complexity of imaging chips increases, the need to easily access individual chips for functional verification is becoming vital. The Bt819A has incorporated special circuitry that allows it to be accessed in full compliance with standards set by the Joint Test Action Group (JTAG). Conforming to IEEE P1149.1 “Standard Test Access Port and Boundary Scan Architecture,” the Bt819A has dedicated pins that are used for testability purposes only. JTAG Approach to Testability JTAG’s approach to testability utilizes boundary scan cells placed at each digital pin and digital interface (a digital interface is the boundary between an analog block and a digital block within the Bt819A). All cells are interconnected into a boundary scan register, as shown in Table 12, that applies or captures test data to be used for functional verification of the integrated circuit. JTAG is particularly useful for board testers using functional testing methods. JTAG consists of five dedicated pins comprising the Test Access Port (TAP). These pins are Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI), Test Data Out (TDO) and Test Reset (TRST ). The TRST pin will reset the JTAG controller when pulled low at any time.Verification of the integrated circuit and its connection to other modules on the printed circuit board can be achieved through these five TAP pins. With boundary scan cells at each digital interface and pin, the Bt819A has the capability to apply and capture the respective logic levels. Since all of the digital pins are interconnected as a long shift register, the TAP logic has ac- cess and control of all the necessary pins to verify functionality. The TAP control- ler can shift in any number of test vectors through the TDI input and apply them to the internal circuitry. The output result is scanned out on the TDO pin and exter- nally checked. While isolating the Bt819A from other components on the board, the user has easy access to all Bt819A digital pins and digital interfaces through the TAP and can perform complete functionality tests without using expensive bed-of-nails testers. Optional Device ID Register The Bt819A has the optional device identification register defined by the JTAG specification. This register contains information concerning the revision, actual part number, and manufacturers identification code specific to Brooktree. This reg- ister can be accessed through the TAP controller via an optional JTAG instruction. Refer to Table 13.

A variety of verification procedures can be performed through the TAP controller. cerning the Instruction Register and JTAG state machine. Table 12. Bt819A Boundary Scan Register Definition (1 of 2)

Table 12. Bt819A Boundary Scan Register Definition

Table 13. Device Identification Register Figure 32. Instruction Register (IR)

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duce inductive ringing. Figure 36 shows an example schematic. es, any input amplifiers, and all the digital signal traces leading to the Bt819A. digital plane. See Figure 33. Figure 33. Example Ground Plane Layout

PC B OARD LAYOUT CONSIDERATIONS Power Planes Bt819A/7A/5A Power Planes The power plane area should encompass all Bt819A power pins, voltage reference circuitry, power supply bypass circuitry for the Bt819A, the analog input traces, any input amplifiers, and all the digital signal traces leading to the Bt819A. The Bt819A has digital power (VDD) and analog power (V AA and VPOS). The layout for the power plane should be such that the two planes are at the same elec- trical potential, but they should be isolated from each other in the areas surround- ing the chip. Also, the return path for current should be through the digital plane. This is the same layout as shown for the ground plane (Figure 33). When using a regulator, circuitry must be included to ensure proper power sequencing. The cir- cuitry shown in Figure 34 should help in this regard. Supply Decoupling The bypass capacitors should be installed with the shortest leads possible, consis- tent with reliable operation, to reduce the lead inductance. These capacitors should also be placed as close as possible to the device. Each group of V AA and VDD pins should have a 0.1 mF ceramic bypass capac- itor to ground, located as close as possible to the device. Additionally, 10 mF capacitors should be connected between the analog power and ground planes, as well as between the digital power and ground planes. These capacitors are at the same electrical potential, but provide additional decoupling by being physically close to the Bt819A power and ground planes. See Figure 35 for additional information about power supply decoupling. Digital Signal Interconnect The digital signals of the Bt819A should be isolated as much as possible from the analog signals and other analog circuitry. Also, the digital signals should not over- lay the analog power plane. Any termination resistors for the digital signals should be connected to the reg- ular PCB power and ground planes. Analog Signal Interconnect Long lengths of closely-spaced parallel video signals should be avoided to mini- mize crosstalk. Ideally, there should be a ground line between the video signal trac- es driving the YIN and CIN inputs. Also, high-speed TTL signals should not be routed close to the analog signals to minimize noise coupling. Latch-up Avoidance Latch-up is a failure mechanism inherent to any CMOS device. It is triggered by static or impulse voltages on any signal input pin exceeding the voltage on the power pins by more than 0.5 V , or falling below the GND pins by more than 0.5 V . Latch-up can also occur if the voltage on any power pin exceeds the voltage on any other power pin by more than 0.5 V . In some cases, devices with mixed signal interfaces, such as the Bt819A, can appear more sensitive to latch-up. In reality, this is not the case. However, mixed signal devices tend to interact with peripheral devices such as video monitors or cameras that are referenced to different ground potentials, or apply voltages to the device prior to the time that its power system is stable. This interaction sometimes creates conditions amenable to the onset of latch-up.

• Apply power to the device before or at the same time as the interface cir- cuitry.
• Do not apply voltages below GND–0.5 V , or higher than V AA+0.5 V to any pin on the device. Do not use negative supply op-amps or any other negative voltage interface circuitry. All logic inputs should be held low until power to the device has settled to the specified tolerance.
• Connect all VDD, V AA and VPOS pins together through a low imped- ance plane.
• Connect all GND, AGND and VNEG pins together through a low imped- ance plane.

Figure 34. Optional Regulator Circuitry

Figure 35. Typical Power and Ground Connection Diagram and Parts List as possible, (ceramic chip capacitors are preferred). digital supply and the digital ground. These should be connected as close to the Bt819A as possible. affect the performance of the Bt819A.

Figure 36. Example Schematic

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The following tables describe the function of the various control registers. The section begins with a summary of the register functions and follows with details of each register. Register Name Mnemonic Register Address 640 x 480 Square Pixel NTSC (Default) 768 x 576 Square Pixel PAL 720 x 480 CCIR NTSC 720 x 576 CCIR PAL 360 x 240 2:1 CCIR NTSC (Single Field, CIF) 360 x 288 2:1 CCIR P AL (Single Field, CIF) Device Status STATUS 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Input Format IFORM 0x01 0x58 0x78 0x58 0x78 0x58 0x78 Temporal Decimation TDEC 0x02 0x00 0x00 0x00 0x00 0x00 0x00 MSB Cropping CROP 0x03 0x12 0x23 0x12 0x22 0x11 0x21 Vertical Delay, Lower Byte VDELAY_LO 0x04 0x16 0x16 0x16 0x16 0x16 0x16 Vertical Active, Lower Byte VACTIVE_LO 0x05 0xE0 0x40 0xE0 0x40 0xE0 0x40 Horizontal Delay, Lower Byte HDELAY_LO 0x06 0x78 0x9A 0x80 0x90 0x38 0x48 Horizontal Active, Lower Byte HACTIVE_LO 0x07 0x80 0x00 0xD0 0xD0 0x40 0x0C Horizontal Scaling, Upper Byte HSCALE_HI 0x08 0x02 0x03 0x00 0x05 0x11 0x1A Horizontal Scaling, Lower Byte HSCALE_LO 0x09 0xAA 0x3C 0xF8 0x04 0xF0 0x09 Brightness Control BRIGHT 0x0A 0x00 0x00 0x00 0x00 0x00 0x00 Miscellaneous Control CONTROL 0x0B 0x20 0x20 0x20 0x20 0x20 0x20 Luma Gain, Lower Byte (Contrast) CONTRAST_LO 0x0C 0xD8 0xD8 0xD8 0xD8 0xD8 0xD8 Chroma (U) Gain, Lower Byte (Saturation) SAT_U_LO 0x0D 0xFE 0xFE 0xFE 0xFE 0xFE 0xFE Chroma (V) Gain, Upper Byte (Saturation) SAT_V_LO 0x0E 0xB4 0xB4 0xB4 0xB4 0xB4 0xB4 Hue Control HUE 0x0F 0x00 0x00 0x00 0x00 0x00 0x00 Reserved 0x10 0x00 0x00 0x00 0x00 0x00 0x00 Reserved 0x11 0x00 0x00 0x00 0x00 0x00 0x00

C ONTROL REGISTER DEFINITIONS 0x00 — Device Status Register (STATUS) Bt819A/7A/5A 0x00 — Device Status Register (STATUS) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00. COF is the least significant bit. An asterisk indicates the default option. The COF and LOF status bits hold their values until reset to their default values by writing to them. The other six bits do not hold their values, but continually output the status. PRES Video Present Status. Video is determined as present when an input signal is deter- mined to have a signal above one half the sync height for 31 consecutive clock cy- cles. In the presence of video, this bit is set to a logical one. It can be reset to zero by writing a logical zero to this bit. Due to the nature of the AGC circuitry, it is pos- sible that noise could induce this bit to be set. Therefore, it can not be used for pre- cise determination of the presence of a video source. 0* = Video not present 1 = Video present Output Format OFORM 0x12 0x06 0x06 0x06 0x06 0x06 0x06 Vertical Scaling, Upper Byte VSCALE_HI 0x13 0x60 0x60 0x60 0x60 0x60 0x60 Vertical Scaling, Lower Byte VSCALE_LO 0x14 0x00 0x00 0x00 0x00 0x00 0x00 Test Control TEST 0x15 0x00 0x00 0x00 0x00 0x00 0x00 Video Timing Polarity Register VPOLE 0x16 0x00 0x00 0x00 0x00 0x00 0x00 ID Code IDCODE 0x17 0x70 0x70 0x70 0x70 0x70 0x70 AGC Delay ADELAY 0x18 0x68 0x7F 0x68 0x7F 0x68 0x7F Burst Gate Delay BDELAY 0x19 0x5D 0x72 0x5D 0x72 0x5D 0x72 ADC Interface ADC 0x1A 0x82 0x82 0x82 0x82 0x82 0x82 Reserved — 0x1B- 0x1E Software Reset SRESET 0x1F — ————— Register Name Mnemonic Register Address 640 x 480 Square Pixel NTSC (Default) 768 x 576 Square Pixel PAL 720 x 480 CCIR NTSC 720 x 576 CCIR PAL 360 x 240 2:1 CCIR NTSC (Single Field, CIF) 360 x 288 2:1 CCIR P AL (Single Field, CIF) 7 6 5 4 3 2 1 0 PRES HLOC FIELD NUML CSEL Reserved LOF COF 00000000

C ONTROL REGISTER DEFINITIONS 0x00 — Device Status Register (STATUS)Bt819A/7A/5A HLOC Device in H-lock. If HSYNC is found within –1 clock cycle of the expected posi- tion of HSYNC for 32 consecutive lines, this bit is set to a logical 1. Once set, if HSYNC is not found within –1 clock cycle of the expected position of HSYNC for 32 consecutive lines, this bit is set to a logical 0. MPU writes to this bit are ignored. This bit indicates the stability of the incoming video. While it is an indicator of horizontal locking, some video sources will characteristically vary from line to line by more than one clock cycle so that this bit will never be set. Consumer VCR’s are examples of sources that will tend to never set this bit. 0* = Device not in H-lock 1 = Device in H-lock FIELD Field Status. This bit reflects whether an odd or even field is being decoded. The FIELD bit is determined by the relationship between HRESET and VRESET. 0* = Odd field 1 = Even field NUML Number of Lines. This bit identifies the number of lines found in the video stream. This bit is used to determine the type of video input to the Bt819A. Thirty-two con- secutive fields with the same number of lines is required before this status bit will change. 0* = 525 line format (NTSC) 1 = 625 line format (PAL) CSEL Crystal Select. This bit identifies which crystal port is selected. When automatic format detection is enabled, this bit will be the same as NUML. 0* = XTAL0 input selected 1 = XTAL1 input selected Reserved This bit should only be written with a logical zero. LOF Luma ADC Overflow. On power-up, this bit is set to 0. If an ADC overflow occurs, the bit is set to a logical 1. It is reset after being written to or a chip reset occurs. If an overflow occurs in the luma ADC, the clamp level used for AGC may be adjust- ed by programming the CLAMP bits in the ADC register (0x1A). This is beneficial if the amplitude of the video signal is not accurate with respect to the sync height. The state of this bit is not valid and should be ignored when the ADC is in pow- er-down mode (Y_SLEEP = 1). When the luma A/D is in sleep mode, LOF is set to 1. COF Chroma ADC Overflow. On power-up, this bit is set to 0. If an ADC overflow oc- curs, the bit is set to a logical 1. It is reset after being written to or a chip reset oc- curs. The state of this bit is not valid and should be ignored when the ADC is in power-down mode (C_SLEEP = 1). When the chroma A/D is in sleep mode, COF is set to 1. Reads from this bit are insignificant on the Bt815A.

C ONTROL REGISTER DEFINITIONS 0x01 — Input Format Register (IFORM) Bt819A/7A/5A 0x01 — Input Format Register (IFORM) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x58. FORMAT(0) is the least significant bit. An asterisk indicates the default option. HACTIVE When using the Bt819A with a packed memory architecture, for example, with field memories, this bit should be programmed with a logical 1. When implement- ing a VRAM based architecture, program with a logical 0. 0* = Reset HACTIVE with HRESET 1 = Extend HACTIVE beyond HRESET MUXSEL Used for software control of video input selection. The Bt819A can select between two composite video sources, or one composite and one S-video source. 00 = Reserved 01 = Select MUX2 input to MUXOUT 10* = Select MUX0 input to MUXOUT 11 = Select MUX1 input to MUXOUT XTSEL If automatic format detection is required, logical 11 must be loaded. Logical 01 and 10 are used if software format selection is desired. 00 = Reserved 01 = Select XT0 input (only XT0 present) 10 = Select XT1 input (both XTs present) 11* = Auto XT select enabled (both XTs present) Reserved This bit should only be written with a logical zero. FORMAT Automatic format detection may be enabled or disabled. The NUML bit is used to determine the input format when automatic format detection is enabled. 00* = Auto format detect enabled 01 = NTSC (M) input format 10 = Reserved 11 = PAL (B, D, G, H, I) input format 7 6 5 4 3 2 1 0 HACTIVE MUXSEL XTSEL Reserved FORMAT 01011000

C ONTROL REGISTER DEFINITIONS 0x02 — Temporal Decimation Register (TDEC)Bt819A/7A/5A 0x02 — Temporal Decimation Register (TDEC) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00. DEC_RAT(0) is the least significant bit. An asterisk indicates the default option. This register enables temporal dec- imation by discarding a finite number of fields or frames from the incoming video. DEC_FIELD Defines whether decimation is by fields or frames. 0* = Decimate frames 1 = Decimate fields DEC_RAT DEC_RAT is the number of fields or frames dropped out of 60 (NTSC) or 50 (PAL) fields or frames. 0x00 value disables decimation (all video frames and fields are output). Caution: When changing the programming in the TDEC register, 0x00 must be loaded first and then the decimation value. This will ensure decimation does not start on the wrong field or frame. The register should not be loaded with greater than 60 (0x3C) for NTSC, or 50 (0x34) for PAL. 0x00–0xFF = Number of fields / frames output. 7 6 5 4 3 2 1 0 DEC_FIELD DEC_RAT 00000000

C ONTROL REGISTER DEFINITIONS 0x03 — MSB Cropping Register (CROP) Bt819A/7A/5A 0x03 — MSB Cropping Register (CROP) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x12. HACTIVE_MSB(0) is the least significant bit. See the V ACTIVE, VDELAY , HACTIVE and HDELAY registers for descriptions on the operation of this register. VDELAY_MSB 00xx xxxx–11xx xxxx = The most significant two bits of vertical delay register VACTIVE_MSB xx00 xxxx–xx11 xxxx = The most significant two bits of vertical active register HDELAY_MSB xxxx 00xx–xxxx 11xx = The most significant two bits of horizontal delay register HACTIVE_MSB xxxx xx00–xxxx xx11 = The most significant two bits of horizontal active register 0x04 — Vertical Delay Register, Lower Byte (VDELAY_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x16. VDELAY_LO(0) is the least significant bit. This 8-bit register is the lower byte of the 10-bit VDELAY register. The two MSB’s of VDELAY are contained in the CROP register. VDELAY defines the number of half lines between the trailing edge of VRESET and the start of active video. VDELAY_LO 0x01–0xFF = The least significant byte of the vertical delay register. 7 6 5 4 3 2 1 0 VDELAY_MSB VACTIVE_MSB HDELAY_MSB HACTIVE_MSB 00010010 7 6 5 4 3 2 1 0 VDELAY_LO 00010110

C ONTROL REGISTER DEFINITIONS 0x05 — Vertical Active Register, Lower Byte (VACTIVE_LO)Bt819A/7A/5A 0x05 — Vertical Active Register, Lower Byte (VACTIVE_LO) This control register may be written to or read by the MPU at any time, and upon reset it is initialized to 0xE0. V ACTIVE_LO(0) is the least significant bit. This 8-bit register is the lower byte of the 10-bit V ACTIVE register. The two MSB’s of V ACTIVE are contained in the CROP register. V ACTIVE defines the number of lines used in the ver- tical scaling process. The actual number of lines output by the Bt819A is SCALING_RATIO * V ACTIVE. VACTIVE_LO 0x00–0xFF = The least significant byte of the vertical active register. 0x06 — Horizontal Delay Register, Lower Byte (HDELAY_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x78. HDELAY_LO(0) is the least significant bit. This 8-bit register is the lower byte of the 10-bit HDELAY register. The two MSB’s of HDELAY are contained in the CROP register. HDELAY defines the number of scaled pixels between the falling edge of HRESET and the start of active video. HDELAY_LO 0x01–0xFF = The least significant byte of the horizontal delay register. HACTIVE pixels will be output by the chip starting at the fall of HRESET. Caution: HDELAY must be programmed with an even number. 0x07 — Horizontal Active Register, Lower Byte (HACTIVE_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x80. HACTIVE_LO(0) is the least significant bit. HACTIVE defines the number of horizontal active pixels per line output by the Bt819A. HACTIVE_LO 0x00–0xFF = The least significant byte of the horizontal active register. This 8-bit register is the lower byte of the 10-bit HACTIVE register. The two MSB’s of HAC- TIVE are contained in the CROP register. 7 6 5 4 3 2 1 0 VACTIVE_LO 11100000 7 6 5 4 3 2 1 0 HDELAY_LO 01111000 7 6 5 4 3 2 1 0 HACTIVE_LO 10000000

C ONTROL REGISTER DEFINITIONS 0x08 — Horizontal Scaling Register, Upper Byte (HSCALE_HI) Bt819A/7A/5A 0x08 — Horizontal Scaling Register, Upper Byte (HSCALE_HI) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x02. This 8-bit register is the upper byte of the 16-bit HSCALE register. HSCALE_HI 0x00–0xFF = The most significant byte of the horizontal scaling ratio 0x09 — Horizontal Scaling Register, Lower Byte (HSCALE_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0xAC. This 8-bit register is the lower byte of the 16-bit HSCALE register. HSCALE_LO 0x00–0xFF = The least significant byte of the horizontal scaling ratio 7 6 5 4 3 2 1 0 HSCALE_HI 00000010 7 6 5 4 3 2 1 0 HSCALE_LO 10101100

C ONTROL REGISTER DEFINITIONS 0x0A — Brightness Control Register (BRIGHT)Bt819A/7A/5A 0x0A — Brightness Control Register (BRIGHT) The brightness control involves the addition of a two’s complement number to the luma channel. Brightness can be adjusted in 255 steps, from –128 to +127. The resolution of brightness change is one LSB (0.39% with respect to the full luma range). BRIGHT 7 6 5 4 3 2 1 0 BRIGHT 00000000 Hex Value Binary Value Brightness Changed By Number of LSBs Percent of Full Scale 0x80 1000 0000 –128 –50% 0x81 1000 0001 –127 –49.6% 0xFF 1111 1111 –01 –0.39% 0x00* 0000 0000* 00 0% 0x01 0000 0001 +01 +0.39% 0x7E 0111 1110 +126 +49.2% 0x7F 0111 1111 +127 +49.6%

C ONTROL REGISTER DEFINITIONS 0x0B — Miscellaneous Control Register (CONTROL) Bt819A/7A/5A 0x0B — Miscellaneous Control Register (CONTROL) This control register may be written to or read by the MPU at any time, and upon reset it is initialized to 0x20. SAT_V_MSB is the least significant bit. LNOTCH This bit is used to include the luma notch filter. For monochrome video, the notch should not be used. This will output full bandwidth luminance. 0* = Enable the luma notch filter 1 = Disable the luma notch filter COMP When COMP is set to logical one, the luma notch is disabled. When COMP is set to logical zero, the C ADC is disabled. When using the Bt815A, this bit must be programmed with a zero. ** Bt819A and Bt817A only. 0* = Composite Video 1 = Y/C Component Video LDEC The luma decimation filter is used to reduce the high-frequency component of the luma signal. Useful when scaling to CIF resolutions or lower. 0 = Enable luma decimation 1* = Disable luma decimation CBSENSE This bit controls whether the first pixel of a line is a Cb pixel or a Cr pixel. For ex- ample, if CBSENSE is low and HDELAY is an even number, the first active pixel output is a Cb pixel. If HDELAY is odd, CBSENSE may be programmed high to produce a Cb pixel as the first active pixel output. 0* = Normal CbFLAG (high for the 1st pixel of line) 1 = Invert the CbFLAG polarity INTERP This is primarily a test mode. The interpolator should always be enabled. 0* = Enable interpolation 1 = Disable interpolation CON_MSB The most significant bit of the luma gain (contrast) value SAT_U_MSB The most significant bit of the chroma (u) gain value SAT_V_MSB The most significant bit of the chroma (v) gain value 7 6 5 4 3 2 1 0 LNOTCH COMP** LDEC CBSENSE INTERP CON_MSB SAT_U_MSB SAT_V_MSB 001000 0 0

C ONTROL REGISTER DEFINITIONS 0x0C — Luma Gain Register, Lower Byte (CONTRAST_LO)Bt819A/7A/5A 0x0C — Luma Gain Register, Lower Byte (CONTRAST_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0xD8. CONTRAST_LO(0) is the least significant bit. The CON_L_MSB bit and the CONTRAST_LO register concatenate to form the 9-bit CONTRAST register. The value in this register is multiplied by the luminance value to provide con- trast adjustment. CONTRAST_LO The least significant byte of the luma gain (contrast) value. 7 6 5 4 3 2 1 0 CONTRAST_LO 11011000 Decimal Value Hex Value % of Original Signal 511 0x1FF 236.57% 510 0x1FE 236.13% 217 0x0D9 100.46% 216 0x0D8* 100.00% 128 0x080 59.26% 1 0x001 0.46% 0 0x000 0.00%

C ONTROL REGISTER DEFINITIONS 0x0D — Chroma (U) Gain Register, Lower Byte (SAT_U_LO) Bt819A/7A/5A 0x0D — Chroma (U) Gain Register, Lower Byte (SAT_U_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0xFE. SAT_U_LO(0) is the least significant bit. SAT_U_MSB in the CONTROL register, and SAT_U_LO concatenate to give a 9-bit register (SAT_U). This register is used to add a gain adjustment to the U component of the video signal. By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted. For normal saturation adjustment, the gain in both the color difference paths must be the same (i.e. the ratio between the value in the U gain register and the value in the V gain register should be kept constant at the default power-up ratio). When changing the saturation, if the SAT_U_MSB bit is altered, care must be taken to ensure that the other bits in the CONTROL register are not affected. SAT_U_LO 7 6 5 4 3 2 1 0 SAT_U_LO 11111110 Decimal Value Hex Value % of Original Signal 511 0x1FF 201.18% 510 0x1FE 200.79% 255 0x0FF 100.39% 254 0x0FE* 100.00% 128 0x080 50.39% 1 0x001 0.39% 0 0x000 0.00%

C ONTROL REGISTER DEFINITIONS 0x0E — Chroma (V) Gain Register, Lower Byte (SAT_V_LO)Bt819A/7A/5A 0x0E — Chroma (V) Gain Register, Lower Byte (SAT_V_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0xB4. SAT_V_LO(0) is the least significant bit. SAT_V_MSB in the CONTROL register and SAT_V_LO concatenate to give a 9-bit register (SAT_V). This register is used to add a gain adjustment to the V component of the video signal. By adjusting the U and V color components of the video stream by the same amount, the saturation is adjusted. For normal saturation adjustment, the gain in both the color difference paths must be the same (i.e. the ratio between the value in the U gain register and the value in the V gain register should be kept constant at the default power-up ratio). When changing the saturation, if the SAT_V_MSB bit is altered, care must be taken to ensure that the other bits in the CONTROL register are not affected. SAT_V_LO 7 6 5 4 3 2 1 0 SAT_V_LO 10110100 Decimal Value Hex Value % of Original Signal 511 0x1FF 283.89% 510 0x1FE 283.33% 181 0x0B5 100.56% 180 0x0B4* 100.00% 128 0x080 71.11% 1 0x001 0.56% 0 0x000 0.00%

C ONTROL REGISTER DEFINITIONS 0x0F — Hue Control Register (HUE) Bt819A/7A/5A 0x0F — Hue Control Register (HUE) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00. HUE(0) is the least significant bit. An asterisk indicates the default option. Hue adjustment involves the addition of a two’s complement number to the demodulating subcarrier phase. Hue can be adjusted in 256 steps in the range –90˚ to +89.3˚, in increments of 0.7˚. HUE 7 6 5 4 3 2 1 0 HUE 00000000 Hex Value Binary Value Subcarrier Reference Changed By Resulting Hue Changed By 0x80 1000 0000 –90˚ +90˚ 0x81 1000 0001 –89.3˚ +89.3˚ 0xFF 1111 1111 –0.7˚ +0.7˚ 0x00* 0000 0000* 00˚ 00˚ 0x01 0000 0001 +0.7˚ –0.7˚ 0x7E 0111 1110 +88.6˚ –88.6˚ 0x7F 0111 1111 +89.3˚ –89.3˚

C ONTROL REGISTER DEFINITIONS 0x10 — ReservedBt819A/7A/5A 0x10 — Reserved This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00, and must only be written to with 0x00. 0x11 — Reserved This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00, and must only be written to with 0x00.

C ONTROL REGISTER DEFINITIONS 0x12 — Output Format Register (OFORM) Bt819A/7A/5A 0x12 — Output Format Register (OFORM) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x06. FULL is the least significant bit. An asterisk indicates the default option. RANGE Luma Output Range: This bit determines the range for the luminance output on the Bt819A. The range must be limited when using the control codes as video timing. 0* = Normal operation (Luma range 16–253, chroma range 2–253). Y=16 is black (pedestal). Cr, Cb=128 is zero color information. 1 = Full-range Output (Luma range 0–255, chroma range 2–253) Y=0 is black (pedestal). Cr, Cb=128 is zero color information. RND Output Rounding: These bits control the number of bits output from the Bt819A, MSB justified. When rounding is implemented, the unused LSBs are set to zero. 00* = Normal Operation 01 = 6-bit Luma & 4-bit Chroma Output (Rounded) 10 = 7-bit Luma & 5-bit Chroma Output (Rounded) 11 = Reserved FIFO_BURST FIFO Read Control: When enabled, this pin internally connects RDEN to DV ALID. In API mode, when these pins are connected, the data is automatically burst out of the FIFO. If these pins are not connected, the system must control reads from the FIFO, and ensure the data does not overflow. Reads and writes to this bit are ignored on the Bt817A and Bt815A. ** Applies only to Bt819A. 0* = Internally Feedback DV ALID to RDEN 1 = Control RDEN externally CODE Code Control Disable: This bit determines if control codes are output with the vid- eo data. SPI mode 2 requires this bit to be programmed with a logical 1. When con- trol codes are inserted into the data stream, the external control signals are still available. 0* = Disable control code insertion 1 = Enable control code insertion 7 6 5 4 3 2 1 0 RANGE RND FIFO_BURST CODE LEN SPI FULL 00 0 0 0110

C ONTROL REGISTER DEFINITIONS 0x12 — Output Format Register (OFORM)Bt819A/7A/5A LEN Eight or Sixteen Bit Format: This bit determines the output data format. In 8-bit mode, the data is output on VD[15:8]. 0 = 8-bit YCrCb 4:2:2 output stream 1* = 16-Bit YCrCb 4:2:2 output stream SPI Pixel Interface Control: When programmed with a logical zero, the data is output using the FIFO in API mode. When programmed with a logical one, the FIFO is bypassed and the data is output in SPI mode. On the Bt817A and Bt815A, this bit must be loaded with a logical one. ** Applies only to Bt819A. 0 = Asynchronous pixel interface 1* = Synchronous pixel interface FULL This bit controls the point at which the FIFO full flag toggles. When programmed with a logical zero, the FIFO signals that it is half full by setting AFF high at 20 pixels (out of a possible 40). When programmed with a logical one, AFF toggles high at 32 pixels indicating that the FIFO is approaching full. Writes and reads to this pin are ignored on the Bt817A and Bt815A. 0* = AFF and DV ALID go high when there are at least 20 pixels in the output FIFO. 1 = AFF and DV ALID go high when there are at least 32 pixels in the output FIFO. Y/Cr/Cb[7] Y/Cr/Cb[0] Y[7] Y[0] VD[15] VD[8] VD[7] VD[0] Cr/Cb[7] Cr/Cb[0] VD 16-bit 8-bit

C ONTROL REGISTER DEFINITIONS 0x13 — Vertical Scaling Register, Upper Byte (VSCALE_HI) Bt819A/7A/5A 0x13 — Vertical Scaling Register, Upper Byte (VSCALE_HI) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x60. LINE Line Store Enable: This bit enables operation of the line store for use in vertical scaling. When enabled, the luminance component of the video signal is scaled us- ing two-tap, poly-phase scaling. When disabled, simple line dropping is imple- mented. Reads and writes to this bit are ignored on the Bt817A and Bt815A. ** Applies to Bt819A only. 0* = Luma VS using Line Store 1 = Luma VS using DDA COMB Chroma Comb Enable: This bit determines if the chroma comb is included in the data path. If enabled, a full line store is used to average adjacent lines of color in- formation, reducing cross-color artifacts. The chroma comb is available on all three parts (Bt819A, Bt817A and Bt815A). 0 = Chroma comb disabled 1* = Chroma comb enabled INT Interlace: This bit is programmed to indicate if the incoming video is interlaced or non-interlaced. For example, if using the full frame as input for vertical scaling, this bit should be programmed high. If using a single field for vertical scaling, this bit should be programmed low. Single field scaling is normally used when scaling below CIF resolution and outputting to a non-interlaced monitor. Using a single field will reduce motion artifacts. 0 = Non-interlace VS 1* = Interlace VS VSCALE_HI Vertical Scaling Ratio: These five bits represent the most significant portion of the 13-bit vertical scaling ratio register. The system must take care not to alter the con- tents of the LINE, COMB and INT bits while adjusting the scaling ratio. 7 6 5 4 3 2 1 0 LINE** COMB INT VSCALE_HI 01100000

C ONTROL REGISTER DEFINITIONS 0x14 — Vertical Scaling Register, Lower Byte (VSCALE_LO)Bt819A/7A/5A 0x14 — Vertical Scaling Register, Lower Byte (VSCALE_LO) This control register may be written to or read by the MPU at any time. Upon reset it is initialized to 0x00. VSCALE_LO Vertical Scaling Ratio: These eight bits represent the least significant byte of the 13-bit vertical scaling ratio register. They are concatenated with five bits in VSCALE_HI. The following equation should be used to determine the value for this register: For example, to scale PAL input to square pixel QCIF, the total number of vertical lines is 156: 7 6 5 4 3 2 1 0 VSCALE_LO 00000000 VSCALE = ( 0x10000 – { [ ( scaling_ratio ) – 1] * 512 } ) & 0x1FFF VSCALE = ( 0x10000 – { [ ( 4/1 ) - 1 ] * 512 } ) & 0x1FFF = 0x1A00

C ONTROL REGISTER DEFINITIONS 0x15 — Test Control Register (TEST) Bt819A/7A/5A 0x15 — Test Control Register (TEST) This control register is reserved for putting the part into test mode. Write operation to this register may cause unde- termined behavior and should not be attempted. A read cycle from this register returns 0x01, and only a write of 0x01 is permitted. 0x16 — Video Timing Polarity Register (VPOLE) This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x00. OUTEN Three-states the following pins: VD[15:0], HRESET, VRESET , ACTIVE, DV ALID, CBFLAG, FIELD, AEF, AFF, QCLK, CLKx1, and CLKx2. 0* = Enable Outputs 1 = Three-stated outputs DVALID 0* = DV ALID Pin: Active high 1 = DV ALID Pin: Active low AFF ** This bit applies only to the Bt819A. Reads and writes to this bit are ignored on the Bt817A and Bt815A. 0* = AFF Pin: Active high 1 = AFF Pin: Active low CBFLAG 0* = CBFLAG Pin: Active high 1 = CBFLAG Pin: Active low FIELD 0* = FIELD Pin: High indicates odd field 1 = FIELD Pin: High indicates even field ACTIVE 0* = ACTIVE Pin: Active high 1 = ACTIVE Pin: Active low HRESET 0* = HRESET Pin: Active low 1 = HRESET Pin: Active high VRESET 0* = VRESET Pin: Active low 1 = VRESET Pin: Active high Note: In API mode, the FIELD, V ALID and AFF pins do not have programmable polar- ities. They are programmable only in SPI mode. 7 6 5 4 3 2 1 0 OUT_EN DVALID AFF** CBFLAG FIELD ACTIVE HRESET VRESET 00000000

C ONTROL REGISTER DEFINITIONS 0x17 — ID Code Register (IDCODE)Bt819A/7A/5A 0x17 — ID Code Register (IDCODE) This control register may be read by the MPU at any time. IDCODE(0) is the least significant bit. PART_ID PART_REV 0x0 – 0xF = Current Revision ID Code 0x18 — AGC Delay Register (ADELAY) This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x68. ADELAY AGC gate delay for back-porch sampling. The following equation should be used to determine the value for this register: For example, for an NTSC input signal: 7 6 5 4 3 2 1 0 PART_ID PART_REV 01110000

0111 Bt819A Part ID Code

0110 Bt817A Part ID Code

0010 Bt815A Part ID Code

ADELAY = ( 6.8 mS * fCLKx1 ) + 7 ADELAY = ( 6.8 mS * 14.32 MHz ) + 7 = 104 (0x68)

C ONTROL REGISTER DEFINITIONS 0x19 — Burst Delay Register (BDELAY) Bt819A/7A/5A 0x19 — Burst Delay Register (BDELAY) This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x5D. BDELAY(0) is the least significant bit. BDELAY The burst gate delay for sub-carrier sampling. The following equation should be used to determine the value for this register: For example, for an NTSC input signal: 7 6 5 4 3 2 1 0 BDELAY 01011101 BDELAY = ( 6.5 mS * fCLKx1 ) BDELAY = ( 6.5 mS * 14.32 MHz ) = 93 (0x5D)

C ONTROL REGISTER DEFINITIONS 0x1A — ADC Interface Register (ADC)Bt819A/7A/5A 0x1A — ADC Interface Register (ADC) This control register may be written to or read by the MPU at any time. Upon reset, it is initialized to 0x82. ADC(0) is the least significant bit. CLAMP 00 = Clamp on the Back Porch to 0x30 01 = Clamp on the Back Porch to 0x34 10* = Clamp on the Back Porch to 0x38 11 = Clamp on the Back Porch to 0x3C SYNC_T 0* = Analog SYNCDET threshold high (~125 mV) 1 = Analog SYNCDET threshold low (~75 mV) AGC_EN 0* = AGC Enabled 1 = AGC Disabled CLK_SLEEP Output clocks are still running, I2C registers are still accessible. Recovery time is approximately one second. 0* = Normal Clock Operation 1 = Shut down the System Clock (Power Down) Y_SLEEP 0* = Normal Y ADC operation 1 = Sleep Y ADC operation C_SLEEP ** Applies only to Bt819A and Bt817A. Reads and writes to this bit are ignored on Bt815A. 0 = Normal C ADC operation 1* = Sleep C ADC operation Reserved This bit should only be written with a logical zero. 7 6 5 4 3 2 1 0 CLAMP SYNC_T AGC_EN CLK_SLEEP Y_SLEEP C_SLEEP** Reserved 10000010

C ONTROL REGISTER DEFINITIONS 0x1B to 0x1E — Reserved Registers Bt819A/7A/5A 0x1B to 0x1E — Reserved Registers These control registers are reserved for future use. Write operations to these registers may cause undetermined be- havior and should not be attempted. A read cycle from these registers returns an undefined value. 0x1F — Software Reset Register (SRESET) This command register can be written at any time. Read cycles to this register return an undefined value. A data write cycle to this register resets the device to the default state (indicated in the command register definitions by an aster- isk). Writing any data value into this address resets the device.

Table 14. Recommended Operating Conditions Table 15. Absolute Maximum Ratings is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. below ground by more than 0.5 V can induce destructive latchup.

Table 16. DC Characteristics Table 17. Clock Timing Parameters

Figure 37. Clock Timing Diagram

Table 18. Power Supply Current Parameters Table 19. Output Enable Timing Parameters Figure 38. Output Enable TIming Diagram

Table 20. JTAG Timing Parameters Figure 39. JTAG TIming Diagram

Table 21. FIFO Timing Parameters (Bt819A Only) Figure 40. FIFO Output Timing Diagram Table 22. Decoder Performance Parameters

Figure 41. 100PQFP Package Mechanical Drawing

Figure 42. 100TQFP Package Mechanical Drawing

Table 23. Bt819A Datasheet Revision History (1 of 2) clock after DVALID transitions low. been added to the API section of the datasheet.

between Bt819, Bt817 and Bt815. as they offer very short lead times. field is field 2, and the odd field is field 1. 6) API mode-A change: CLKIN must be connected to CLKx1. empty, during the active video line. 9) Example schematic in Figure 36 changed to reflect Bt819A. 12) The timing from QCLK to Data Valid in 8-bit mode was changed. Table 23. Bt819A Datasheet Revision History

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