BT169

UTCBT169 UTC | Alldatasheet

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UTC UNISONIC TECHNOLOGIES CO., LTD. 1

DESCRIPTION

The UTC BT169 is glass passivated, sensitive gate thyristors in a plastic envelope, intended for use in general purpose switching and phase control applications. These devices are intended to be interfaced directly to microcontrollers, logic integrated circuits and other low power gate trigger circuits. TO-92 1:CATHODE 2:GATE 3:ANODE QUICK REFERENCE DATA PARAMETER SYMBOL MAX( B ) MAX(D) MAX( E ) MAX(G) UNIT Repetitive peak off-state voltages V DRM , V RRM 200 400 500 600 V Average on-state current IT( AV) 0.5 0.5 0.5 0.5 A RMS on-state current IT( RMS) 0.8 0.8 0.8 0.8 A Non-repetitive peak on-state current ITSM 8 8 8 8 A ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Repetitive peak off-state voltages : V DRM ,V RRM B:200 D:400 E:500 G:600 V Average on-state current IT( AV) Half sine wave; Tlead<=83 °C 0.5 A RMS on-state current IT( RMS) All conduction angles 0.8 A Non-repetitive peak on-state current ITSM t=10ms t=8.3ms half sine wave; Tj=25 °C prior to surge A I2 t for fusing I2 t t=10ms 0.32 A 2 S Repetitive rate of rise of on-state current after triggering DI T /dt ITM =2A;I G =10mA; dI G /dt=100mA/ µs

50 A/ µs

Peak gate voltage V GM 5 V Peak reverse gate voltage V RGM 5 V

UTC UNISONIC TECHNOLOGIES CO., LTD. 2 PARAMETER SYMBOL CONDITIONS MIN MAX UNIT Peak gate power P GM 2 W Average gate power P G( AV) Over any 20 ms period 0.1 W Storage temperature Tstg -40 150 °C Operating junction temperature Tj 125 °C THERMAL RESISTANCES PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Thermal resistance junction to lead Rth j-lead 60 K/W Thermal resistance junction to ambient Rth j-a pcb mounted; lead length=4mm

150 K/W

ELECTRICAL CHARACTERISTICS (Tj=25 °C unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT STATIC Gate trigger current IGT V D =12V;IT=10mA;gate open circuit 50 200 µA Latching current IL V D =12V;I GT =0.5mA; R GK =1k Ω 2 6 mA Holding current IH V D =12V;I GT =0.5mA; R GK =1k Ω 2 5 mA On-state voltage V T IT =1A 1.2 1.35 V Gate trigger voltage V GT V D =12V;I T =10mA; gate open circuit V D =V DRM(max) ;IT=10mA ; Tj=125 °C; gate open circuit 0.2 0.5 0.3 0.8 V Off-state leakage current ID ,I R V D =V DRM(max) ;V R =V RRM(m ax) ;Tj=125 °C;R GK =1k Ω 0.05 0.1 mA DYNAMIC Ciritical rate of rise of off-state voltage dV D /dt V DM =67% V DRM(max) ; Tj=125 °C; exponential waveform;R GK =1k Ω

25 V/ µs

Gate controlled turn-on time tgt ITM =2A;V D =V DRM (max); IG =10mA;dI G /dt=0.1A/ µs 2 µs Circuit commutated turn-off time tq V D =67% V DRM(max) ; Tj=125 °C ;I TM =1.6A;V R =35V ;dI TM /dt=30A/ µs; V D /dt=2V/ µs;R GK =1k Ω 100 µs

UTC UNISONIC TECHNOLOGIES CO., LTD. 3 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 119 125 113 107 101 77conduction angle degrees form factor a 120 180 2.8 2.2 1.9 1.57 2.8 2.2 1.9 a=1.57 Tc(max) / C IF(AV) / A FIG.1 Maximum on-state dissipation, P tot , versus average on-state current, I T(AV) , where a=form factor=I T(RMS) / I T(AV) P tot / W 10 µs 100 1000 T / s FIG.2 Maximum permissible non-repetitive peak on-state current ITSM ,versus pulse width tp,for sinusoidal currents, t p <=10ms. ITSM / A 100 µs 1 ms 10 ms ITSMIT time Tj initial=25 ¢XC max T 50 100 150 0.2 0.4 0.6 0.8 1.0 Tlead / C FIG.3 Maximum permissible rms current I T(RMS) , versus lead temperature, Tlead IT(RMS) / A -50 0 83 ¢XC Number of half cycles at 50Hz FIG.4 Maximnum permissible non-repetitive peak on-state current ITSM , versus number of cycles, for sinusoidal currents, f = 50Hz. ITSM / A 10 100 1000 ITSMI T time Tj initial=25 ¢XC max T 0.01 0.5 1.0 surge duration / s FIG.5 Maximum permissible repetitive rms on-state current I T(RMS) , versus surge duration, for sinusoidal currents, f= 50Hz; Tlead<=83 ¢XC IT(RMS) / A 0.1 1.0 10 1.5 2.0 0.4 50 100 150 0.6 0.8 1.0 1.4 1.6 Tj / C FIG.6 Normalised gate trigger voltage V GT (Tj)/V GT( 25 ¢XC), versus junction temperature Tj VGT(Tj) VGT(25 ¢XC) -50 0 1.2

UTC UNISONIC TECHNOLOGIES CO., LTD. 4 50 150 1000 Tj / C FIG.12 Typical, critical rate of rise of off-state voltage, dV D /dt versus junction temperature Tj. dVD/dt(V/us) 0 0 100 50 100 150 0.5 1.0 1.5 2.5 3.0 Tj / C FIG.7 Normalised gate trigger current I GT (Tj)/I GT (25 ¢XC), versus junction temperature Tj IGT(Tj) VGT(25 ¢XC) -50 0 2.0 50 100 150 Tj / C FIG.8 Normalised latching current I L( Tj)/I L (25 ¢XC),versus junction temperature Tj, R GK = 1K Ω IL(Tj) IL(25 ¢XC) -50 0 50 100 150 Tj / C FIG.9 Normalised holding current I H (Tj)/I H (25 ¢XC),versus junction temperature Tj, R GK =1K Ω IH(Tj) IH(25 ¢XC) -50 0 0.5 1.0 1.5 2.5 3.0 2.0 0.5 1.0 1.5 2.5 3.0 2.0 1.0 1.5 2.0 VT / V FIG.10 Typical and maximum on-state characteristic. IT / A 0 0.5 Tj=125 ¢XC - - - Tj= 25 ¢XC Vo=1.067V Rs=0.187 Ω typ max 10us 0.01 0.1 tp / s FIG.11 Transient thermal impedance Zth j-lead, versus pulse width tp. Zth j-lead (K/W) 1ms 0.1s 10s 100 0.1ms 10ms 1s tpPD t RGK=1K Ω