BS320GTD8V

AM29BDS320G SPANSION | Alldatasheet

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October 1, 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am29BDS320G Data Sheet Publication Number 27243 Revision B Amendment 1 Issue Date October 1, 2003

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Publication Number 27243 Revision B Amendment 1 Issue Date October 1, 2003 PRELIMINARY Am29BDS320G 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory Data Sheet Distinctive Characteristics Architectural Advantages „ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) „ Manufactured on 0.17 µm process technology „ Enhanced VersatileIO™ (V IO) Feature — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin — 1.8V and 3V compatible I/O signals „ Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture: 8Mb/8Mb/8Mb/8Mb „ Programmable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst „ Sector Architecture — Eight 8 Kword sectors and sixty-two 32 Kword sectors — Banks A and D each contain four 8 Kword sectors and fifteen 32 Kword sectors; Banks B and C each contain sixteen 32 Kword sectors — Eight 8 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range „ Minimum 1 million erase cycle guarantee per sector „ 20-year data retention at 125°C — Reliable operation for the life of the system „ 64-ball FBGA package Performance Charcteristics „ Read access times at 54/40 MHz (at 30 pF) — Burst access times of 13.5/20 ns — Asynchronous random access times of 70 ns — Initial Synchronous access times as fast as 87.5/95 ns „ Power dissipation (typical values, CL = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA —S t a n d b y m o d e : 0 . 2 µ A Hardware Features „ Sector Protection — Software command sector locking „ Reduced Wait-State Handshaking feature available — Provides host system with minimum possible latency by monitoring RDY „ Hardware reset input (RESET#) — Hardware method to reset the device for reading array data „ WP# input — Write protect (WP#) function protects sectors 0 and 1 (bottom boot), or sectors 68 and 69 (top boot), regardless of sector protect status „ ACC input: Acceleration function reduces programming time; all sectors locked when ACC = V IL „ CMOS compatible inputs, CMOS compatible outputs „ Low VCC write inhibit Software Features „ Supports Common Flash Memory Interface (CFI) „ Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families „ Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion „ Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation „ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences

2A m 2 9 B D S 3 2 0 G 27243B1 October 1, 2003 Preliminary General Description The Am29BDS320G is a 32 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 2,097,152 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the mem- ory array. The device supports Enhanced VIO to offer up to 3V compatible inputs and outputs. A 12.0-volt VID may be used for faster program performance if de- sired. The device can also be programmed in standard EPROM programmers. At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30 pF with a latency of 95 ns at 30 pF. The device operates within the industrial tem- perature range of -40°C to +85°C. The device is offered in the 64-ball FBGA package. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: The Enhanced VersatileIO™ (V IO) control allows the host system to set the volt- age levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the V IO pin. This allows the device to operate in 1.8 V and 3 V system environments as required. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the bu rst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single- power-supply Flash standard. Commands are written to the command regis- ter using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Bank Quantity Size A

48 K w o r d s

D 15 32 Kwords

October 1, 2003 27243B1 Am29BDS320G 3 Preliminary Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read b oot-up firmware from the Flash memory device. The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automat- ically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. The sector lock/unlock com- mand sequence disables or re-enables both program and erase operations in any sector. When at V IL, WP# locks sectors 0 and 1 (bottom boot device) or sec- tors 68 and 69 (top boot device). The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consump- tion is greatly reduced in both modes. Spansion flash technology combines years of flash memory manufacturing expe- rience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler- Nordheim tunnelling. The data is programmed using hot electron injection.

6A m 2 9 B D S 3 2 0 G 27243B1 October 1, 2003 Preliminary Product Selector Guide Notes: 1. Speed Options ending in “3” and “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous accesses for even addresses. 2. Speed Options ending in “4” and “9” indicate the “standard handshaking” option. 3. See the AC Characteristics section of th is data sheet for full specifications. Part Number Am29BDS320G Burst Frequency 54 MHz 40 MHz Speed Option VCC = 1.65 – 1.95 V, VIO = 2.7 – 3.15 V D3, D4 C3, C4 VCC, VIO = 1.65 – 1.95 V D8, D9 C8, C9 Max Initial Synchronous Access Time, ns (tIACC) Reduced Wait-state Handshaking: Even Address 87.5 95 Max Initial Synchronous Access Time, ns (tIACC) Reduced Wait-state Handshaking: Odd Address; or Standard Handshaking 106 120 Max Burst Access Time, ns (tBACC) 13.5 20 Max Asynchronous Access Time, ns (tACC) 70 90 Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) 13.5 20

October 1, 2003 27243B1 Am29BDS320G 7 Preliminary Block Diagram Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS VIO WE# RESET# WP# ACC CE# OE# DQ15–DQ0 Data Latch Y-Gating Cell Matrix Address Latch A20–A0 RDY Buffer RDY Burst State Control Burst Address Counter AVD# CLK

8A m 2 9 B D S 3 2 0 G 27243B1 October 1, 2003 Preliminary Block Diagram of Simultaneous Operation Circuit VSS VCC VIO Bank B Address RESET# ACC WE# CE# AVD# RDY DQ15–DQ0 WP# STATE CONTROL COMMAND REGISTER Bank B X-Decoder Y-Decoder Latches and Control Logic Bank A X-Decoder Y-Decoder Latches and Control Logic DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Bank C Y-Decoder X-Decoder Latches and Control Logic Bank D Y-Decoder X-Decoder Latches and Control Logic OE# Status Control A20–A0 A20–A0 A20–A0 A20–A0 A20–A0 Bank C Address Bank D Address Bank A Address

October 1, 2003 27243B1 Am29BDS320G 9 Preliminary Connection Diagram Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultra- sonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged peri- ods of time. A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 A7 B7 C7 D7 E7 F7 G7 H7 DQ15 V SSNCA16A15A14A12A13 A8 B8 C8 D8 E8 F8 G8 H8 NC NCNCVSSVIONCNCNC DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18ACCRDY DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 A1 B1 C1 D1 E1 F1 G1 H1 VSS NCVIOAVD#WP#CLKVCCNC 64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)

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A20-A0 = Address inputs DQ15-DQ0 = Data input/output CE# = Chip Enable input. Asynchronous relative to CLK for the Burst mode. OE# = Output Enable input. Asynchronous relative to CLK for the Burst mode. WE# = Write Enable input. V CC = Device Power Supply (1.65 – 1.95 V). VIO = Input & Output Buffer Power Supply (either 1.65 – 1.95 V or 2.7 – 3.15 V). VSS = Ground NC = No Connect; not connected internally RDY = Ready output; indicates the status of the Burst read. Low = data not valid at expected time. High = data valid. CLK = CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. AVD# = Address Valid input. Indicates to device that the valid address is present on the address inputs (A20–A0). Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. High = device ignores address inputs RESET# = Hardware reset input. Low = device resets and returns to reading array data WP# = Hardware write protect input. At V IL, disables program and erase functions in the two outermost sectors. Should be at V IH for all other conditions. ACC = At V ID, accelerates programming; automatically places device in unlock bypass mode. At VIL, locks all sectors. Should be at VIH for all other conditions. Logic Symbol DQ15–DQ0 A20–A0 CE# OE# WE# RESET# CLK RDY AVD# WP# ACC

October 1, 2003 27243B1 Am29BDS320G 11 Preliminary

Ordering Information

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local sales office or representative to confirm availability of specific valid combinations and to check on newly released combinations. Note: For the Am29BDS320G, the last digit of the speed grade specifies the V IO range of the device. Speed options ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt VIO range. Speed grades ending in “3” and “4” (e.g., D3, D4) indicate a 3.0 Volt VIO range. Am29BDS320G T D 8 VM I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE VM = 64-Ball Fine-Pitch Grid Array (FBGA) 0.80 mm pitch, 8 x 9 mm package (VBD064) VIO AND HANDSHAKING FEATURES 8 = 1.8 V VIO, reduced wait-state handshaking 9 = 1.8 V VIO, standard handshaking 3 = 3 V VIO, reduced wait-state handshaking 4 = 3 V VIO, standard handshaking CLOCK RATE/ASYNCHRONOUS SPEED D = 54 MHz/70 ns C = 40 MHz/90 ns BOOT CODE SECTOR ARCHITECTURE T = Top boot sector B = Bottom boot sector DEVICE NUMBER/DESCRIPTION Am29BDS320G

32 Megabit (2 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write,

Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase Valid Combinations Burst Frequency (MHz) VIO Range Order Number Package Marking Am29BDS320GTD8 Am29BDS320GBD8 VMI BS320GTD8V BS320GBD8V 1.65–1.95V Am29BDS320GTD9 Am29BDS320GBD9 BS320GTD9V BS320GBD9V Am29BDS320GTC8 Am29BDS320GBC8 BS320GTC8V BS320GBC8V Am29BDS320GTC9 Am29BDS320GBC9 BS320GTC9V BS320GBC9V Am29BDS320GTD3 Am29BDS320GBD3 VMI BS320GTD3V BS320GBD3V 2.7–3.15V Am29BDS320GTD4 Am29BDS320GBD4 BS320GTD4V BS320GBD4V Am29BDS320GTC3 Am29BDS320GBC3 BS320GTC3V BS320GBC3V Am29BDS320GTC4 Am29BDS320GBC4 BS320GTC4V BS320GBC4V

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This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com- posed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machin e. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and con- trol levels they require, and the resu lting output. The following subsections describe each of these operations in further detail. Ta b l e 1 . Device Bus Operations Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. Enhanced VersatileIO™ (VIO) Control The Enhanced VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data and address inputs to the same voltage level that is asserted on the V IO device to operate in 1.8 V or 3 V system environments as required. For example, a VIO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving and receiving signals to and from other 3 V devices on the same bus. Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must first assert a valid address on A20–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0. Operation CE# OE# WE# A20–0 DQ15–0 RESET# CLK (See Note) AVD# Asynchronous Read - Addresses Latched L L H Addr In I/O H X Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L Asynchronous Write L H L Addr In I/O H L L Synchronous Write L H L Addr In I/O H Standby (CE#) H X X HIGH Z HIGH Z H X X Hardware Reset X X X HIGH Z HIGH Z L X X Burst Read Operations Load Starting Burst Address L X H Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus LLH H I G H Z Burst Data Out HH Terminate current Burst read cycle H X H HIGH Z HIGH Z H X Terminate current Burst read cycle via RESET# X X H HIGH Z HIGH Z L X X Terminate current Burst read cycle and start new Burst read cycle LXH H I G H Z I / O H

October 1, 2003 27243B1 Am29BDS320G 13 Preliminary Since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE) is the delay from the stable ad- dresses and stable CE# to valid data at the outputs. The output enable access time (t OE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. Requirements for Synchronous (Burst) Read Operation The device is capable of continuous sequential burst operation and linear burst operation of a preset length. When the device first powers up, it is enabled for asynchronous read operation. Prior to entering burst mode, the system should determine how many wait states are desired for the initial word (t IACC) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the RDY signal will transition with valid data. The system would then write the burst mode configuration register command sequence. See “Set Burst Mode Configuration Register Command Sequence” and “Command Definitions” for fur- ther details. Once the system has written the “Set Burst Mode Configuration Register” com- mand sequence, the device is enabled for synchronous reads only. The initial word is output t IACC after the active edge of the first CLK cycle. Sub- sequent words are output t BACC after the active edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003Fh. During the time the device is outputting data at this fixed internal address boundary (address 00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.). The RDY output indicates this condition to the system by pulsing low. For standard handshaking devices, there is no two cycle latency between 3Fh and 40h (or addresses offset from 3F and 40h by a multiple of 64). See Table 10. For reduced wait-state handshaking devices, if the address latched is 3Dh (or off- set from 3Dh by a multiple of 64), an additional cycle latency occurs prior to the initial access. If the address latched is 3Eh (or offset from 3Eh by a multiple of 64) two additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3Fh and 40h (or offset from 3Fh by a multiple of 64) will not oc- cur. For 3Fh latched addresses (or offset from 3Fh by a multiple of 64) three additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3Fh and 40h (or offset from these addresses by a multiple of 64) will not occur. The device will continue to output sequential burst data, wrapping around to ad- dress 000000h after it reaches the highest addressable memory location, until the system drives CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 1, “Device Bus Operations,” on page 12. If the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as de- scribed above in the subsequent bank. If the host system crosses the bank

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restart a burst operation using a new address and AVD# pulse. tional latencies will occur. RDY indicates the length of the latency by pulsing low. Table 2. Burst Address Groups (latching of a new address). and synchronous mode active. by the rising edge of RDY after OE# goes low.

October 1, 2003 27243B1 Am29BDS320G 15 Preliminary For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system mu st set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Burst Mode Configuration Register Command Se- quence” section on page 25 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Com- mand Sequence” section for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while program- ming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (ex- cept the sector being erased). Figure 33, “Back-to-Back Read/Write Cycle Timings,” on page 69 shows how read and write cycles may be initiated for simul- taneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asynchronous or synchronous write operation. During a synchronous write operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to V IL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. During an asynchronous write op- eration, the system must drive CE#, WE#, and CLK to VIL and OE# to VIH when providing an address, command, and data. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypa ss mode, only two write cycles are re- quired to program a word, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 8, “Programmable Wait State Settings,” on page 27 indicates the address space that each sector occupies. The de vice address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 8 Kword boot sectors in addition to 32 Kword sectors. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification ta- bles and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V ID on this input, the device automatically enters the afore- mentioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-

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cycle program command sequence as required by the Unlock Bypass mode. Re- moving VID from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VID. Note that the ACC pin must not be at VID for operations other than accelerated programming, or device dam- age may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at V IL, ACC locks all sectors. ACC should be at VIH for all other conditions. Autoselect Functions If the system writes the autoselect command sequence, the device enters the au- toselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15–DQ0. Autoselect mode may only be entered and used when in the asynchronous read mode. Refer to the “Autoselect Command Sequence” section on page 30 section for more information. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V CC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous mode, the device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. While in synchronous mode, the de- vice automatically enables this mode when either the first active CLK edge occurs after t ACC or the CLK runs slower than 5MHz. Note that a new burst operation is required to provide new data. ICC4 in the “DC Characteristics” section on page 44 represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t RP, the device im- mediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the de- vice is ready to accept another command sequence, to ensure data integrity.

October 1, 2003 27243B1 Am29BDS320G 17 Preliminary Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the device requires a time of t READY (during Embedded Algorithms) before the device is ready to read data again. If RESET# is asserted when a program or erase operation is not ex- ecuting, the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after RESET# returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 20, “Reset Timings,” on page 56 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14, “Command Definitions,” on page 36 for command definitions). The device offers two types of data protection at the sector level: „ The sector lock/unlock command sequence disables or re-enables both pro- gram and erase operations in any sector. „ When WP# is at V IL, sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot) are locked. „ When ACC is at VIL, all sectors are locked. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Write Protect (WP#) The Write Protect (WP#) input provides a hardware method of protecting data without using V ID. If the system asserts VIL on the WP# pin, the device disables program and erase functions in sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot). If the system asserts VIH on the WP# pin, the device reverts to whether the two outermost 8K Byte boot sectors were last set to be protected or unprotected. Note that the WP# pin must not be left floating or unconnected; inconsistent be- havior of the device may result. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This pro- tects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V CC is greater than VLKO. The sys-

18 Am29BDS320G 27243B1 October 1, 2003

tem must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. VCC and VIO Power-up And Power-down Sequencing The device imposes no restrictions on VCC and VIO power-up or power-down se- quencing. Asserting RESET# to V IL is required during the entire V CC and V IO power sequence until the respective supplies reach their operating voltages. Once V CC and VIO attain their respective operating voltages, de-assertion of RESET# to VIH is permitted. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back- ward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 3-6. To ter- minate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the au- toselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 3-6. The system must write the reset command to return the device to the reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the web at the following URL: http://www.amd.com/flash/cfi. Alternatively, contact a sales office or representative for copies of these documents.

October 1, 2003 27243B1 Am29BDS320G 19 Preliminary Ta bl e 3 . CFI Query Identification String T able 4. System Interface String Addresses Data Description 10h 11h 12h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Addresses Data Description 1Bh 0017h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0019h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h V PP Min. voltage (00h = no VPP pin present) 1Eh 0000h V PP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2 N µs 20h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2 N ms 22h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 0004h Max. timeout for byte/word write 2 N times typical 24h 0000h Max. timeout for buffer write 2 N times typical 25h 0004h Max. timeout per individual block erase 2 N times typical 26h 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported)

20 Am29BDS320G 27243B1 October 1, 2003

Table 5. Device Geometry Definition

October 1, 2003 27243B1 Am29BDS320G 21 Preliminary Ta b l e 6 . Primary Vendor-Specific Extended Query Addresses Data Description 40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII 45h 0004h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5-2) 0001 = 0.17 µm 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0000h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0005h Sector Protect/Unprotect scheme 04 = 29LV800 mode 4Ah 0033h Simultaneous Operation Number of Sectors in all banks except boot block 4Bh 0001h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00B5h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 00C5h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 00xxh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot Device 50h 0000h Program Suspend. 00h = not supported 57h 0004h Bank Organization: X = Number of banks 58h 0013h Bank A Region Information. X = Number of sectors in bank 59h 0010h Bank B Region Information. X = Number of sectors in bank 5Ah 0010h Bank C Region Information. X = Number of sectors in bank 5Bh 0013h Bank D Region Information. X = Number of sectors in bank

22 Am29BDS320G 27243B1 October 1, 2003

Ta b l e 7 . Sector Address T able Sector Sector Size (x16) Address Range Bank D SA0 8 Kwords 000000h-001FFFh SA1 8 Kwords 002000h-003FFFh SA2 8 Kwords 004000h-005FFFh SA3 8 Kwords 006000h-007FFFh SA4 32 Kwords 008000h-00FFFFh SA5 32 Kwords 010000h-017FFFh SA6 32 Kwords 018000h-01FFFFh SA7 32 Kwords 020000h-027FFFh SA8 32 Kwords 028000h-02FFFFh SA9 32 Kwords 030000h-037FFFh SA10 32 Kwords 038000h-03FFFFh SA11 32 Kwords 040000h-047FFFh SA12 32 Kwords 048000h-04FFFFh SA13 32 Kwords 050000h-057FFFh SA14 32 Kwords 058000h-05FFFFh SA15 32 Kwords 060000h-067FFFh SA16 32 Kwords 068000h-06FFFFh SA17 32 Kwords 070000h-077FFFh SA18 32 Kwords 078000h-07FFFFh

October 1, 2003 27243B1 Am29BDS320G 23 Preliminary Bank C SA19 32 Kwords 080000h-087FFFh SA20 32 Kwords 088000h-08FFFFh SA21 32 Kwords 090000h-097FFFh SA22 32 Kwords 098000h-09FFFFh SA23 32 Kwords 0A0000h-0A7FFFh SA24 32 Kwords 0A8000h-0AFFFFh SA25 32 Kwords 0B0000h-0B7FFFh SA26 32 Kwords 0B8000h-0BFFFFh SA27 32 Kwords 0C0000h-0C7FFFh SA28 32 Kwords 0C8000h-0CFFFFh SA29 32 Kwords 0D0000h-0D7FFFh SA30 32 Kwords 0D8000h-0DFFFFh SA31 32 Kwords 0E0000h-0E7FFFh SA32 32 Kwords 0E8000h-0EFFFFh SA33 32 Kwords 0F0000h-0F7FFFh SA34 32 Kwords 0F8000h-0FFFFFh Bank B SA35 32 Kwords 100000h-107FFFh SA36 32 Kwords 108000h-10FFFFh SA37 32 Kwords 110000h-117FFFh SA38 32 Kwords 118000h-11FFFFh SA39 32 Kwords 120000h-127FFFh SA40 32 Kwords 128000h-12FFFFh SA41 32 Kwords 130000h-137FFFh SA42 32 Kwords 138000h-13FFFFh SA43 32 Kwords 140000h-147FFFh SA44 32 Kwords 148000h-14FFFFh SA45 32 Kwords 150000h-157FFFh SA46 32 Kwords 158000h-15FFFFh SA47 32 Kwords 160000h-167FFFh SA48 32 Kwords 168000h-16FFFFh SA49 32 Kwords 170000h-177FFFh SA50 32 Kwords 178000h-17FFFFh Sector Sector Size (x16) Address Range

24 Am29BDS320G 27243B1 October 1, 2003

SA51 32 Kwords 180000h-187FFFh SA52 32 Kwords 188000h-18FFFFh SA53 32 Kwords 190000h-197FFFh SA54 32 Kwords 198000h-19FFFFh SA55 32 Kwords 1A0000h-1A7FFFh SA56 32 Kwords 1A8000h-1AFFFFh SA57 32 Kwords 1B0000h-1B7FFFh SA58 32 Kwords 1B8000h-1BFFFFh SA59 32 Kwords 1C0000h-1C7FFFh SA60 32 Kwords 1C8000h-1CFFFFh SA61 32 Kwords 1D0000h-1D7FFFh SA62 32 Kwords 1D8000h-1DFFFFh SA63 32 Kwords 1E0000h-1E7FFFh SA64 32 Kwords 1E8000h-1EFFFFh SA65 32 Kwords 1F0000h-1F7FFFh SA66 8K words 1F8000h-1F9FFFh SA67 8K words 1FA000h-1FBFFFh SA68 8K words 1FC000h-1FDFFFh SA69 8K words 1FE000h-1FFFFFh Sector Sector Size (x16) Address Range

October 1, 2003 27243B1 Am29BDS320G 25 Preliminary Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 14, “Command Definitions,” on page 36 defines the valid register command sequences. Note that writing incorrect ad- dress and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is required to return the device to normal operation. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the “Erase Suspend/Erase Resume Commands” section on page 34 section for more information. The system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the “Reset Command” section on page 30 section for more information. See also “Requirements for Asynchronous Read Operation (Non-Burst)” and “Re- quirements for Synchronous (Burst) Read Operation” sections for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figures 11, 13, and 18 show the timings. Set Burst Mode Configuration Register Command Sequence The device uses a burst mode configuration register to set the various burst pa- rameters: number of wait states, burs t read mode, active clock edge, RDY configuration, and synchronous mode active. The burst mode configuration reg- ister must be set before the device will enter burst mode. The burst mode configuration register is loaded with a three-cycle command se- quence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C0h, address bits A11–A0 should be 555h, and address bits A19–A12 set the code to be latched. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The burst mode configu- ration register can not be changed during device operations (program, erase, or sector lock).

26 Am29BDS320G 27243B1 October 1, 2003

Figure 1. Synchronous/Asynchronous State Diagram cycles that must elapse after AVD# is driven active before data will be available. A12 determine the setting (see Table 8). should be programmed into the device is directly related to the clock frequency.

Table 8. Programmable Wait State Settings

1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a

total initial access cycle of 2. hardware reset will set the wait state to the default setting. Table 9. Initial Access Cycles vs. Frequency cross 64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64). mand Sequence” section for more information.

40 MHz

54 MHz

28 Am29BDS320G 27243B1 October 1, 2003

Standard Handshaking Operation For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system mu st set the appropriate number of wait states in the flash device depending on the clock frequency. Table 10 describes the typical number of clock cycles (wait states) for various conditions with A14–A12 set to 101. T able 10. Wait States for Standard Handshaking * In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64). Burst Read Mode Configuration The device supports four different burst read modes: continuous mode, and 8, 16, and 32 word linear wrap around modes. A continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear burst with wrap around begins on the starting burst address written to the device and then proceeds until the next 8 word boundary. The address pointer then returns to the first word of the burst se- quence, wrapping back to the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 11 shows the address bits and settings for the four burst read modes. T able 11. Burst Read Mode Settings Note: Upon power-up or hardware reset the default setting is continuous. Burst Active Clock Edge Configuration By default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. Subsequent outputs will also be on the following rising edges, barring any delays. The device can be set so that the falling clock Conditions at Address Typical No. of Clock Cycles after AVD# Low 40/54 MHz Initial address is even 7 Initial address is odd 7 Initial address is even, and is at boundary crossing* 7 Initial address is odd, and is at boundary crossing* 7 Burst Modes Address Bits A16 A15 Continuous 0 0 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1

October 1, 2003 27243B1 Am29BDS320G 29 Preliminary edge is active for all synchronous accesses. Address bit A17 determines this set- ting; “1” for rising active, “0” for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; “1” for RDY active with data, “0” for RDY active one clock cycle before valid data. Configuration Register Table 12 shows the address bits that determine the configuration register settings for various device functions. Ta b l e 12 . Burst Mode Configuration Register Note: Device will be in the default state upon power-up or hardware reset. Sector Lock/Unlock Command Sequence The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system must write the sector lock/ unlock command sequence. In the first and second cycles, the address must point to the bank that contains the sector(s) to be locked or unlocked. The first and second cycle data is 60h. In the third cycle, the address must point to the target sector, and A6 is used to specify a lock (A6 = V IL) or unlock (A6 = VIH) operation. The third cycle data is 60h. After the third cycle, the system can continue to lock or unlock additional sectors in the same bank or exit the sector lock/unlock se- quence by writing the reset command (F0h). It is not possible to read from the bank selected for sector lock/unlock operations. To enable such read operations, write the reset command. Note that the last two outermost boot sectors can be locked by taking the WP# signal to V IL. Address Bit Function Settings (Binary) A19 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) A18 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data (default) A17 Clock 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) A16 Burst Read Mode 00 = Continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around A15 A14 Programmable Wait State 000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) A13 A12

30 Am29BDS320G 27243B1 October 1, 2003

Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). This re- sets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writ- ing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the op- eration is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). The reset command is used to exit the sector lock/unlock sequence. This com- mand is required before reading from the bank selected for sector lock/unlock operations. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manu- facturer and device codes, and determine whether or not a sector is protected. Table 14, “Command Definitions,” on page 36 shows the address and data re- quirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autose- lect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. No subsequent data will be made available if the autoselect data is read in synchronous mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. The following table de- scribes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address, and SA represents the sector ad- dress. The device ID is read in three cycles.

Table 13. Device IDs suspend-read mode if the bank was previously in Erase Suspend). data requirements for the program command sequence. has returned to the read mode, to ensure data integrity.

32 Am29BDS320G 27243B1 October 1, 2003

page 36 shows the requirements for the unlock bypass command sequences. bank then returns to the read mode. Figure 2. Erase Operation

October 1, 2003 27243B1 Am29BDS320G 33 Preliminary the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. Table 14, “Command Defi nitions,” on page 36 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. The command sequence is two cycles in length instead of six cycles. See Table 14 for details on the unlock bypass com- mand sequences. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Pro- gram Operations table in the AC Characteristics section for parameters and timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 14 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Em- bedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than 35 µs occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise era- sure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor inter- rupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. Th e system must rewrite the command se- quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 42.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading

34 Am29BDS320G 27243B1 October 1, 2003

DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” sec- tion on page 37 section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Pro- gram Operations table in the AC Characteristics section for parameters and timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This com- mand is valid only during the sector erase operation, including the minimum 50 µs time-out period during the sector erase command sequence. The Erase Sus- pend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-sus- pend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces sta- tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program op- eration. Refer to the “Write Operation Status” section for more information. In the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. Refer to the “Autoselect Functions” section on page 16 and “Autoselect Command Sequence” section on page 30 sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writ- ing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

Note: See Table 14 for program command sequence. Figure 3. Program Operation

36 Am29BDS320G 27243B1 October 1, 2003

Ta bl e 1 4 . Command Definitions Command Sequence (Notes) Cycles Bus Cycles (Notes 1–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Asynchronous Read (6) 1 RA RD Reset (7) 1 XXX F0 Autoselect (8) Manufacturer ID 4 555 AA 2AA 55 (BA)555 90 (BA)X00 0001 Device ID (9) 6 555 AA 2AA 55 (BA)555 90 (BA)X01 227E (BA)X (Note (BA) X0F 2200 Sector Lock Verify (10) 4 555 AA 2AA 55 (SA)555 90 (SA)X02 0000/0001 Handshaking Option (11) 4 555 AA 2AA 55 (BA)555 90 (BA)X03 0042/0043 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (12) 2 XXX A0 PA PD Unlock Bypass Sector Erase (12) 2 XXX 80 SA 30 Unlock Bypass Chip Erase (12) 2 XXX 80 XXX 10 Unlock Bypass Reset (13) 2 BA 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (7, 14) 1 BA B0 Erase Resume (15) 1 BA 30 Sector Lock/Unlock (7) 3 BA 60 BA 60 SLA 60 Set Burst Mode Configuration Register (16) 3 555 AA 2AA 55 (CR)555 C0 CFI Query (17) 1 55 98 Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# pulse. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A13 uniquely select any sector. BA = Address of the bank (A20, A19) that is being switched to Autoselect mode, is in bypass mode, is being erased, or is being selected for sector lock/unlock. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20–A12 are don’t cares. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. 9. The data in the fifth cycle is 2222 for 1.8 V V IO, and 2214 for 3.0 V VIO (top boot); 2223 for 1.8 V VIO, and 2234 for 3.0 V VIO (bottom boot). 10. The data is 0000h for an unlocked sector and 0001h for a locked sector 11. The data is 0043h for reduced wait-state handshaking and 0042h for standard handshaking. 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. See “Set Burst Mode Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode.

October 1, 2003 27243B1 Am29BDS320G 37 Preliminary Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 16, “Write Operation Status,” on page 42 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase op- eration is complete or in progress. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the com- plement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a pro- gram address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status in- formation on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the bank returns to the read mode. If not all selected sectors are protected, the Em- bedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6–DQ0 while Output Enable (OE#) is as- serted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6–DQ0 may be still invalid. Valid data on DQ7–DQ0 will appear on successive read cycles. Table 16 shows the outputs for Data# Polling on DQ7. Figure 3 shows the Data# Polling algorithm. Figure 27, “Data# Polling Timings (During Embedded Algorithm),” on page 64 in the AC Characteristics section shows the Data# Polling timing diagram.

38 Am29BDS320G 27243B1 October 1, 2003

1. VA = Valid address for programming. Duri ng a sector erase operation, a valid

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simulta-

Figure 4. Data# Polling Algorithm indicates the system should wait 2 clock cycles before expecting valid data.

October 1, 2003 27243B1 Am29BDS320G 39 Preliminary DQ6: T oggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cy- cles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is ac- tively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en- ters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alter- natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a pr otected sector, DQ6 toggles for approxi- mately 1 ms after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 4 (toggle bit flowchart), DQ6: Toggle Bit I (description), Figure 28, “Toggle Bit Timings (During Embedded Algorithm),” on page 64 (toggle bit timing diagram), and Table 15, “DQ6 and DQ2 Indications,” on page 41.

40 Am29BDS320G 27243B1 October 1, 2003

Figure 5. T oggle Bit Algorithm edge of the final WE# pulse in the command sequence.

October 1, 2003 27243B1 Am29BDS320G 41 Preliminary sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 5, “Toggle Bit Algorithm,” on page 40, See “DQ6: Toggle Bit I” on page 39., Figure 28, “Toggle Bit Timings (During Embedded Algorithm),” on page 64, and Table 15, “DQ6 and DQ2 Indi- cations,” on page 41. Ta b l e 1 5 . DQ6 and DQ2 Indications Reading T oggle Bits DQ6/DQ2 Refer to Figure 4 for the following discussion. Whenever the system initially be- gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as de- scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified inter- nal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. If device is and the system reads then DQ6 and DQ2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. The system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.

42 Am29BDS320G 27243B1 October 1, 2003

The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to de- termine whether or not erasure has beg un. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be as- sumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept addi- tional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub- sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 16 shows the status of DQ3 relative to the other status bits. Ta b l e 16 . Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 4. The system may read either asynchronously or synchron ously (burst) while in erase suspend. RDY will function exactly as in non-erase-suspended mode. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) Standard Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle Embedded Erase Algorithm 0 Toggle 0 1 Toggle Erase Suspend Mode Erase-Suspend- Read (Note 4) Erase Suspended Sector 1 No toggle 0 N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle 0 N/A N/A

44 Am29BDS320G 27243B1 October 1, 2003

Notes: 1. Maximum I CC specifications are tested with VCC = VCCmax. 2. All ICC specifications are tested with VIO = VCC. 3. The I CC current listed is typically less than 2 mA/MHz, with OE# at V IH. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for t ACC + 60 ns. Typical sleep mode current is equal to ICC3. Parameter Description Test Conditions (Note 1,2) Min Typ. Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCCmax ±1 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCCmax ±1 µA ICCB VCC Active Burst Read Current CE# = VIL, OE# = VIH, WE# = VIH,

54 MHz 10 20 mA

CE# = VIL, OE# = VIH, WE# = VIH,

40 MHz 81 6 m A

VIO = 1.8 V, OE# = VIH 0.2 10 µA VIO = 3.0 V, OE# = VIH 0.2 10 µA ICC1 VCC Active Asynchronous Read Current (Note 3) CE# = VIL, OE# = VIH, WE# = VIH

5 MHz 12 16 mA

1 M H z 3 . 55m A ICC2 VCC Active Write Current (Note 4) CE# = VIL, OE# = VIH, VPP = VIH 15 40 mA ICC3 VCC Standby Current (Note 5) CE# = RESET# = V CC ± 0.2 V 0.2 10 µA ICC4 VCC Reset Current RESET# = V IL, CLK = VIL 0.2 10 µA ICC5 VCC Active Current (Read While Write) CE# = VIL, OE# = VIH 25 60 mA VIL Input Low Voltage VIO = 1.8 V –0.5 0.2 V VIO = 3.0 V –0.5 0.4 V VIH Input High Voltage VIO = 1.8 V V IO – 0.2 V IO + 0.2 V VIO = 3.0 V V IO – 0.4 V IO + 0.4 V VOL Output Low Voltage IOL = 100 µA, VCC = VCC min, VIO = VIO min 0.1 V VOH Output High Voltage IOH = –100 µA, VCC = VCC min, VIO = VIO min VIO – 0.1 V VID Voltage for Accelerated Program 11.5 12.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V

46 Am29BDS320G 27243B1 October 1, 2003

Figure 10. VCC and VIO Power-up Diagram

October 1, 2003 27243B1 Am29BDS320G 47 Preliminary AC Characteristics Synchronous/Burst Read Note: Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. Parameter

Description

(54 MHz) (54 MHz) (40 MHz) (40 MHz) UnitJEDEC Standard tIACC Latency (Even Address in Reduced Wait-State Handshaking Mode) Max 87.5 95 ns Parameter D8, D9 (54 MHz) D3, D4 (54 MHz) C8, C9 (40 MHz) C3, C4 (40 MHz) UnitJEDEC Standard tIACC Latency—(Standard Handshaking or Odd Address in Handshake mode) Max 106 120 ns tBACC Burst Access Time Valid Clock to Output Delay Max 13.5 20 ns tACS Address Setup Time to CLK (Note Note:) Min 5 ns tACH Address Hold Time from CLK (Note Note:) Min 7 ns tBDH Data Hold Time from Next Clock Cycle Min 3 ns tOE Output Enable to Output Valid Max 13.5 20 ns tCEZ Chip Enable to High Z Max 10 10.5 10 10.5 ns tOEZ Output Enable to High Z Max 10 10.5 10 10.5 ns tCES CE# Setup Time to CLK Min 5 ns tRDYS RDY Setup Time to CLK Min 5 4.5 5 4.5 ns tRACC Ready Access Time from CLK Max 13.5 14 20 20 ns tAAS Address Setup Time to AVD# (Note Note:) Min 5 ns tAAH Address Hold Time to AVD# (Note Note:) Min 7 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 5 ns tAVD AVD# Pulse Min 12 ns tACC Access Time Max 70 ns

48 Am29BDS320G 27243B1 October 1, 2003

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.

Figure 11. CLK Synchronous Burst Mode Read 7 cycles for initial access shown.

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from

two cycles to seven cycles. Clock is set for active falling edge.

1. If any burst address occurs at a 64-word boundary, one a dditional clock cycle is inserted, and is indicated by RDY.
2. The device is in synchronous mode.
3. In the Burst Mode Configuration Register, A17 = 0.

Figure 12. CLK Synchronous Burst Mode Read 4 cycles for initial access shown.

50 Am29BDS320G 27243B1 October 1, 2003

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

1. If any burst address occurs at a 64-word boundary, one a dditional clock cycle is inserted, and is indicated by RDY.
2. The device is in synchronous mode.
3. In the Burst Mode Configuration Register, A17 = 1.

Figure 13. Synchronous Burst Mode Read Set Configuration Register command sequence has been written with A18=1; device will output RDY with valid data. Figure 14. 8-word Linear Burst with Wrap Around 7 cycles for initial access shown. 7 cycles for initial access shown.

ister command sequence has been written with A18=0; device will output RDY one cycle before valid data. Figure 15. Burst with RDY Set One Cycle Before Data 6 wait cycles for initial access shown.

52 Am29BDS320G 27243B1 October 1, 2003

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

1. If any burst address occurs at a 64-word boundary, one a dditional clock cycle is inserted, and is indicated by RDY.
2. The device is in synchronous mode.
3. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state

handshaking under a CLK synchronous burst mode. Figure 16. Reduced Wait-State Handshaking Burst Mode Read 7 cycles for initial access shown.

Figure 17. Reduced Wait-State Handshaking Burst Mode Read

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed

from two cycles to seven cycles. Clock is set for active rising edge.

1. If any burst address occurs at a 64-word boundary, one a dditional clock cycle is inserted, and is indicated by RDY.
2. The device is in synchronous mode.
3. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state

handshaking under a CLK synchronous burst mode. 7 cycles for initial access shown.

54 Am29BDS320G 27243B1 October 1, 2003

Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. Note: RA = Read Address, RD = Read Data. Figure 18. Asynchronous Mode Read with Latched Addresses D3, D4 D8, D9 (54 MHz) C3, C4 C8, C9 (40 MHz) UnitJEDEC Standard tCE Access Time from CE# Low Max 70 90 ns tACC Asynchronous Access Time (Note 1) Max 70 90 ns tAVDP AVD# Low Time Min 12 ns tAAVDS Address Setup Time to Rising Edge of AVD Min 5 ns tAAVDH Address Hold Time from Rising Edge of AVD Min 7 ns tOE Output Enable to Output Valid Max 13.5 20 ns tOEH Output Enable Hold Time Read Min 0 ns Toggle and Data# Polling Min 10 ns tOEZ Output Enable to High Z (Note 2) Max 10 10.5 ns tCAS CE# Setup Time to AVD# Min 0 ns tCEWE# A20-A0 CE# OE# Valid RD tACC tOEH tOE DQ15-DQ0 tOEZ tAAVDH tAVDP tAAVDS AVD# RA tCAS

Note: RA = Read Address, RD = Read Data. Figure 19. Asynchronous Mode Read

56 Am29BDS320G 27243B1 October 1, 2003

Hardware Reset (RESET#) Note: Not 100% tested. Figure 20. Reset Timings RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 35 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 µs RESET# tRP tReadyw Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP

October 1, 2003 27243B1 Am29BDS320G 57 Preliminary AC Characteristics Erase/Program Operations Notes: 1. Not 100% tested. 2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 3. See the “Erase and Programming Performance” section for more information. 4. Does not include the preprogramming time. Parameter Options UnitJEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 80 ns tAVWL tAS Address Setup Time (Note 2) Synchronous Min ns Asynchronous 0 tWLAX tAH Address Hold Time (Note 2) Synchronous Min ns Asynchronous 45 tACS Address Setup Time to CLK (Note 2) Min 5 ns tACH Address Hold Time to CLK (Note 2) Min 7 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 50 ns tWHWL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 3) Typ 8 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 3) Typ 2.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 3, 4) Typ 0.4 sec Chip Erase Operation (Notes 3, 4) 28 tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tCSW1 Clock Setup Time to WE# (Asynchronous) Min 5 ns tCSW2 Clock Setup Time to WE# (Synchronous) Min 1 ns tCHW Clock Hold Time from WE# Max 1 ns tELWL tCS CE# Setup Time to WE# Min 0 ns tAVSW AVD# Setup Time to WE# Min 5 ns tAVHW AVD# Hold Time to WE# Min 5 ns tAVHC AVD# Hold Time to CLK Min 5 ns tAVDP AVD# Low Time Min 12 ns

58 Am29BDS320G 27243B1 October 1, 2003

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A20–A12 are don’t care during command sequence unlock cycles.
4. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode

Figure 21. Asynchronous Program Operation Timings

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A20–A12 are don’t care during command sequence unlock cycles.
4. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode

Figure 22. Alternate Asynchronous Program Operation Timings

60 Am29BDS320G 27243B1 October 1, 2003

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A20–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode
7. CLK must not have an active edge while WE# is at V
8. AVD# must toggle during command sequence unlock cycles.

Figure 23. Synchronous Program Operation Timings

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A20–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode
7. AVD# must toggle during command sequence unlock cycles.
8. CLK must not have an active edge while WE# is at V IL.

Figure 24. Alternate Synchronous Program Operation Timings

62 Am29BDS320G 27243B1 October 1, 2003

Figure 25. Chip/Sector Erase Command Sequence

1. SA is the sector address for Sector Erase.
2. Address bits A20 –A12 are don’t cares during unlock cycles in the command sequence.

Note: Use setup and hold times from conventional program operation. Figure 26. Accelerated Unlock Bypass Programming Timing

64 Am29BDS320G 27243B1 October 1, 2003

1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, and Data# Polling will output true data.

1. AVD# must toggle between data reads.

Figure 27. Data# Polling Timings (During Embedded Algorithm)

1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, the toggle bits will stop toggling.

1. AVD# must toggle between data reads.

Figure 28. T oggle Bit Timings (During Embedded Algorithm)

1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is

complete, the toggle bits will stop toggling.

1. RDY is active with data (A18 = 0 in the Burst Mode Configuration Register). When A18 = 1 in the Burst Mode

Configuration Register, RDY is active one clock cycle before data.

1. AVD# must toggle between data reads.

Figure 29. Synchronous Data Polling Timings/T oggle Bit Timings

66 Am29BDS320G 27243B1 October 1, 2003

1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register).
2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not

crossing a bank in the process of performing an erase or program. Figure 30. Latency with Boundary Crossing 00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing.

1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register).
2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device

crossing a bank in the process of performing an erase or program. Figure 31. Latency with Boundary Crossing

68 Am29BDS320G 27243B1 October 1, 2003

Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 32. Example of Wait States Insertion (Standard Handshaking Device)

Figure 33. Back-to-Back Read/Write Cycle Timings

70 Am29BDS320G 27243B1 October 1, 2003

Erase and Programming Performance Notes: 1. Typical program and erase times as sume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and prog ram cycle endurance of 1 million cycles. FBGA Ball Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Data Retention Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 28 s Word Programming Time 11.5 210 µs Excludes system level overhead (Note 5) Accelerated Word Programming Time 4 120 µs Chip Programming Time (Note 3) 25 75 s Excludes system level overhead (Note 5) Accelerated Chip Programming Time 9 27 s Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0Y e a r s 125°C2 0Y e a r s

October 1, 2003 27243B1 Am29BDS320G 71 Preliminary Physical Dimensions VBD064—64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm Package Note: BSC is an ANSI standard for Basic Space Centering. PACKAGE VBD 064 JEDEC N/A 8.95 mm x 7.95 mm NOM PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.00 OVERALL THICKNESS A1 0.20 --- 0.30 BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 8.95 BSC. BODY SIZE E 7.95 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 64 TOTAL BALL COUNT φb 0.30 0.35 0.40 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT NONE DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. SIDE VIEW A2A SEATING PLANE C CC 0.10 0.08A1 TOP VIEW C (2X) 0.05 (2X) C0.05 A B INDEX MARK CORNER PIN A1 E D BOTTOM VIEW A1 CORNER SD SE e AB NXφb Mφ 0.15 φ 0.08 M C C GH B A D CEF

72 Am29BDS320G 27243B1 October 1, 2003

Revision A (November 22, 2002) Initial release. Revision A + 1 (March 7, 2003) Autoselect Command Sequence Updated Table 3. Command Definitions Updated Table 14, Device ID Sixth Cycle. Revision B (August 12, 2003) Global Updated formatting to new Spansion template. Sector Lock/Unlock Command Sequence Modified description of write cycles. Reset Command Modified last paragraph of section. Table 14, Command Definitions Added note references to Erase Suspend and Sector Lock/Unlock rows in table. Replaced addresses “XXX” with “BA” in first and second cycles of Sector Lock/Un- lock table row. Modified description of BA in legend. Revision B + 1 (October 1, 2003) DC Characteristics - CMOS Compatible Added note #2. Modified column heading fr om Test Conditions (Note 1) to Test Conditions (Note 1,2). Trademarks and Notice This document contains FASL confidential information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from FASL. The information in this document is subject to change without notice. Product and Company names are trademarks or registered trademarks of their respective owners Copyright 2003 FASL LLC. All rights reserved.