BLUENRG-332VT

BLUENRG-LPS STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 67

Technical content

Datasheet sections

• 1 Introduction
• 2 Functional overview
• 2.1 System architecture
• 2.2 Arm Cortex-M0+ core with MPU
• 2.3 Memories
• 2.3.1 Embedded flash memory
• 2.3.2 Embedded SRAM
• 2.3.3 Embedded ROM
• 2.3.4 Embedded OTP
• 2.3.5 Memory protection unit (MPU)
• 2.4 Security and safety
• 2.5 RF subsystem
• 2.5.1 RF front-end block diagram
• 2.5.2 IPDs for BlueNRG-LPS
• 2.6 Power supply management
• 2.6.1 SMPS step-down regulator
• 2.6.2 Power supply schemes
• 2.6.3 Linear voltage regulators
• 2.6.4 Power supply supervisor
• 2.7 Operating modes
• 2.7.1 RUN mode
• 2.7.2 DEEPSTOP mode
• 2.7.3 SHUTDOWN mode
• 2.8 Reset management
• 2.9 Clock management
• 2.10 Boot mode
• 2.11 Embedded UART bootloader
• 2.12 General purpose inputs/outputs (GPIO)
• 2.13 Direct memory access (DMA)
• 2.14 Nested vectored interrupt controller (NVIC)
• 2.15 Analog digital converter (ADC)
• 2.15.1 Temperature sensor
• 2.16 True random number generator (RNG)
• 2.17 Timers and watchdog
• 2.17.1 General-purpose timers (TIM2, TIM16, TIM17)

Features

• Bluetooth ® Low Energy system-on-chip supporting Bluetooth 5.3 specifications – 2 Mbps data rate – Long range (Coded PHY) – Advertising extensions – Channel selection algorithm #2 – GATT caching – Direction finding (AoA/AoD) – LE ping procedure – Periodic advertising and periodic advertising sync transfer – LE L2CAP connection-oriented channel – LE power control and path loss monitoring
• Radio – RX sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps (long range) – Programmable output power up to +8 dBm (at antenna connector) – Data rate supported: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps – 128 physical connections – Integrated balun – Support for external PA and LNA – BlueNRG core coprocessor (DMA based) for Bluetooth Low Energy timing critical operation – 2.4 GHz proprietary radio driver – Suitable for systems requiring compliance with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part 15, ARIB STD-T66 – Available integrated passive device (IPD) companion chip for optimized matching and filtering
• Ultra-low power radio performance – 8 nA in SHUTDOWN mode (1.8 V) – 0.8 µA in DEEPSTOP mode (with external LSE and BLE wake-up sources, 1.8 V) – 1.0 µA in DEEPSTOP mode (with internal LSI and BLE wake-up sources, 1.8 V) – 4.3 mA peak current in TX (@ 0 dBm, 3.3 V) – 3.4 mA peak current in RX (@ sensitivity level, 3.3V)
• High performance and ultra-low power Arm ® Cortex®-M0+ 32-bit, running up to

64 MHz

• Dynamic current consumption: 14 µA/MHz
• Operating supply voltage: from 1.7 to 3.6 V
• -40 ºC to 105 ºC temperature range
• Supply and reset management – High efficiency embedded SMPS step-down converter with intelligent bypass mode – Ultra-low power power-on-reset (POR) and power-down-reset (PDR) – Programmable voltage detector (PVD) VFQFPN32 (5 x 5 mm) WLCSP36 (2.83 x 2.99 mm) Product status link BlueNRG-LPS Product summary Order code BlueNRG-332xy Programmable Bluetooth® Low Energy wireless SoC BlueNRG-LPS Datasheet DS13819 - Rev 4 - March 2023 For further information contact your local STMicroelectronics sales office.

• Clock sources – 64 MHz PLL – Fail safe 32 MHz crystal oscillator with integrated trimming capacitors – 32 kHz crystal oscillator – Internal low-power 32 kHz RO
• On-chip non-volatile flash memory of 192 Kbytes
• On-chip RAM of 24 Kbytes + 4 Kbytes PKA RAM
• One-time-programmable (OTP) memory area of 1 Kbytes
• Embedded UART bootloader
• Ultra-low power modes with or without timer and RAM retention
• Quadrature decoder
• Enhanced security mechanisms such as: – Flash read/write protection – SWD disabling – Secure bootloader
• Security features – True random number generator (RNG) – Hardware encryption AES maximum 128-bit security co-processor – HW public key accelerator (PKA) – Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p) – CRC calculation unit – 64-bit unique ID
• System peripherals – 1x DMA controller with 8 channels supporting ADC, SPI-I2S, I2C, USART, LPUART, TIMERS – 1x SPI with I2S interface multiplexed – 1x I 2C (SMBus/PMBus) – 1x LPUART (low power) – 1x USART (ISO 7816 smartcard mode, IrDA, SPI Master and Modbus) – 1x independent WDG – 1x real-time clock (RTC) – 1x independent SysTick – 1x 16-bits, four channel general purpose timer – 2x 16-bits, two channel general purpose timer – Infrared interface
• Up to 20 fast I/Os – All of them with wake-up capability – All of them retain state in low-power – All of them 5 V tolerant
• Analog peripherals – 12-bit ADC with 8 input channels, up to 16 bits with down sampler – Battery monitoring – Analog watchdog
• Development support – Serial wire debug (SWD) – 4 breakpoints and 2 watchpoints
• All packages are ECOPACK2 compliant BlueNRG-LPS DS13819 - Rev 4 page 2/67

Applications

• Industrial
• Home and industrial automation
• Asset tracking, ID location, real-time locating system
• Smart lighting
• Fitness,wellness and sports
• Healthcare, consumer medical
• Security/proximity
• Remote control
• Assisted living
• Mobile phone peripherals
• PC peripherals

Description

The BlueNRG-LPS is an ultra-low power programmable Bluetooth® Low Energy wireless SoC solution. It embeds STMicroelectronics’s state-of-the-art 2.4 GHz radio IPs, optimized for ultra-low-power consumption and excellent radio performance, for unparalleled battery lifetime. It is compliant with Bluetooth Low Energy SIG core specification version 5.3 addressing point-to-point connectivity and Bluetooth Mesh networking and allows large-scale device networks to be established in a reliable way. The BlueNRG-LPS is also suitable for 2.4 GHz proprietary radio wireless communication to address ultra-low latency applications. The BlueNRG-LPS embeds a Arm® Cortex®-M0+ microcontroller that can operate up to 64 MHz and also the BlueNRG core co-processor (DMA based) for Bluetooth Low Energy timing critical operations. The main Bluetooth Low Energy 5.3 specification supported features are:

2 Mbps data rate, long range (Coded PHY), advertising extensions, channel selection algorithm #2, GATT

caching, Direction Finding (AoA/AoD), hardware support for simultaneous connection, master/slave and multiple roles simultaneously, extended packet length support, LE Ping procedure, periodic advertising and periodic advertising sync transfer, LE power control and path loss monitoring. In addition, the BlueNRG-LPS provides enhanced security hardware support by dedicated hardware functions: True random number generator (RNG), encryption AES maximum 128-bit security co-processor, public key accelerator (PKA), CRC calculation unit, 64-bit unique ID, flash memory read and write protection. The public key acceleration (PKA) supports the modular arithmetic including exponentiation with maximum modulo size of 3136 bits and the elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits CRC calculation unit. The BlueNRG-LPS can be configured to support standalone or network processor applications. In the first configuration, the BlueNRG-LPS operates as a single device in the application for managing both the application code and the Bluetooth Low Energy stack. The BlueNRG-LPS embeds high-speed and flexible memory types: Flash memory of 192 Kbytes, RAM memory of 24 Kbytes, one-time-programmable (OTP) memory area of 1 Kbyte, ROM memory of 7 Kbytes (ST reserved area). Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA channels with a full flexible channel mapping by the DMAMUX peripheral. The BlueNRG-LPS embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to three internal sources, including battery monitoring and a temperature sensor. The BlueNRG-LPS has a low-power RTC and three general purpose 16-bit timers. The BlueNRG-LPS features standard and advanced communication interfaces: 1x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode), IrDA and Modbus mode, 1x I2C supporting SMBus/PMBus. The BlueNRG-LPS operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The BlueNRG-LPS integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with a fixed threshold that generates a device reset when the VDD drops under 1.65 V. The BlueNRG-LPS comes in different package versions supporting up to: BlueNRG-LPS DS13819 - Rev 4 page 3/67

20 I/Os for the QFN32 package. 20 I/Os for the WLCSP36 package. Figure 1. BlueNRG-LPS block diagram

192 Kbyte flash

1 Introduction

This document provides the ordering information and mechanical device characteristics of the microcontrollers, based on Arm® core. This document must be read in conjunction with the BlueNRG-LPS reference manual (RM0491) and the BlueNRG-LPS radio controller reference manual (RM0498). For information on the device errata with respect to the datasheet and reference manual, refer to the BlueNRG- LPS errata sheet (ES0576). For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ technical reference manual, available from the www.arm.com website. For information on Bluetooth® refer to www.bluetooth.com website. Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. BlueNRG-LPS Introduction DS13819 - Rev 4 page 5/67

2 Functional overview

2.1 System architecture

• Three masters: – CPU (Cortex-M0+) core S-bus – DMA1 – Radio system
• Seven slaves: – Internal flash memory on CPU (Cortex-M0+) S bus – Internal SRAM0 (12 Kbytes) – Internal SRAM1 (12 Kbytes) – APB0 peripherals (through an AHB to APB bridge) – APB1 peripherals (through an AHB to APB bridge) – AHB0 peripherals – AHBRF including AHB to APB bridge and radio peripherals (connected to APB2) The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously.

Figure 2. Bus matrix

2.2 Arm Cortex-M0+ core with MPU

consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm Cortex-M0+ can run from 1 MHz up to 64 MHz. core, the BlueNRG-LPS family is compatible with all ARM tools and software.

2.3 Memories

2.3.1 Embedded flash memory

implements the read and write protection.

• Memory organization: – 1 bank of 192 Kbytes – Page size: 2 Kbytes – Page number 96
• 32-bit wide data read/write
• Page erase and mass erase The flash controller features are:
• flash memory read operations: single read or mass read
• flash memory write operations: single data write or 4x32-bits burst write or mass write
• flash memory erase operations: page erase or mass erase
• page write protect mechanism: 4 variable-size memory segments

2.3.2 Embedded SRAM

Table 1. SRAM overview

2.3.3 Embedded ROM

• The UART bootloader from which the CPU boots after each reset (first 6 Kbytes of ROM memory)
• Some ST reserved values including the ADC trimming values (the last 1 Kbyte of ROM memory)

2.3.4 Embedded OTP

system reset. This operation freezes the OTP memory from further unwanted write operations.

2.3.5 Memory protection unit (MPU)

The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area settings, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.

2.4 Security and safety

The BlueNRG-LPS contains many security blocks for the BLE and the host application. It includes:

• Flash read/write protection over accidental and intentional actions
• As protection against potential hacker attacks, the SWD access can be disabled
• Secure bootloader (refer to the dedicated application note AN5471)
• Customer storage of the BLE keys
• True random number generator (RNG)
• Public key accelerator (PKA) including: – Modular arithmetic including exponentiation with maximum modulo size of 3136 bits – Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits
• Cyclic redundancy check calculation unit (CRC)

2.5 RF subsystem

The BlueNRG-LPS embeds an ultra-low power radio, compliant with Bluetooth Low Energy (BLE) specification. The BLE features 1 Mbps and 2 Mbps transfer rates as well as long range options (125 kbps, 500 kbps), supports multiple roles simultaneously acting at the same time as Bluetooth Low Energy sensor and hub device. The BLE protocol stack is implemented by an efficient system partitioned as follows:

• Hardware part: BlueCore handling time critical and time consuming BLE protocol parts
• Firmware part: Arm® Cortex-M0+ core handling non time critical BLE protocol parts

2.5.1 RF front-end block diagram

The RF front end is based on a direct modulation of the carrier in TX, and uses a low IF architecture in RX mode. Thanks to an internal transformer with RF pins, the circuit directly interfaces the antenna (single ended connection, impedance close to 50 Ω). The natural band pass behavior of the internal transformer simplifies outside circuitry aimed at harmonic filtering and out of band interferer rejection. In transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the power amplifier. A linearized, smoothed analog control offers a clean power ramp-up. In receive mode the circuit can be used in standard high performance or in reduced power consumption (user programmable). The automatic gain control (AGC) is able to reduce the chain gain at both RF and IF locations, for an optimized interferer rejection. Thanks to the use of complex filtering and highly accurate I/Q architecture, high sensitivity, and excellent linearity can be achieved. BlueNRG-LPS Security and safety DS13819 - Rev 4 page 8/67

Figure 3. BlueNRG-LPS RF block diagram Note: QFN32: VSS through exposed pad,and VSSRF pins must be connected to ground plane. CSP36: VSSRF pins must be connected to ground plane. Note: QFN32: VSS through exposed pad,and VSSRF pins must be connected to ground plane. CSP36: VSSRF pins must be connected to ground plane.

2.5.2 IPDs for BlueNRG-LPS

Table 2 lists the available IPD variants for the BlueNRG-LPS device. Table 2. IPDs for BlueNRG-LPS

2.6 Power supply management

2.6.1 SMPS step-down regulator

where the voltage is low, or where the power consumption is not critical. Figure 4. Power supply configuration

2.6.2 Power supply schemes

• V DD33 (VDDIO or VDD): – the voltage range is between 1.7 V and 3.6 V – it supplies a part of the I/O ring, the embedded regulators and the system analog IPs as power management block and embedded oscillators
• V DD12o: – always-on digital power domain – this domain is generally supplied at 1.2 V during active phase of the device – this domain is supplied at 1.0 V during low power mode (DEEPSTOP)
• V DD12i: – interruptible digital power domain – this domain is generally supplied at 1.2 V during active phase of the device – this domain is shut down during low power mode (DEEPSTOP) BlueNRG-LPS Power supply management DS13819 - Rev 4 page 10/67

Figure 5. Power supply domain overview

2.6.3 Linear voltage regulators

• The main LDO (MLDO): – it provides 1.2 V from a 1.4-3.3 V input voltage – it supplies both V DD12i and VDD12o when the device is active – it is disabled during the low power mode (DEEPSTOP)
• Low power LDO (LPREG): – it stays enabled during both active and low power phases – it provides 1.0 V voltage – it is not connected to the digital domain when the device is active – it is connected to the V DD12o domain during low power mode (DEEPSTOP)
• A dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).

2.6.4 Power supply supervisor

• Power-on-reset (POR): during the power-on, the device remains in reset mode if V DDIO is below a VPOR threshold (typically 1.65 V)
• Power-down-reset (PDR): during power-down, the PDR puts the device under reset when the supply voltage (VDD) drops below the VPDR threshold (around 20 mV below VPOR). The PDR feature is always enabled
• Power voltage detector (PVD): can be used to monitor the V DDIO (against a programmed threshold) or an external analog input signal. When the feature is enabled and the PVD measures a voltage below the comparator, an interrupt is generated (if unmasked) BlueNRG-LPS Power supply management DS13819 - Rev 4 page 11/67

2.7 Operating modes

• RUN mode
• DEEPSTOP mode
• SHUTDOWN mode

Table 3. Relationship between the low power modes and functional blocks

2.7.1 RUN mode

• All interfaces are active
• The internal power supplies are active
• The system clock and the bus clock are running
• The CPU core and the radio can be used The power consumption may be reduced by gating the clock of the unused peripherals.

2.7.2 DEEPSTOP mode

environment and the application at wake-up to go on running.

• The radio is sleeping (no radio activity)
• The CPU is sleeping (WFI with SLEEPDEEP bit activated)
• No unmasked wake-up sources are active
• The low-power mode selection (LPMS) bit of the power controller unit is 0 (default)
• The GPIO Retention Mode Selection (GPIORET) bit of the Power Controller unit must be set In DEEPSTOP mode:
• The system and the bus clocks are stopped
• Only the essential digital power domain is ON and supplied at 1.0 V
• The bank RAM0 is kept in retention
• The bank RAM1 can be in retention or not, depending on the software configuration BlueNRG-LPS Operating modes DS13819 - Rev 4 page 12/67

• The I/Os pull-up and pull-down can be controlled during DEEPSTOP mode, depending on the software configuration
• The low speed clock can be running or stopped, depending on the software configuration: – ON or OFF – Sourced by LSE or by LSI
• The RTC, IWDG and LPUART stay active, if enabled and the low speed clock is ON
• The radio wake-up block, including its timer, stay active (if enabled and the low speed clock is ON)
• Up to 20 GPIOs retaining their configuration: – I/Os retain the RUN mode configuration while in DEEPSTOP mode
• Up to 20 I/Os are able to be in output driving: – A static low or high level
• Some I/Os are able to be in output driving: – The low speed clock (on PA10) – The RTC output (on PA8) Possible wake-up sources are:
• The radio block is able to generate two events to wake up the system through its embedded wake-up timer running on low speed clock: – Radio wake-up time is reached – CPU host wake-up time is reached
• The RTC can generate a wake-up event
• The IWDG can generate a reset event
• The LPUART is able to generate a wake-up event
• All GPIOs are able to wake up the system At wake-up, all the hardware resources located in the digital power domain that are OFF during the DEEPSTOP mode, are reset. The CPU reboots. The wake-up reason is visible in the register of the power controller. BlueNRG-LPS Operating modes DS13819 - Rev 4 page 13/67

2.7.3 SHUTDOWN mode

The SHUTDOWN mode is the least power consuming mode. The conditions to enter SHUTDOWN mode are the same conditions needed to enter DEEPSTOP mode except that the LPMS bit of the power controller unit is 1. In SHUTDOWN mode, the BlueNRG-LPS is in ultra-low power consumption: all voltage regulators, clocks and the RF interface are not powered. The BlueNRG-LPS can enter shutdown mode by internal software sequence. The only way to exit shutdown mode is by asserting and deasserting the RSTN pin. In SHUTDOWN mode:

• The system is powered down as both the regulators are OFF
• The V DDIO power domain is ON
• All the clocks are OFF, LSI and LSE are OFF
• The I/Os pull-up and pull-down can be controlled during SHUTDOWN mode, depending on the software configuration
• The only wake-up source is a low pulse on the RSTN pin The exit from SHUTDOWN is similar to a POR startup. The PDR feature can be enabled or disabled during SHUTDOWN.

2.8 Reset management

The BlueNRG-LPS offers two different resets:

• The PORESETn: this reset is provided by the low power management unit (LPMU) analog block and corresponds to a POR or PDR root cause. It is linked to power voltage ramp-up or ramp-down. This reset impacts all resources of the BlueNRG-LPS. The exit from SHUTDOWN mode is equivalent to a POR and thus generates a PORESETn. The PORESETn signal is active when the power supply of the device is below a threshold value or when the regulator does not provide the target voltage.
• The PADRESETn (system reset): this reset is built through several sources: – PORESETn – Reset due to the watchdog The BlueNRG-LPS device embeds a watchdog timer, which may be used to recover from software crashes – Reset due to CPU Lockup The Cortex-M0+ generates a lockup to indicate the core is in the lock-up state resulting from an unrecoverable exception. The lock-up reset is masked if a debugger is connected to the Cortex-M0+ – Software system reset The system reset request is generated by the debug circuitry of the Cortex-M0+. The debugger sets the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system reset request through the AIRCR can also be done by the embedded software (into the hardfault handler for instance) – Reset from the RSTN external pin The RSTN pin toggles to inform that a reset has occurred This PADRESETn resets all resources of the BlueNRG-LPS, except: – Debug features – Flash controller key management – RTC timer – Power controller unit – Part of the RCC registers The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low. BlueNRG-LPS Reset management DS13819 - Rev 4 page 14/67

2.9 Clock management

Three different clock sources may be used to drive the system clock of the BlueNRG-LPS:

• HSI: high speed internal 64 MHz RC oscillator
• PLL64M: 64 MHz PLL clock
• HSE: high speed 32 MHz external crystal The BlueNRG-LPS also has a low speed clock tree used by some timers in the radio, RTC, IWDG and LPUART. Three different clock sources can be used for this low speed clock tree:
• Low speed internal (LSI): low speed and low drift internal RC with a fixed frequency between 24 kHz and 49 kHz depending on the sample
• Low speed external (LSE) from: – An external crystal 32.768 kHz – A single-ended 32.738 kHz input signal
• A 32 kHz clock derived from dividing HSI or HSE. In this case, the slow clock is not available in DEEPSTOP low-power mode By default, after a system reset, all low speed sources are OFF. Both the activation and the selection of the slow clock are relevant during DEEPSTOP mode and at wakeup as slow clock generates a clock for the timers involved in wake-up event generation. The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock output by this block can be:
• A non-accurate clock when no external XO provides an input clock to this block (HSI)
• An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M) After reset, the CLK_SYS is divided by four to provide 16 MHz to the whole system (CPU, DMA, memories and peripherals). BlueNRG-LPS Clock management DS13819 - Rev 4 page 15/67

Figure 6. Clock tree

• The low speed clocks can be output on the LCO I/O
• The high speed clocks can be output on the MCO I/O This is possible by programming the associated I/O in the correct alternate function. Most of the peripherals only use the system clock except:
• I 2C, USART: they use an always 16 MHz clock to have a fixed reference clock for baud rate management. The goal is to allow the CPU to boost or slow down the system clock (depending on on-going activities) without impacting a potential on-going serial interface transfer on external I/Os
• LPUART: always uses a 16 MHz clock or LSE to have a fixed reference clock for baud rate management. The goal is to allow the CPU to boost or slow down the system clock (depending on on-going activities) without impacting a potential on-going serial interface transfer on external I/Os. BlueNRG-LPS Clock management DS13819 - Rev 4 page 16/67

• SPI: when using the I2S mode, the baud rate is managed through the always 16 MHz or always 32 MHz clock or system clock (CLK_SYS) to reach higher baud rates. When running in other modes than the I2S, the baud rate is managed by the system clock. This implies its baud rate is impacted by dynamic system clock frequency changes.
• RNG: in parallel with the system clock, the RNG uses an always 16 MHz clock to generate at a constant frequency the random number whatever the system clock frequency
• Flash controller: in parallel with the system clock, the flash controller uses an always 16 MHz clock to generate specific delays required by the flash memory during programming and erase operations for example
• PKA: in parallel with the system clock, the PKA uses the system clock frequency
• Radio: it does not directly use the system clock for its APB/AHB interfaces, but the system clock with a potential divider (1 or 2 or 4). In parallel, the radio uses an always 16 MHz and an always 32 MHz for modulator, demodulator and to have a fixed reference clock to manage specific delays
• ADC: in parallel with the system clock, ADC uses a 64 MHz prescaled clock running at 16 MHz

2.10 Boot mode

Following CPU boot, the application software can modify the memory map at address 0x0000 0000. This modification is performed by programming the REMAP bit in the flash controller. The following memory can be remapped:

• main flash memory
• SRAM0 memory

2.11 Embedded UART bootloader

The BlueNRG-LPS has a pre-programmed bootloader supporting UART protocol with automatic baud rate detection. The main features of the embedded bootloader are:

• auto baud rate detection up to 1 Mbps
• flash mass erase, section erase
• flash programming
• flash readout protection enable/disable The pre-programmed bootloader is an application, which is stored in the BlueNRG-LPS internal ROM at manufacturing time by STMicroelectronics. This application allows upgrading of the device flash memory with a user application using a serial communication channel (UART). Bootloader is activated by hardware by forcing PA10 high during hardware reset, otherwise, application residing in flash memory is launched. Note: Bootloader protocol is described in a separate application note (the UART bootloader protocol, AN5471)

2.12 General purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB0 bus. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.13 Direct memory access (DMA)

The DMA is used in order to provide high-speed data transfer between peripherals and memory as well as memory-to-memory. Data can be quickly moved by DMA without any CPU actions. In this manner, CPU resources are free for other operations. The DMA controller has eight channels in total. Each has an arbiter to handle the priority among DMA requests. DMA main features are:

• Eight independently configurable channels (requests)
• Each of the eight channels is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software BlueNRG-LPS Boot mode DS13819 - Rev 4 page 17/67

• Priorities among requests from channels of DMA are software programmable (four levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)
• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size
• Support for circular buffer management
• Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer (RAM only)
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to SRAMs, APB0 and APB1 peripherals as source and destination
• Programmable number of data to be transferred: up to 65536

2.14 Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex-M0+ nested vector interrupt controller (NVIC). NVIC controls specific Cortex-M0+ interrupts as well as the BlueNRG-LPS peripheral interrupts. The NVIC benefits are the following:

• Nested vectored interrupt controller that is an integral part of the ARM Cortex-M0+
• Tightly coupled interrupt controller provides low interrupt latency
• Control system exceptions and peripheral interrupts
• NVIC supports 32 vectored interrupts
• Four programmable interrupt priority levels with hardware priority level masking
• Software interrupt generation using the ARM exceptions SVCall and PendSV
• Support for NMI
• ARM Cortex M0+ vector table offset register VTOR implemented NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

2.15 Analog digital converter (ADC)

The BlueNRG-LPS embeds a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-to- digital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources and up to two internal sources. The ADC main features are:

• Conversion frequency is up to 1 Msps
• Three input voltage ranges are supported (0 - 1.2 V, 0 - 2.4 V, 0 - 3.6 V)
• Up to eight analog single-ended channels or four analog differential inputs or a mix of both
• Temperature sensor conversion
• Battery level conversion up to 3.6 V
• ADC continuous or single mode conversion is possible
• ADC down-sampler for multi-purpose applications to improve analog performance while off-loading the CPU (ratio adjustable from 1 to 128)
• A watchdog feature to inform when data is outside thresholds
• DMA capability
• Interrupt sources with flags.

2.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage that varies linearly with temperature. The temperature sensor is internally connected to the ADC input channel, which is used to convert the sensor output voltage into a digital value. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. BlueNRG-LPS Nested vectored interrupt controller (NVIC) DS13819 - Rev 4 page 18/67

2.16 True random number generator (RNG)

RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the host when read. The minimum period is 1.25 us, corresponding to 20 RNG clock cycles between two consecutive random number.

2.17 Timers and watchdog

The BlueNRG-LPS includes three general-purpose timers, one watchdog timer and a SysTick timer.

2.17.1 General-purpose timers (TIM2, TIM16, TIM17)

There are up to three general-purpose timers embedded in the BlueNRG-LPS. Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2 – Full-featured general-purpose timer – Features four independent channels for input capture/output compare, PWM or one-pulse mode output – Independent DMA request generation, support of quadrature encoders
• TIM16 and TIM17 – General-purpose timers with mid-range features: – 16-bit auto-reload upcounters and 16-bit prescalers – 1 channel and 1 complementary channel – All channels can be used for input capture/output compare, PWM or one-pulse mode output – The timers have independent DMA request generation – The timers are internally connected to generate an infrared interface (IRTIM) for remote control

2.17.2 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from the LS clock and it can operate in DEEPSTOP mode. It can also be used as a watchdog to reset the device when a problem occurs.

2.17.3 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0

2.18 Real-time clock (RTC)

The RTC is an independent BCD timer/counter. The RTC provides a time of day/clock/calendar with programmable alarm interrupt. RTC includes also a periodic programmable wake-up flag with interrupt capability. The RTC provides an automatic wake-up to manage all low power modes. Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the programmable alarm sub seconds, seconds, minutes, hours, day, and date. A digital calibration circuit with 0.95 ppm resolution is available to compensate for quartz crystal inaccuracy. After power-on reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (RUN mode, low power mode or under system reset). The RTC counter does not freeze when CPU is halted by a debugger. BlueNRG-LPS True random number generator (RNG) DS13819 - Rev 4 page 19/67

2.19 Inter-integrated circuit interface (I2C)

The BlueNRG-LPS embeds one I2Cs. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports:

• I 2C bus specification and user manual rev. 5 compatibilities: – Slave and master modes – Multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (fm+), with a bitrate up to 1 Mbit/s and 20 mA output driver I/Os – 7-bit and 10-bit addressing mode – Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) – All 7-bit address acknowledge mode – General call – Programmable setup and hold times – Easy to use event management – Optional clock stretching – Software reset
• System management Bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (Packet Error Checking) generation and verification with ACK control – Address resolution protocol (ARP) support – Host and device support – SMBus alert – Timeouts and idle condition detection
• Power system management protocol (PMBus TM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I 2C communication speed to be independent from the PCLK reprogramming
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

2.20 Universal synchronous/asynchronous receiver transmitter (USART)

USART offers flexible full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. USART is able to communicate with a speed up to 2 Mbit/s. Furthermore, USART is able to detect and automatically set its own baud rate, based on the reception of a single character. The USART peripheral supports:

• Synchronous one-way communication
• Half-duplex single wire communication
• Local interconnection network (LIN) master/slave capability
• Smart card mode, ISO 7816 compliant protocol
• IrDA (infrared data association) SIR ENDEC specifications
• Modem operations (CTS/RTS)
• RS485 driver enable
• Multiprocessor communications
• SPI-like communication capability High speed data communication is possible by using DMA (direct memory access) for multibuffer configuration.

2.21 LPUART

The device embeds one low-power UART, enabling asynchronous serial communication with minimum power consumption. The LPUART supports half duplex single wire communication and modem operations (CTS/RTS), allowing multiprocessor communication. BlueNRG-LPS Inter-integrated circuit interface (I2C) DS13819 - Rev 4 page 20/67

The LPUART has a clock domain independent from the CPU clock, and can wake up the system from DEEPSTOP mode using baud rates up to 9600 baud. The wake-up events from Stop mode are programmable and can be:

• Start bit detection
• Any received data frame
• A specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in DEEPSTOP mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baud rates in RUN mode. The LPUART interfaces can be served by the DMA controller.

2.22 Serial peripheral interface (SPI)

The BlueNRG-LPS has one SPI interface (SPI3) allowing communication up to 32 Mbit/s in both master and slave modes. The SPI peripheral supports:

• Master or slave operation
• Multimaster support
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• Serial communication with external devices
• NSS management by hardware or software for both master and slave: dynamic change of master/slave operations
• SPI Motorola support
• SPI TI mode support
• Hardware CRC feature for reliable communication All SPI interfaces can be served by the DMA controller.

2.23 Inter-IC sound (I2S)

The BlueNRG-LPS SPI interface SPI3 supports the I2S protocol. The I2S interface can operate in slave or master mode with half-duplex communication. It can address four different audio standards:

• Philips I2S standard
• MSB-justified standards (left-justified)
• LSB-justified standards (right-justified)
• PCM standard. The I2S interfaces DMA capability for transmission and reception.

2.24 Serial wire debug port

The BlueNRG-LPS embeds an ARM SWD interface that allows interactive debugging and programming of the device. The interface is composed of only two pins: SWDIO and SWCLK. The enhanced debugging features for developers allow up to 4 breakpoints and up to 2 watchpoints.

2.25 TX and RX event alert

The BlueNRG-LPS is provided with the TX_SEQUENCE and RX_SEQUENCE signals which alert, respectively, transmission and reception activities. A signal can be enabled for TX and RX on two pins, through alternate functions:

• TX_SEQUENCE is available on PA10 (AF2) or PB14 (AF1).
• RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2). The signal is high when radio is in TX (or RX), low otherwise. The signals can be used to control external antenna switching and support coexistence with other wireless technologies. BlueNRG-LPS Serial peripheral interface (SPI) DS13819 - Rev 4 page 21/67

Note: The RF_ACTIVITY signal is used to notify if there is an ongoing RF operation ( either TX or RX). It is a logical OR between the RX_SEQUENCE and TX_SEQUENCE. This signal can be used to enable an antenna switch component when achieving antenna switching during AoA or AoD operation.

2.26 Direction finding

The BlueNRG-LPS Bluetooth radio controller supports the angle of arrival (AoA) and angle of departure (AoD) features by managing:

• the constant tone extension (CTE) inside a packet
• the antenna switching mechanism for both AoA and AoD. The antenna switching mechanism provides a 7-bit antenna identifier ANTENNA_ID[6:0] indicating the antenna number to be used. In a AoD transmitter or in a AoA receiver, the radio needs to switch antenna during the CTE field of the packet. For this purpose, the ANTENNA_ID signal can be enabled on some I/Os, by programming them in the associated alternate function. This signal needs to be provided to an external antenna switching circuit, since ANTENNA_ID[0] is the least significant bit and ANTENNA _ID[6] the most significant bit of the antenna identifier to be used. BlueNRG-LPS Direction finding DS13819 - Rev 4 page 22/67

3 Pinouts and pin description

The BlueNRG-LPS comes in two package versions: WLCSP36 offering 20 GPIOs and QFN32 offering 20 GPIOs. Figure 7. Pinout top view (QFN32 package)

Figure 8. Pinout bump side view (WLCSP36 package)

Table 4. Pin descriptions

1 C6 PB3 I/O FT_a

2 D5 PB2 I/O FT_a USART_RTS_DE, TIM2_CH3,

3 E6 PB1 I/O FT_a USART_CK, TIM2_ETR, TIM16_CH1N,

4 D7 PB0 I/O FT_a USART_RX, LPUART_RTS_DE,

5 H5 PA3 I/O FT_a SWCLK, USART_RTS_DE, SPI3_SCK,

6 G6 PA2 I/O FT_a SWDIO, USART_CK, SPI3_MCK,

7 F7 PA1 I/O FT_f I2C1_SDA, IR_OUT, USART_TX,

8 H7 PA0 I/O FT_f I2C1_SCL, USART_CTS, IR_OUT,

9 M7 PA8 I/O FT

10 J6 PA9 I/O FT USART_TX, RTC_OUT, SPI3_NSS,

11 K5 PA10 I/O FT LPUART_CTS, TX_SEQUENCE,

12 J4 PA11 I/O FT MCO, RX_SEQUENCE, SPI3_MOSI,

14 M5 RF1 I/O RF - RF input/output.

16 M1 OSCOUT I/O FT_a - 32 MHz crystal

17 K1 OSCIN I/O FT_a - 32 MHz crystal

18 F3 PB15 I/O FT_a USART_RX Wakeup

19 E2 PB14 I/O FT_a TX_SEQUENCE, I2C1_SDA,

20 D3 PB13 I/O FT_a TIM2_CH4 SXTAL1, Wakeup

21 C2 PB12 I/O FT_a LPUART_CTS, LCO, TIM2_CH3 SXTAL0, Wakeup

22 E4 PB7 I/O FT_f USART_CTS, I2C1_SDA, LPUART_RX,

23 C4 PB6 I/O FT_f I2C1_SCL, LPUART_TX, TIM2_CH1,

25 D1 VLXSD S - - SMPS input/output

26 A2 VSSSD S - - SMPS Ground

27 B3 VFBSD S - - SMPS output

28 A4 VDDA_VCA

29 B5 RSTN I/O RST - Reset pin

30 G4 PB5 I/O FT_a LPUART_RX, TIM2_CH2, TIM17_BK,

31 F5 PB4 I/O FT_a LPUART_TX, TIM2_CH1, TIM17_CH1N,

Table 5. Legend/abbreviations used in the pinout table

1. The related I/O structures in Table 4. Pin descriptions are: FT_f
2. The related I/O structures in Table 4. Pin descriptions are: FT_a
3. IO BOOSTER block allows the good behavior of those switches to be guaranteed when the VBAT goes below 2.7 V.

Table 6. Alternate function port A Table 7. Alternate function port B

4 Memory mapping

Program memory, data memory and registers are organized within the same linear 4-Gbyte address space. Figure 9. Memory map

5 Application circuits

The schematics below are purely indicative. Figure 10. Application circuit: DC-DC converter, WLCSP36 package Figure 11. Application circuit: DC-DC converter, QFN32 package

Table 8. Application circuit external components

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to ground (GND).

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the following standard conditions:

• Ambient temperature is T A = 25 °C
• Supply voltage is V DD: 3.3 V
• System clock frequency is 32 MHz (clock source HSI)
• SMPS clock frequency is 4 MHz Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are only given as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in the figure below. Figure 12. Pin loading conditions

Electrical characteristics

DS13819 - Rev 4 page 31/67

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in the figure below. Figure 13. Pin input voltage

6.2 Absolute maximum ratings

device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Voltage characteristics Table 10. Current characteristics Table 11. Thermal characteristics

6.3 Operating conditions

6.3.1 Summary of main performance

Table 12. Main performance SMPS ON

Table 13. Main performance SMPS bypassed

Table 14. Peripheral current consumption at VDD = 3.3 V, system clock (CLK_SYS), SMPS on

6.3.2 General operating conditions

Table 15. General operating conditions

1. It could be 0 if all the peripherals are disabled.
2. T A cannot exceed TJ max.

6.3.3 RF general characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design. Table 16. Bluetooth Low Energy RF general characteristics

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

6.3.4 RF transmitter characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design. Table 17. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps not coded

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

Table 18. Bluetooth Low Energy RF transmitter characteristics at 2 Mbps not coded

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

Table 19. Bluetooth Low Energy RF transmitter characteristics at 1 Mbps LE coded (S=8)

1. Tested according to Bluetooth SIG radio frequency physical layer (RF PHY) test suite (not tested in production).

6.3.5 RF receiver characteristics

All performance data are referred to a 50 Ω antenna connector, via reference design. Table 20. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s uncoded

2000 MHz

2399 MHz

2997 MHz

12.75 GHz

Table 21. Bluetooth Low Energy RF receiver characteristics at 2 Msym/s uncoded

Table 22. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=2)

Table 23. Bluetooth Low Energy RF receiver characteristics at 1 Msym/s LE coded (S=8)

6.3.6 Embedded reset and power control block characteristics

Table 24. Embedded reset and power control block characteristics

6.3.7 Supply current characteristics

location in memory and executed binary code.

• all I/O pins are in analog input mode
• all peripherals are disabled except when explicitly mentioned
• the flash memory access time is adjusted with the minimum wait states number
• when the peripherals are enabled f PCLK = fHCLK

Table 25. Current consumption

1. The current consumption in DEEPSTOP is measured considering the entire SRAM retained.

6.3.8 Wake-up time from low power modes

goes to low-power mode after WFI (wait for interrupt) instructions. Table 26. Low power mode wake-up timing

6.3.9 High speed crystal requirements

32 MHz crystal, with a resolution of 1 ppm. The requirements for the external 32 MHz crystal are reported in the table below. Table 27. HSE crystal requirements

1. XOTUNE programed at minimum code = 0
2. XOTUNE programed at center code = 32
3. XOTUNE programed at maximum code = 63

6.3.10 Low speed crystal requirements

32.768 kHz crystal are reported in the table below. Table 28. LSE crystal requirements

6.3.11 High speed ring oscillator characteristics

Table 29. HSI oscillator characteristics

6.3.12 Low speed ring oscillator characteristics

Table 30. LSI oscillator characteristics

6.3.13 PLL characteristics

Characteristics measured over recommended operating conditions unless otherwise specified. Table 31. PLL characteristics

6.3.14 Flash memory characteristics

The characteristics below are guaranteed by design. Table 32. Flash memory characteristics

Table 33. Flash memory endurance and data retention

6.3.15 Electrostatic discharge (ESD)

(3 parts x (n + 1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 34. ESD absolute maximum ratings

6.3.16 I/O port characteristics

conditions summarized in Table 15. General operating conditions. All I/Os are designed as CMOS-compliant. Table 35. I/O static characteristics

1. Max(V DDx) is the maximum value among all the I/O supplies.

All I/Os are CMOS-compliant (no software configuration required).

• The sum of currents sourced by all I/Os on VDD, plus the maximum consumption of MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD
• The sum of currents sunk by all I/Os on VSS, plus the maximum consumption of the MCU sunk on GND, cannot exceed the absolute maximum rating ΣIVGND. BlueNRG-LPS Operating conditions DS13819 - Rev 4 page 46/67

Table 36. Output voltage characteristics

1. CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

6.3.17 RSTN pin characteristics

The RSTN pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU. ambient temperature and supply voltage conditions summarized in Section 6.3.2 General operating conditions. Table 37. RSTN pin characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit. Figure 14. Recommended RSTN pin protection Note: The external reset circuit protects the device against parasitic resets. placed as close as possible to the device.

6.3.18 ADC characteristics

Table 38. ADC characteristics (HSI must be set to PLL mode)

6.3.19 Temperature sensor characteristics

Table 39. Temperature sensor characteristics

6.3.20 Timer characteristics

Table 40. TIM2/16/17 characteristics Table 41. IWDG min./max. timeout period at 32 kHz (LSE)

6.3.21 I2C interface characteristics

• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode plus (Fm+): bit rate up to 1 Mbit/s SDA and SCL I/O requirements are met with the following restrictions: SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive requirement in fast-mode plus is supported partially. This limits the maximum load Cload supported in fast-mode plus, given by these formulas:
• t r(SDA/SCL) = 0.8473 x Rp x Cload
• R p(min.) = [VDD - VOL(max)] / IOL(max) where Rp is the I2C lines pull-up. All I2C SDA and SCL I/Os embed an analog filter.

Table 42. I2C analog filter characteristics

6.3.22 SPI characteristics

conditions summarized in Table 15. General operating conditions.

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x V DD

Table 43. SPI characteristics

Figure 17. SPI timing diagram - master mode

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 VFQFPN32 package information

This VFQFPN is a 32 lead, 5 x 5 mm, 0.50 mm pitch, very fine pitch quad flat no lead package. Figure 18. VFQFPN32 - Outline

1. Package outline exclusive of any mold flashes dimensions and metal burrs.
2. Details of terminal 1 are optional but must be located on the top surface of the package by using either a

Package information

DS13819 - Rev 4 page 53/67

Table 44. VFQFPN32 - Mechanical data

1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. VFQFPN stands for thermally Enhanced very thin fine pitch quad flat package No lead . Very thin profile 0.80 < A ≤ 1.00

Figure 19. VFQFPN32 - Footprint example

7.2 WLCSP36 package information (01C1)

This WLCSP is a 36-ball, 2.652 x 2.592 mm, 0.40 mm pitch, wafer level chip scale array package. Figure 20. WLCSP36 - Outline

1. The terminal A1 on the bumps side is identified by a distinguishing feature (for instance by a circular "clear

area" - typically 0.1 mm diameter) and/or a missing bump. circular "clear area" - typically 0.5 mm diameter).

Table 45. WLCSP36 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 21. WLCSP36 - Footprint example

1. Dimensions are expressed in millimeters.

Table 46. WLCSP36 - Example of PCB design rules

7.3 Thermal characteristics

The maximum chip junction temperature (TJmax.) must never exceed the values in general operating conditions.

• T A max. is the maximum ambient temperature in °C
• Θ JA is the package junction-to-ambient thermal resistance, in °C/W
• PINT max. is the product of I DD and VDD, expressed in Watts. This is the maximum chip internal power PI/O max represents the maximum power dissipation on output pins:
• PI/O max. = Σ (V OL × IOL) + Σ ((VDD – VOH) × IOH) taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the applications. Note: When the SMPS is used, a portion of the power consumption is dissipated into the external inductor, therefore reducing the chip power dissipation. This portion depends mainly on the inductor ESR characteristics. Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the chip power consumption. Note: RF characteristics (such as: sensitivity, Tx power, consumption) are provided up to 85 °C.

Table 47. Package thermal characteristics

8 Ordering information

Table 48. Ordering information Figure 22. Ordering information device, contact your nearest ST sales office.

Ordering information

DS13819 - Rev 4 page 59/67

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise. BlueNRG-LPS DS13819 - Rev 4 page 60/67

Revision history

Table 49. Document revision history 09-Dec-2021 1 Initial release. Added reference to integrated passive device (IPD) in Features section. Added Section 2.5.2 IPDs for BlueNRG-LPS. Figure 18. VFQFPN32 - Outline. Corrected Section 7.2 WLCSP36 package information (01C1). Added reference to ANTENNA_ID[2] for PB2 pin in Table 4. Pin descriptions.

Contents

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DS13819 - Rev 4 page 64/67

IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2023 STMicroelectronics – All rights reserved BlueNRG-LPS DS13819 - Rev 4 page 67/67