BF512F

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Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin Embedded Processor ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without no tice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2011 Analog Devices, Inc. All rights reserved.

FEATURES

Up to 400 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages. See Operating Conditions on Page 20 Qualified for Automotive Applications. See Automotive Products on Page 65 168-ball CSP_BGA or 176-lead LQFP with exposed pad MEMORY 116K bytes of on-chip memory External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories Optional 4M bit SPI flash with boot option Flexible booting options from internal SPI flash, OTP memory, external SPI/parallel memories, or from SPI/UART host devices Code security with Lockbox secure technology One-time-programmable (OTP) memory Memory management unit providing memory protection PERIPHERALS IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 support (ADSP-BF518/ADSP-BF518F only) Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats 2 dual-channel, full-duplex synchronous serial ports (SPORTs), supporting 8 stereo I2S channels 12 peripheral DMAs, 2 mastered by the Ethernet MAC 2 memory-to-memory DMAs with external request lines Event handler with 56 interrupt inputs 2 serial peripheral interfaces (SPI) Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA

2 UARTs with IrDA support

2-wire interface (TWI) controller Eight 32-bit timers/counters with PWM support 3-phase 16-bit center-based PWM unit 32-bit general-purpose counter Real-time clock (RTC) and watchdog timer 32-bit core timer 40 general-purpose I/Os (GPIOs) Debug/JTAG interface On-chip PLL capable of frequency multiplication JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS OTP 3-PHASE PWM WATCHDOG TIMERRTC TWI SPORT1-0 RSI (SDIO) PPI UART1–0 SPI0

4 Mbit SPI Flash

(See Table 1) SPI1 TIMER7–0 COUNTER EMAC BOOT ROM DMA EXTERNAL BUS INTERRUPT CONTROLLER DMA CONTROLLER DATA MEMORY INSTRUCTION MEMORY

16 DMA CORE BUS

FLASH, SDRAM CONTROL PORTS B

Rev. B | Page 2 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F TABLE OF CONTENTS Designing an Emulator-Compatible

REVISION HISTORY

1/11—Rev. A to Rev. B This data sheet release coincides with the release of the revised ADSP-BF51x Blackfin Processor Hardware Reference. All redundant information has been removed. Revised several specifications in Operating Conditions ... 20 Revised f VCO specification in Phase-Locked Loop Operating Revised several specifications in Electrical Characteristics 22 Added additional fCKIN specification for automotive models in Changed the parameter VDDMEM to VDDEXT in Asynchronous Revised t HFSPE specification in Parallel Peripheral Interface Tim- Revised tHFSPE specification and added the tPSUD specification in Revised the tWL and tWH specifications in Revised tWL, tWH and tOH specification in RSI Controller Timing Revised tMDCIH and tMDCOH specifications in 10/100 Ethernet Corrected dimensions in 168-Ball Chip Scale Package Ball Grid

ties into a single instruction-set architecture. processing in one integrated package. process 8-, 16-, or 32-bit data from the register file. register file and instruction constant fields. cycle, accumulating the results into the 40-bit accumulators. and 8-bit subtract/absolute value/accumulate (SAA) operations. Table 1. Processor Comparison

quad 16-bit operations are possible. instructions with data dependencies. registers from unintended access. unrestricted access to the system and core resources. Figure 1. Blackfin Processor Core

resources in a single instruction cycle. resulting in fast and efficient software implementations. nal memory space is shown in Figure 2. memory that provide high bandwidth access to the core. ity. This memory block is accessed at full processor speed. as data SRAM and cannot be configured as cache memory. to four internal SDRAM banks, improving overall performance. the package of the processor and connected to SPI0. write protection and for fast erase and byte-program. Figure 2. ADSP-BF51x Inte rnal/External Memory Map

Rev. B | Page 6 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F The processors internally connect to the flash memory die with the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO sig- nals similar to an external SPI flash. To further provide a secure processing environment, these internally connected signals are not exposed outside of the package. For this reason, program- ming the ADSP-BF51xF flash memory is performed by running code on the processor andcannot be programmed from external signals. Data transfers between the SPI flash and the processor cannot be probed externally. The flash memory has the follow- ing additional features

• Serial Interface Architecture—SPI compatible with Mode 0 and Mode 3
• Superior Reliability—Endurance of 100,000 cycles and greater than 100 years data retention
• Flexible Erase Capability—Uni form 4K Byte sectors and uniform 32 and 64K Byte overlay blocks
• Fast Erase and Byte-Program —Chip-erase time = 125 ms (typical), Sector-/Block-Erase Time = 62 ms (typical) Byte- Program Time = 50 μS (typical)
• Auto Address Increment ( AAI) Programming—Decreases total chip programming time over byte-program operations
• End-of-Write Detection—Software polling the BUSY bit in status register, busy status readout on SO pin
• Software Write Protection—W rite protection through block-protection bits in status register One-Time Programmable Memory The processors have 64K bits of one-time programmable non- volatile memory that can be programmed by the developer only once. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. The OTP memory allows both public and private data to be stored on-chip. In addition to storing public and private key data for applications requiring security, OTP allows developers to store completely user-definable data such as customer ID, product ID, and MAC address. Therefore, generic parts can be supplied which are then programmed and protected by the developer within this non-volatile memory. I/O Memory Space The processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory- mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting from ROM The processors contain a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. If the processors are configured to boot from boot ROM memory space, the pro- cessor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 14. EVENT HANDLING The event controller handles all asynchronous and synchronous events to the processor. The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher priority event takes precedence over servicing of a lower priority event. The controller provides support for five different types of events:
• Emulation—An emulation even t causes the processor to enter emulation mode, allowing command and control of the processor through the JTAG interface.
• Reset—This event resets the processor.
• Nonmaskable Interrupt (N MI)—The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system.
• Exceptions—Events that occur synchronously to program flow; that is, the exception is taken before the instruction is allowed to complete. Conditions such as data alignment violations and undefined instructions cause exceptions.
• I n t e r r u p t s — E v e n t s t h a t o c c ur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The event controller consists of two stages, the core event con- troller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all system events. Conceptually, inter- rupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processors. The inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities are described in the ADSP-BF51x Blackfin Processor Hardware Reference Manual “System Interrupts” chapter.

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Rev. B | Page 7 of 68 | January 2011 System Interrupt Controller (SIC) The system interrupt controller provides the mapping and rout- ing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the processors provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the interrupt assignment registers (SIC_IARx). See the ADSP-BF51x Blackfin Processor Hardware Reference Manual “System Interrupts” chapter for the inputs into the SIC and the default mappings into the CEC. The SIC allows further control of event processing by providing three pairs of 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events. For more information, see the ADSP-BF51x Blackfin Processor Hardware Reference Manual “System Inter- rupts” chapter. DMA CONTROLLERS The ADSP-BF51x processors have multiple independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor's internal memories and any of its DMA- capable peripherals. Additionally, DMA transfers can be accom- plished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous mem- ory controller. DMA-capable peripherals include the Ethernet MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual DMA-capable peripheral has at least one dedicated DMA channel. The processors’ DMA controller supports both one-dimen- sional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2-D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de- interleaved on the fly. Examples of DMA types supported by the DMA controller include:

• A single, linear buffer that stops upon completion
• A circular, auto-refreshing bu ffer that interrupts on each full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2 - D D M A u s i n g a n a r r a y o f d e s criptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, there are two memory DMA channels that transfer data between the vari- ous memories of the processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal pro- cessor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a stan- dard register-based autobuffer mechanism. The processors also have an external DMA controller capability via dual external DMA request signals when used in conjunc- tion with the external bus interface unit (EBIU). This functionality can be used when a high speed interface is required for external FIFOs and high bandwidth communica- tions peripherals. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow mem- ory DMA to have an increased priority on the external bus relative to the core. PROCESSOR PERIPHERALS The ADSP-BF51x processors contain a rich set of peripherals connected to the core via several high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see Figure 1 on Page 4). The processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexi- ble management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the proces- sor and system to many application scenarios. All of the peripherals, except for the general-purpose I/O, rotary counter, TWI, three-phase PWM, real-time clock, and timers, are supported by a flexible DMA structure. There are also sepa- rate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. Real-Time Clock The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the proces- sors. The RTC peripheral has a dedicated power supply so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several pro- grammable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.

enabled and the counter underflows, an interrupt is generated. from sleep mode upon generation of any RTC wakeup event. condition or software error. clock or to a count of external signals. clock for generation of operating system periodic interrupts. switched reluctance motors (SRM).

• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementa tion which permits smooth transition to full ON and full OFF states
• Possibility to sync hronize the PWM generation to an exter- nal synchronization
• Special provisions for BDCM operation (crossover and output enable functions)
• Wide variety of special switched reluctance (SR) operating modes
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal General-Purpose (GP) Counter A 32-bit GP counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or man- ual thumb wheels. The counter can also operate in general- purpose up/down count modes. Then, count direction is either controlled by a level-sensitive input signal or by two edge detectors.

Figure 3. External Components for RTC NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Rev. B | Page 9 of 68 | January 2011 A third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. All three signals have a programmable debouncing circuit. An internal signal forwarded to the GP timer unit enables one timer to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. Serial Ports The ADSP-BF51x processors incorporate two dual-channel syn- chronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the fol- lowing features: Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA chan- nels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. In this configura- tion, one SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in five modes:

• Standard DSP serial mode
• Multichannel (TDM) mode 2S mode
• P a c k e d I2S mode
• L e f t - j u s t i f i e d m o d e Serial Peripheral Interface (SPI) Ports The processors have two SPI-compatible ports (SPI0 and SPI1) that enable the processor to communicate with multiple SPI- compatible devices. The SPI interface uses three signals for transferring data: two data signals (master output-slave input–MOSI, and master input-slave output–MISO) and a clock signal (serial clock–SCK). An SPI chip select input signal (SPIxSS ) lets other SPI devices select the processor, and multiple SPI chip select output signals let the processor select other SPI devices. The SPI select signals are reconfigured general-purpose I/O signals. Using these signals, the SPI port provides a full-duplex, syn- chronous serial interface, which supports both master/slave modes and multimaster environments. The SPI port baud rate and clock phase/polarities are program- mable, and it has an integrated DMA channel, configurable to support transmit or receive data streams. The SPI’s DMA chan- nel can only service unidirectional accesses at any given time. UART Ports The processors provide two full-duplex universal asynchronous receiver/transmitter (UART) ports, which are fully compatible with PC-standard UARTs. Each UART port provides a simpli- fied UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multi-drop bus (MDB) systems. A frame is terminates by one, one and a half, two or two and a half stop bits. The UART ports support automatic hardware flow control through the Clear To Send (CTS) input and Request To Send (RTS) output with programmable assertion FIFO levels. To help support the Local Interconnect Network (LIN) proto- cols, a special command causes the transmitter to queue a break command of programmable bit length into the transmit buffer. Similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. The capabilities of the UARTs are further extended with sup- port for the Infrared Data Association (IrDA®) serial infrared physical layer link specification (SIR) protocol. 2-Wire Interface (TWI) The processors include a TWI module for providing a simple exchange method of control data between multiple devices. The TWI is compatible with the widely used I2C® bus standard. The TWI module offers the capabilities of simultaneous master and slave operation, support for both 7-bit addressing and multime- dia data arbitration. The TWI interface utilizes two signals for transferring clock (SCL) and data (SDA) and supports the pro- tocol at speeds up to 400k bits/sec. The TWI interface signals are compatible with 5 V logic levels. Additionally, the processor’s TWI module is fully compatible with serial camera control bus (SCCB) functionality for easier control of various CMOS camera sensor devices. Removable Storage Interface (RSI) The RSI controller, available on the ADSP-BF514, ADSP- BF516, ADSP-BF518, and ADSP-BF518F acts as the host inter- face for multi-media cards (MMC), secure digital memory cards (SD Card), secure digital input/output cards (SDIO), and CE- ATA hard disk drives. The following list describes the main fea- tures of the RSI controller.
• Support for a single MMC, SD memory, SDIO card or CE- ATA hard disk drive
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• A ten-signal external interf ace with clock, command, and up to eight data lines
• Card detection using one of the data signals
• Card interface clock generation from SCLK
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and disable

Rev. B | Page 10 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F 10/100 Ethernet MAC The ADSP-BF516/ADSP-BF516F and ADSP- BF518/ADSPBF518F processors offer the capability to directly connect to a network by way of an embedded fast Ethernet media access controller (MAC) that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec) operation. The 10/100 Ethernet MAC peripheral on the processor is fully com- pliant to the IEEE 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. Some standard features are:

• Support of MII and RMII pr otocols for external PHYs
• Full duplex and half duplex modes
• Data framing and encapsulation: generation and detection of preamble, length padding, and FCS
• Media access management (in half-duplex operation): col- lision and contention handling, including control of retransmission of collision frames and of back-off timing
• Flow control (in full-duplex operation): generation and detection of pause frames
• Station management: generation of MDC/MDIO frames for read-write access to PHY registers
• Operating range for active and sleep operating modes, see Table 43 on Page 45 and Table 44 on Page 46
• Internal loopback from transmit to receive Some advanced features are:
• Buffered crystal output to ex ternal PHY for support of a single crystal system
• Automatic checksum computat ion of IP header and IP payload fields of Rx frames
• Independent 32-bit descriptor-driven receive and transmit DMA channels
• Frame status delivery to me mory through DMA, including frame completion semaphores for efficient buffer queue management in software
• Tx DMA support for separate descriptors for MAC header and payload to eliminate buffer copy operations
• Convenient frame alignment modes support even 32-bit alignment of encapsulated receive or transmit IP packet data in memory after the 14-byte MAC header
• Programmable Ethernet event interrupt supports any com- bination of:
• Selected receive or transmit frame status conditions
• PHY interrupt condition
• Wakeup frame detected
• Selected MAC management counter(s) at half-full
• DMA descriptor error
• 47 MAC management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value
• Programmable receive address filters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, uni- cast, control, and damaged frames
• Advanced power management supporting unattended transfer of receive and transmit frames and status to/from external memory via DMA during low power sleep mode
• System wakeup from sleep operating mode upon magic packet or any of four user-definable wakeup frame filters
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
• In RMII operation, seven unused signals may be config- ured as GPIO signals for other purposes IEEE 1588 Support The IEEE 1588 standard is a precision clock synchronization protocol for networked measurement and control systems. The ADSP-BF518/ADSP-BF518F processors include hardware sup- port for IEEE 1588 with an integrated precision time protocol synchronization engine (PTP_TSYNC). This engine provides hardware assisted time stamping to improve the accuracy of clock synchronization between PTP nodes. The main features of the PTP_SYNC engine are:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro- tocol standards
• Hardware assisted ti me stamping capable of up to 12.5 ns resolution
• Lock adjustment
• Programmable PTM message support
• Dedicated interrupts
• Programmable alarm
• Multiple input clock sources (SCLK, MII clock, external clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events Ports Because of the rich set of peripherals, the processors group the many peripheral signals to four ports—port F, port G, port H, and port J. Most of the associated pins/balls are shared by multi- ple signals. The ports function as multiplexer controls. General-Purpose I/O (GPIO) The ADSP-BF51x processors have 40 bidirectional, general- purpose I/O (GPIO) signals allocated across three separate GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ- ated with Port F, Port G, and Port H, respectively. Each GPIO-capable signal shares functionality with other peripherals via a multiplexing scheme; however, the GPIO functionality is the default state of the device upon power-up. Neither GPIO output nor input drivers are active by default. Each general-pur- pose port signal can be individually controlled by manipulation of the port control, status, and interrupt registers.

synchronization signals, and up to 16 data signals.

• Active video only mode—The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI.
• Vertical blanking only mode—T he PPI only transfers verti- cal blanking interval (VBI) data, as well as horizontal blanking information and control byte sequences on VBI lines.
• Entire field mode—The entire incoming bitstream is read in through the PPI. This includes active video, control pre- amble sequences, and ancillary data that may be embedded in horizontal and vertical blanking intervals. Though not explicitly supported, ITU-R-656 output functional- ity can be achieved by setting up the entire frame structure (including active video, blanking, and control information) in memory and streaming the data out the PPI in a frame sync-less mode. The processor’s 2-D DMA features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on a per-frame basis. The general-purpose modes of the PPI are intended to suit a wide variety of data capture and transmission applications. The modes are divided into four main categories, each allowing up to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs These modes support ADC/DAC connections, as well as video communication with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. Code Security with Lockbox Secure Technology A security system consisting of a blend of hardware and soft- ware provides customers with a flexible and rich set of code security features with Lockbox® secure technology. Key features include:
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation The security scheme is based upon the concept of authentica- tion of digital signatures using standards-based algorithms and provides a secure processing environment in which to execute code and protect assets. DYNAMIC POWER MANAGEMENT The ADSP-BF51x processors provide four operating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation. When configured for a 0 V core supply voltage, the processor enters the hibernate state. Control of clocking to each of the processor peripherals also reduces power consumption. See Table 2 for a summary of the power settings for each mode. Full-On Operating Mode—Maximum Performance In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency. This is the power-up default execution state in which maximum per- formance can be achieved. The processor core and all enabled peripherals run at full speed. Active Operating Mode—Moderate Power Savings In the active mode, the PLL is enabled but bypassed. Because the PLL is bypassed, the processor’s core clock (CCLK) and system clock (SCLK) run at the input clock (CLKIN) frequency. In this mode, the CLKIN to CCLK multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. DMA access is available to appropriately configured L1 memories.

Table 2. Power Settings

re-enabled before transitioning to the full-on or sleep modes. cally an external event or RTC activity wakes up the processor. power applied without drawing unwanted current. cate the occurrence of wakeup events. tion and through the subsequent reset sequence. ture/peripheral is not used. quency (fCCLK) to be dynamically controlled. Table 3. Power Domains

down input of many common regulators. refer to the ADSP-BF51x Blackfin Processor Hardware Reference. an external clock oscillator. clock is used, the XTAL pin/ball must be left unconnected. devices over temperature range.

25 MHz or 50 MHz crystal may be applied directly to the pro-

connected to an external Ethernet MII or RMII PHY device. by a software instruction sequence. Figure 4. External Crystal Connections Figure 5. Frequency Mo dification Methods RESISTOR VALUE SHOULD BE REDUCED TO 0 /H9024.

All on-chip peripherals are clocked by the system clock (SCLK).

1. Table 4 illustrates typical system clock ratios.

the appropriate values to the PLL divisor register (PLL_DIV). changed by means of the CSEL1–0 bits of the PLL_DIV register. Table 5. This programmable core clock capability is useful for fast core frequency modifications. VDDEXT, and VDDMEM voltages (see Table 11 on Page 21). cessor receives data from external host devices.

• Idle/no boot mode (BMODE = 0x0)—In this mode, the processor goes into idle. The idle boot mode helps recover from illegal operating modes, such as when the user has mis configured the OTP memory.
• Boot from 8-bit or 16-bit external flash memory (BMODE = 0x1)—In this mode, the boot kernel loads the first block header from address 0x2000 0000 and—depend- ing on instructions containing in the header—the boot kernel performs 8-bit or 16-bit boot or starts program exe- cution at the address provided by the header. By default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle R/W access times, 4-cycle setup). The ARDY is not enabled by default, but it can be enabled by OTP programming. Similarly, all interface behavior and timings can be customized by OTP programming. This includes activation of burst-mode or page-mode operation. In this mode, all signals belonging to the asynchronous interface are enabled at the port muxing level.
• Boot from internal SPI memory (BMODE = 0x2)—The processor uses the internal PH8 GPIO signal to load code previously loaded to the 4 Mbit internal SPI flash con- nected to SPI0. Only available on the ADSP-BF512F/ ADSP-BF514F/ADSP-BF516F/ADSP-BF518F.
• Boot from external SPI EEPROM or flash (BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit address- able devices are supported. The processor uses the PG15 GPIO signal (at SPI0SEL2 ) to select a single SPI EEPROM/flash device connected to the SPI0 interface; then submits a read command and successive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SSEL and MISO signals. By default, a value of 0x85 is written to the SPI0_BAUD register.
• Boot from SPI0 host device (BMODE = 0x4)—The proces- sor operates in SPI slave mode and is configured to receive the bytes of the LDR file from an SPI host (master) agent. In the host, the HWAIT signal must be interrogated by the

Table 4. Example System Clock Ratios Table 5. Core Clock Ratios Table 6. Booting Modes

000 Idle - No boot

001 Boot from 8- or 16-bit external flash memory

010 Boot from internal SPI memory

011 Boot from external SPI memory (EEPROM or flash)

100 Boot from SPI0 host

101 Boot from OTP memory

110 Boot from SDRAM

111 Boot from UART0 Host

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Rev. B | Page 15 of 68 | January 2011 host before every transmitted byte. A pull-up resistor is required on the SPI0SS input. A pull-down on the serial clock may improve signal quality and booting robustness.

• Boot from OTP memory (BMODE = 0x5)—This provides a stand-alone booting method. The boot stream is loaded from on-chip OTP memory. By default the boot stream is expected to start from OTP page 0x40 on and can occupy all public OTP memory up to page 0xDF. This is 2560 bytes. Since the start page is programmable the maximum size of the boot stream can be extended to 3072 bytes.
• Boot from SDRAM (BMODE = 0x6)—This is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. The SDRAM is expected to contain a valid boot stream and the SDRAM controller must be configured by the OTP settings.
• Boot from UART0 host (BMODE = 0x7)—Using an auto- baud handshake sequence, a boot-stream formatted program is downloaded by the host. The host selects a bit rate within the UART clocking capabilities. When performing the autobaud, the UART expects a “@” (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the RX0 signal to determine the bit rate. The UART then replies with an acknowledgement com- posed of 4 bytes (0xBF—the value of UART0_DLL and 0x00—the value of UART0_DLH). The host can then download the boot stream. To hold off the host the Blackfin processor signals the host with the boot host wait (HWAIT) signal. Therefore, the host must monitor HWAIT before every transmitted byte. For each of the boot modes, a 16-byte header is first read from an external memory device. The header specifies the number of bytes to be transferred and the memory destination address. Multiple memory blocks may be loaded by any boot sequence. Once all blocks are loaded, program execution commences from the address stored in the EVT1 register. Prior to booting, the pre-boot routine interrogates the OTP memory. Individual boot modes can be customized or even dis- abled based on OTP programming. External hardware, especially booting hosts may watch the HWAIT signal to deter- mine when the pre-boot has finished and the boot kernel starts the boot process. By programming OTP memory, the user can instruct the preboot routine to also customize the PLL, the SDRAM Controller, and the Asynchronous Interface. The boot kernel differentiates between a regular hardware reset and a wakeup-from-hibernate event to speed up booting in the later case. Bits 6-4 in the system reset configuration (SYSCR) register can be used to bypass pre-boot routine and/or boot ker- nel in case of a software reset. They can also be used to simulate a wakeup-from-hibernate boot in the software reset case. The boot process can be further customized by “initialization code.” This is a piece of code that is loaded and executed prior to the regular application boot. Typically, this is used to configure the SDRAM controller or to speed up booting by managing PLL, clock frequencies, wait states, or serial bit rates. The boot ROM also features C-callable function entries that can be called by the user application at run time. This enables sec- ond-stage boot or boot management schemes to be implemented with ease. INSTRUCTION SET DESCRIPTION The Blackfin processor family assembly language instruction set employs an algebraic syntax designed for ease of coding and readability. The instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. The instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the processor core resources in a single instruction. Coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of opera- tion, allowing multiple levels of access to core processor resources. The assembly language, which takes advantage of the proces- sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MC U features are optimized for both 8-bit and 16-bit operations.
• A multi-issue load/store modified-harvard architecture, which supports two 16-bit MACs or four 8-bit ALUs plus two load/store plus two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified 4G byte memory space, providing a simplified program- ming model.
• Microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and supervisor stack pointers.
• Code density enhancements, which include intermixing of 16-bit and 32-bit instructions (no mode switching, no code segregation). Frequently used instructions are encoded in 16 bits. DEVELOPMENT TOOLS The ADSP-BF51x processors are supported with a complete set of CROSSCORE® software and hardware development tools, including Analog Devices emulators and VisualDSP++® devel- opment environment. The same emulator hardware that supports other Blackfin processors also fully emulates the ADSP-BF51x processors. For more information about develop- ment tools, visit www.analog.com. EZ-KIT Lite Evaluation Board For evaluation of the processors, use the EZ-KIT Lite® board being developed by Analog Devices. The board comes with on- chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available.

Rev. B | Page 16 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F DESIGNING AN EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET) The Analog Devices family of emulators are tools that every sys- tem developer needs in order to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG processor. The emulator uses the TAP to access the internal features of the pro- cessor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the processor system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see (EE-68) Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSP-BF512/ ADSP-BF514/ADSP-BF516/ADSP-BF518 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website:

• Getting Started With Blackfin Processors
• ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Blackfin Processor Hardware Reference
• ADSP-BF53x/BF56x Blackfin Processor Programming Reference
• ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Blackfin Processor Anomaly List RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the "signal chain" entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Application Signal Chains page in the Circuits from the Lab TM site (http://www.analog.com/circuits) provides:
• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection guides and application information
• Reference designs applying be st practice design techniques LOCKBOX SECURE TECHNOLOGY DISCLAIMER Analog Devices products containing Lockbox Secure Technol- ogy are warranted by Analog Devices as detailed in the Analog Devices Standard Terms and Conditions of Sale. To our knowl- edge, the Lockbox Secure Technology, when used in accordance with the data sheet and hardware reference manual specifica- tions, provides a secure method of implementing code and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL EXPRESS AND IMPLIED WARRANTIES THAT THE LOCK- BOX SECURE TECHNOLOGY CANNOT BE BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTEL- LECTUAL PROPERTY.

2C specification for the proper resistor value. should be chosen to match the average board trace impedance. Table 7. Signal Descriptions

Power Supplies ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 20. 1 See Output Drive Currents on Page 50 for more information about each driver type. is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor. 3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signa l polarity. 4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).

Rev. B | Page 20 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS Parameter Conditions Min Nominal Max Unit VDDINT Internal Supply Voltage Industrial Models 1.14 1.47 V Internal Supply Voltage Commercial Models 1.10 1.47 V Internal Supply Voltage Automotive Models 1.33 1.47 V V DDEXT 1, 2 1 Must remain powered (even if the associated function is not used). 2 VDDEXT is the supply to the GPIO. External Supply Voltage 1.8 V I/O, Nonautomotive Models 1.7 1.8 1.9 V External Supply Voltage 2.5 V I/O, Nonautomotive Models 2.25 2.5 2.75 V External Supply Voltage 3.3 V I/O, All Models 3.0 3.3 3.6 V VDDMEM 3 Pins/balls that use VDDMEM are DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These pins/balls are not tolerant to voltages higher than VDDMEM. When using any of the asynchronous memory signals AMS3–2, ARDY, or AOE VDDMEM and VDDEXT must be shorted externally. MEM Supply Voltage 1.8 V I/O, Nonautomotive Models 1.7 1.8 1.9 V MEM Supply Voltage 2.5 V I/O, Nonautomotive Models 2.25 2.5 2.75 V MEM Supply Voltage 3.3 V I/O, All Models 3.0 3.3 3.6 V VDDRTC 4 If not used, power with VDDEXT. RTC Power Supply Voltage 2.25 3.6 V VDDFLASH

4 Internal SPI Flash Supply

1.7 1.8 1.9 V VDDOTP OTP Supply Voltage 2.25 2.5 2.75 V VPPOTP OTP Programming Voltage For Reads1 2.25 2.5 2.75 V For Writes5 5 The VPPOTP voltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent on voltage and junction temperature) over the lifetime of the part. 6.9 7.0 7.1 V VIH High Level Input Voltage6, 7 6 Bidirectional pins/balls (PF15–0, PG15–0, PH7–0) and input pins/balls (RTXI, TCK, TDI, TMS, TRST , CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF51x are 3.3 V tolerant (always accept up to 3.6 V maximum V IH). Voltage compliance (on outputs, VOH) is limited by the VDDEXT supply voltage. 7 Parameter value applies to all input and bi directional pins/balls except SDA and SCL. VDDEXT/VDDMEM = 1.90 V 1.2 V High Level Input Voltage6, 7 VDDEXT/VDDMEM = 2.75 V 1.7 V High Level Input Voltage6, 7 VDDEXT/VDDMEM = 3.6 V 2 V VIHTWI High Level Input Voltage V DDEXT = 1.90 V/2.75 V/3.6 V 0.7 x V BUSTWI VBUSTWI 8 The VIHTWI min and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V BUSTWI min and max values in Table 8. V VIL Low Level Input Voltage6, 7 VDDEXT/VDDMEM = 1.7 V 0.6 V Low Level Input Voltage6, 7 VDDEXT/VDDMEM = 2.25 V 0.7 V Low Level Input Voltage6, 7 VDDEXT/VDDMEM = 3.0 V 0.8 V VILTWI Low Level Input Voltage V DDEXT = Minimum 0.3 x V BUSTWI 9 SDA and SCL are pulled up to VBUSTWI. See Table 8. V Junction Temperature 168-Ball CSP_BGA @ T AMBIENT = 0°C to +70°C 0 +95 °C Junction Temperature 168-Ball CSP_BGA @ T AMBIENT = –40°C to +85°C –40 +105 °C Junction Temperature 176-Lead LQFP @ T AMBIENT = 0°C to +70°C 0 +95 °C Junction Temperature 176-Lead LQFP @ T AMBIENT = –40°C to +85°C –40 +105 °C

register. Set this register prior to using the TWI port. not to exceed the maximum core clock and system clock. Table 10 describes phase-locked loop operating conditions. Table 8. TWI_DT Field Selections and V DDEXT/VBUSTWI Table 9. Core Clock (CCLK) Requirements Table 10. Phase-Locked Loop Operating Conditions

72 Instruction Rate 1 MHz

84 Instruction Rate 1 MHz

1 For more information, see Ordering Guide on Page 65. Table 11. SCLK Conditions

1.8 V Nominal

1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 28 on Page 31.

Rev. B | Page 22 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Typical Max Unit VOH High Level Output Voltage V DDEXT /VDDMEM = 1.7 V, IOH =– 0 . 5m A 1.35 V High Level Output Voltage V DDEXT /VDDMEM = 2.25 V, IOH =– 0 . 5m A High Level Output Voltage V DDEXT /VDDMEM = 3.0 V, IOH =– 0 . 5m A 2.4 V VOL Low Level Output Voltage V DDEXT /VDDMEM = 1.7/2.25/3.0 V, I OL =2 . 0m A 0.4 V IIH 1 High Level Input Current V DDEXT /VDDMEM =3.6 V , VIN =3 . 6V 10 μA IIL 1 Low Level Input Current V DDEXT /VDDMEM =3.6 V , VIN = 0 V 10 μA IIHP 2 High Level Input Current JTAG V DDEXT = 3.6 V, VIN = 3.6 V 75 μA IOZH 3 Three-State Leakage Current V DDEXT /VDDMEM= 3.6 V, VIN =3 . 6V 10 μA IOZHTWI 4 Three-State Leakage Current V DDEXT =3.0 V , VIN = 5.5 V 10 μA IOZL 3 Three-State Leakage Current V DDEXT /VDDMEM= 3.6 V, VIN = 0 V 10 μA CIN 5, 6 Input Capacitance f IN = 1 MHz, TAMBIENT = 25°C, VIN =2 . 5V 58 p F CINTWI 4, 6 Input Capacitance f IN = 1 MHz, TAMBIENT = 25°C, VIN =2 . 5V 15 pF IDDDEEPSLEEP

7 VDDINT Current in Deep Sleep

VDDINT = 1.3 V, fCCLK = 0 MHz, fSCLK =0M H z , TJ = 25°C, ASF = 0.00 2.1 mA IDDSLEEP VDDINT Current in Sleep Mode V DDINT = 1.3 V, fSCLK = 25 MHz, TJ = 25°C 5.5 mA IDD-IDLE VDDINT Current in Idle V DDINT = 1.3 V, fCCLK = 50 MHz, fSCLK =2 5M H z , TJ = 25°C, ASF = 0.41 12 mA IDD-TYP VDDINT Current V DDINT = 1.3 V, fCCLK = 300 MHz, fSCLK =2 5M H z , TJ = 25°C, ASF = 1.00 77 mA IDD-TYP VDDINT Current V DDINT = 1.4 V, fCCLK = 400 MHz, fSCLK =2 5M H z , TJ = 25°C, ASF = 1.00 108 mA IDDHIBERNATE 8 Hibernate State Current V DDEXT =VDDMEM =VDDRTC =3 . 3 0 VVDDOTP =VPPOTP =2.5 V , TJ = 25°C, CLKIN = 0 MHz @ TJ = 25°C 40 μA IDDRTC VDDRTC Current V DDRTC = 3.3 V, TJ = 25°C 20 μA IDDSLEEP 8, 9 VDDINT Current in Sleep Mode f CCLK = 0 MHz, fSCLK > 0 MHz Table 13 + (0.20 × VDDINT × fSCLK) mA10 IDDDEEPSLEEP 8, 10 VDDINT Current in Deep Sleep Mode fCCLK = 0 MHz, fSCLK = 0 MHz Table 13 mA

1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics

due to transistor switching in the core clock (CCLK) domain. domain, which is included in the IDDINT specification equation. 2 Applies to JTAG input balls (TCK, TDI, TMS, TRST). 3 Applies to three-statable balls. 4 Applies to bidirectional balls SCL and SDA. 5 Applies to all signal balls, except SCL and SDA. 6 Guaranteed, but not tested. 7 See the ADSP-BF51x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 8 Includes current on VDDEXT, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low. 9 Guaranteed maximum specifications. 10Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. 11See Table 12 for the list of IDDINT power vectors covered. Table 12. Activity Scaling Factors (ASF) 1

1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors

Table 13. Static Current—I DD-DEEPSLEEP (mA) 1 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20. Table 14. Dynamic Current in CCLK Domain (mA, with ASF = 1.0) 1 1 The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 22 . 2 Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20. Table 15. Reliability Characteristics Table 16. AC Operating Characteristics

1 Serial Clock Frequency 25 MHz

2 Byte-Program 60 μs

1 Maximum clock frequency for Read instruction, 0x03, is 20 MHz. 2 AAI-Word Program TBP maximum specificatio n is also at 60 μs maximum time.

nent damage to the device. These are stress ratings only. gramming time for the processor is shown in Table 19. ments as shown in the Electrical Characteristics table. Table 17. Absolute Maximum Ratings 1 Applies to 100% transient duty cycle. For other duty cycles see Table 18. fications, the range is VDDEXT ± 0.2. 3 Applies to signals SCL, SDA. 4 For more information, see the information preceding Table 20 and Table 21. Table 18. Maximum Duty Cycle for Input Transient Voltage 1 1 Applies to all signal pins/balls with the exception of CLKIN, XTAL.

2 The individual values cannot be combined for analysis of a single instance of

3 Duty cycle refers to the percentage of time the signal exceeds the value for the

overshoot or undershoot as a percentage of the period of occurrence. Table 19. Maximum OTP Memory Programming Time Table 20. Total Current Pin Groups–V DDMEM Groups

1 DATA15, DATA14, DATA13, DATA12, DATA11, DATA10

2 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4

3 DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18

4 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13

5 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7

6 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1

Table 21. Total Current Pin Groups–V DDEXT Groups

1 PF9, PF8, PF7, PF6, PF5, PF4, PF3, PF2

2 PF1, PF0, PG15, PG14, PG13, PG12, PG11, PG10

3 PG9, PG8, PG7, PG6, PG5, PG4, PG3, PG2, BMODE0,

6 PH7, PH6, PH5, PH4, PH3, PH2, PH1, PH0

7 PF15, PF14, PF13, PF12 , PF11, SDA, SCL, PF10

Rev. B | Page 26 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

PACKAGE INFORMATION

The information presented in Figure 6 and Table 22 provides details about the package branding for the processor. For a com- plete listing of product availability, see Ordering Guide on Page 65. ESD SENSITIVITY Figure 6. Product Information on Package Table 22. Package Br and Information ESD (electrostatic discharge) sensitive device. may occur on devices subjected to high energy ESD. avoid performance degradation or loss of functionality.

the processor’s speed grade. Table 23. Clock and Reset Timing 1 Applies to PLL bypass mode and PLL nonbypass mode. 2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 through Table 11 on Page 21. 3 The tCKIN period (see Figure 7) equals 1/fCKIN. 4 If the DF bit in the PLL_CTL register is set, the minimum f CKIN specification is 24 MHz for commercial/industri al models and 28 MHz for automotive models. 5 Applies after power-up sequence is complete. See Table 24 and Figure 8 for power-up reset timing. Figure 7. Clock and Reset Timing Table 24. Power-Up Reset Timing

Table 26. Asynchronous Memory Read Cycle Timing 1 Output pins/balls include AMS3–0 , ABE1–0, ADDR19–1, AOE , ARE. Figure 10. Asynchronous Memory Read Cycle Timing

2 CYCLES

3 CYCLES

1 CYCLE

Table 27. Asynchronous Memory Write Cycle Timing 1 Output pins/balls include AMS3–0 , ABE1–0 , ADDR19–1, DATA15–0, AOE, AWE. Figure 11. Asynchronous Memory Write Cycle Timing

Table 28. SDRAM Interface Timing 1 The tSCLK value is the inverse of the fSCLK specification discussed in Table 11 on Page 21. Package type and reduced supply voltages affect the best-case value listed here. 2 Command pins/balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 12. SDRAM Interface Timing NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Table 29. External DMA Request Timing 1 VDDMEM are NOT equal may require level shifting logic for correct operation. Figure 13. External DMA Request Timing

Table 30. Parallel Peripheral Interface Timing guaranteed to be received correctly by the PPI peripheral. Figure 14. PPI with External Frame Sync Timing Figure 15. PPI GP Rx Mode with External Frame Sync Timing

and Figure 20 describe RSI controller (high speed) timing. Table 31. RSI Controller Timing

1 Clock Frequency Data Transfer Mode 0 25 MHz

2 Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required. Figure 19. RSI Controller Timing 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

Table 32. RSI Controller Timing (High Speed Mode)

1 Clock Frequency Data Transfer Mode 0 50 MHz

Figure 20. RSI Controller Timing (High Speed Mode) 1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS. 2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

through Figure 24 on Page 40 describe serial port operations. Table 33. Serial Ports—External Clock

1 TFSx/RFSx Setup Before TSCLKx/RSCLKx 3 3 ns

1 TFSx/RFSx Hold After TSCLKx/RSCLKx 3 3 ns

1 Receive Data Setup Before RSCLKx 3 3 ns

2 Start-Up Delay From SPORT Enable To First External TFSx 4 × t SCLKE 4 × tSCLKE ns

2 Start-Up Delay From SPORT Enable To First External RFSx 4 × t SCLKE 4 × tSCLKE ns

3 TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated

3 TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated

3 Transmit Data Delay After TSCLKx 10 10 ns

3 Transmit Data Hold After TSCLKx 0 0 ns

1 Referenced to sample edge. 2 Verified in design but untested. Table 34. Serial Ports—Internal Clock

2 TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated

2 TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated

2 Transmit Data Delay After TSCLKx 3 3 ns

1 Referenced to sample edge.

Table 35. Serial Ports—Enable and Three-State 1 Figure 23. Enable and Three-State

Table 36. External Late Frame Sync 1 MCE = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFSE. 2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2 then tDDTTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply. Figure 24. External Late Frame Sync

Table 37 and Figure 25 describe SPI port master operations. Table 37. Serial Peripheral Interface (SPI) Port—Master Timing Figure 25. Serial Peripheral Interface (SPI) Port—Master Timing

Table 38 and Figure 26 describe SPI port slave operations. in the ADSP-BF51x Hardware Reference Manual. Table 38. Serial Peripheral Interface (SPI) Port—Slave Timing Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing

Table 41. Timer Cycle Timing

1 Timer Pulse Width Input Low (Measured In SCLK Cycles) t SCLK tSCLK ns

1 Timer Pulse Width Input High (Measured In SCLK Cycles) t SCLK tSCLK ns

2 Timer Input Setup Time Before CLKOUT Low 10 7 ns

2 Timer Input Hold Time After CLKOUT Low –2 –2 ns

1 The minimum pulse widths apply for TMRx sign als in width capture and external clock mode s. They also apply to the PF15 or PPI_CLK signals in PWM output mode. 2 Either a valid setup and hold time or a valid pulse width is suff icient. There is no need to resynchronize programmable flag inputs. Figure 29. Timer Cycle Timing

Table 46. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal 1 RMII outputs synchronous to RMII REF_CLK are ETxD1–0. Figure 34. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Table 49 and Figure 37 describe JTAG port operations. Table 49. JTAG Port Timing

1 System Inputs Setup Before TCK High 4 ns

1 System Inputs Hold After TCK High 5 ns

3 System Outputs Delay After TCK Low 0 13 ns

1 System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TD1, TMS, RESET , NMI, BMODE2–0. DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO. Figure 37. JTAG Port Timing

circuit board design considerations. measurement complies with MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board. Table 50. Thermal Characteristics for SQ-176-2 Package Table 51. Thermal Characteri stics for BC-168-1 Package

Table 52 lists the LQFP leads by lead number. Table 53 on Page 58 lists the LQFP by signal mnemonic. Table 52. 176-Lead LQFP Pin Assignme nt (Numerical by Lead Number)

1 GND 45 GND 89 GND 133 GND

2 GND 46 GND 90 GND 134 GND

3 PF9 47 PG1 91 A12 135 PG

4 PF8 48 PG0 92 A11 136 V DDEXT

10 PF5 54 TRST 98 V DDINT 142 V DDRTC

11 PF4 55 TMS 99 GND 143 CLKIN

12 PF3 56 D15 100 V

13 PF2 57 D14 101 A6 145 V DDEXT

14 V DDINT 58 D13 102 A5 146 RESET

15 GND 59 V DDMEM 103 A4 147 NMI

16 V DDFLASH 60 D12 104 V DDMEM 148 V DDEXT

17 V DDFLASH 61 D11 105 A3 149 GND

18 PF1 62 D10 106 A2 150 CLKBUF

19 PF0 63 V

20 PG15 64 D9 108 ABE 11 5 2 V DDINT

21 PG14 65 D8 109 ABE 01 5 3 P H 7

22 GND 66 D7 110 SA10 154 PH6

24 V DDEXT 68 V DDMEM 112 V DDMEM 156 PH4

25 PG13 69 D6 113 SWE 157 GND

26 PG12 70 D5 114 SCAS 158 V DDEXT

27 PG11 71 D4 115 SRAS 159 PH3

28 PG10 72 D3 116 V DDINT 160 PH2

29 V DDFLASH 73 D2 117 GND 161 PH1

30 V DDINT 74 D1 118 SMS 162 PH0

31 PG9 75 V DDMEM 119 SCKE 163 GND

32 PG8 76 D0 120 AMS 11 6 4 V DDINT

33 PG7 77 A19 121 ARE 165 PF15

34 PG6 78 A18 122 AWE 166 PF14

35 V DDEXT 79 V DDINT 123 AMS 01 6 7 P F 1 3

36 PG5 80 A17 124 V DDMEM 168 PF12

37 PG4 81 A16 125 CLKOUT 169 GND

38 PG3 82 V

39 PG2 83 GND 127 NC 1 171 PF11

40 BMODE2 84 A15 128 V DDEXT 172 SDA

41 BMODE1 85 A14 129 V DDEXT 173 SCL

42 BMODE0 86 A13 130 EXT_WAKE 174 PF10

43 GND 87 GND 131 GND 175 GND

44 GND 88 GND 132 GND 176 GND

• Pin no. 177 is the GND supply (see Figure 69) for the processor; this pad must connect to GND.

1 This pin must not be connected.

Table 53. 176-Lead LQFP Pin Assignment (Alphabetical by Signal Mnemonic)

107 A1 58 D13 5 PF7 113 SWE

106 A2 57 D14 4 PF8 53 TCK

105 A3 56 D15 3 PF9 52 TDI

103 A4 51 EMU

174 PF10 50 TDO

102 A5 130 EXT_WAKE 171 PF11 55 TMS

101 A6 1 GND 168 PF12 54 TRST

97 A7 2 GND 167 PF13 7 V DDEXT

96 A8 15 GND 166 PF14 24 V DDEXT

94 A9 22 GND 165 PF15 35 V DDEXT

93 A10 43 GND 135 PG 49 V DDEXT

92 A11 44 GND 48 PG0 128 V DDEXT

91 A12 45 GND 47 PG1 129 V DDEXT

86 A13 46 GND 39 PG2 136 V DDEXT

85 A14 67 GND 38 PG3 145 V DDEXT

84 A15 83 GND 37 PG4 148 V DDEXT

81 A16 87 GND 36 PG5 158 V DDEXT

80 A17 88 GND 34 PG6 170 V DDEXT

78 A18 89 GND 33 PG7 16 V DDFLASH

77 A19 90 GND 32 PG8 17 V DDFLASH

109 ABE 0 9 9G N D 3 1P G 9 2 9V DDFLASH

108 ABE 1 111 GND 28 PG10 126 V DDFLASH

123 AMS 0 1 3 1 G N D 2 7P G 1 1 1 4V DDINT

120 AMS 1 1 3 2 G N D 2 6P G 1 2 2 3V DDINT

121 ARE 133 GND 25 PG13 30 V DDINT

122 AWE 134 GND 21 PG14 63 V DDINT

42 BMODE0 137 GND 20 PG15 79 V DDINT

41 BMODE1 139 GND 162 PH0 98 V DDINT

40 BMODE2 149 GND 161 PH1 100 V DDINT

150 CLKBUF 151 GND 160 PH2 116 V DDINT

143 CLKIN 157 GND 159 PH3 138 V DDINT

125 CLKOUT 163 GND 156 PH4 152 V DDINT

76 D0 169 GND 155 PH5 164 V DDINT

74 D1 175 GND 154 PH6 59 V DDMEM

73 D2 176 GND 153 PH7 68 V DDMEM

72 D3 117 GND 146 RESET 75 V DDMEM

71 D4 127 NC 1 141 RTXI 82 V DDMEM

70 D5 147 NMI 140 RTXO 95 V DDMEM

69 D6 19 PF0 110 SA10 104 V DDMEM

66 D7 18 PF1 114 SCAS 112 V DDMEM

65 D8 13 PF2 119 SCKE 124 V DDMEM

64 D9 12 PF3 173 SCL 9 V DDOTP

62 D10 11 PF4 172 SDA 142 V DDRTC

61 D11 10 PF5 118 SMS 8V PPOTP

60 D12 6 PF6 115 SRAS 144 XTAL

• Pin no. 177 is the GND supply (see Figure 69) for the processor; this pad must connect to GND.

1 This pin must not be connected.

Page 61 lists the CSP_BGA balls by signal mnemonic. Table 54. 168-Ball CSP_BGA Ball Assign ment (Numerical by Ball Number) 1 This pin must not be connected.

Table 55. 168-Ball CSP_BGA Ball Assignment (Alphabetical by Signal Mnemonic) 1 This pin must not be connected.

Dimensions in Figure 72 are shown in millimeters. Figure 72. 176-Lead Low Profile Quad Flat Package [LQFP_EP]

0.08 MAX

1.00 REF

5.80 REF

Figure 73. 168-Ball Chip Scale Package Ball Grid Array [CSP_BGA] COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

0.34 NOM

0.29 MIN

Table 56. BGA Data for Use with Surface-Mount Design

Table 57. Automotive Products 2 The use of xx designates silicon revision. specification which is the only temperature specification.

Rev. B | Page 66 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F ADSP-BF514KSWZ-4 0ºC to +70ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2 ADSP-BF514KSWZ-4F4 0ºC to +70ºC 400 MHz 4M bit 176-Lead LQFP_EP SQ-176-2 ADSP-BF516KSWZ-3 0ºC to +70ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2 ADSP-BF516KBCZ-3 0ºC to +70ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1 ADSP-BF516KSWZ-4 0ºC to +70ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2 ADSP-BF516KBCZ-4 0ºC to +70ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1 ADSP-BF516KSWZ-4F4 0ºC to +70ºC 400 MHz 4M bit 176-Lead LQFP_EP SQ-176-2 ADSP-BF516KBCZ-4F4 0ºC to +70ºC 400 MHz 4M bit 168-Ball CSP_BGA BC-168-1 ADSP-BF516BBCZ-3 –40ºC to +85ºC 300 MHz N/A 168-Ball CSP_BGA BC-168-1 ADSP-BF516BBCZ-4 –40ºC to +85ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1 ADSP-BF516BBCZ-4F4 –40ºC to +85ºC 400 MHz 4M bit 168-Ball CSP_BGA BC-168-1 ADSP-BF516BSWZ-3 –40ºC to +85ºC 300 MHz N/A 176-Lead LQFP_EP SQ-176-2 ADSP-BF516BSWZ-4 –40ºC to +85ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2 ADSP-BF516BSWZ-4F4 –40ºC to +85ºC 400 MHz 4M bit 176-Lead LQFP_EP SQ-176-2 ADSP-BF518BBCZ-4 –40ºC to +85ºC 400 MHz N/A 168-Ball CSP_BGA BC-168-1 ADSP-BF518BBCZ-4F4 –40ºC to +85ºC 400 MHz 4M bit 168-Ball CSP_BGA BC-168-1 ADSP-BF518BSWZ-4 –40ºC to +85ºC 400 MHz N/A 176-Lead LQFP_EP SQ-176-2 ADSP-BF518BSWZ-4F4 –40ºC to +85ºC 400 MHz 4M bit 176-Lead LQFP_EP SQ-176-2 1 Z = RoHS compliant part. 2 Referenced temperature is ambient temperature. The ambie nt temperature is not a specification. Please see Operating Conditions on Page 20 for junction temperature (TJ) specification which is the only temperature specification. Model1 Temperature Range2 Processor Instruction Rate (Max) Flash Memory Package Description Package Option

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Rev. B | Page 67 of 68 | January 2011

Rev. B | Page 68 of 68 | January 2011 ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08574-0-1/11(B)