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BD9G101G

Rohm

Simple Step-down Switching Regulators with Built-in Power MOSFET

Manufacturer: Rohm

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BD9G101G ROHM | Alldatasheet

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General Description The BD9G101G is switching regulator with integrated internal high-side 42V Power MOSFET. It provides 0.5A DC output with small SOT23 package. Operating frequency is fixed 1.5MHz, allowing the use of small inductor and ceramic capacitor. Phase compensation components is built in. The BD9G101G is available in SOT-23-6(SSOP6) package.
Features ■ High and Wide Input Range (VCC=6V~42V) ■ 45V/800mΩ Internal Power MOSFET ■ 1.5MHz Fixed Operating Frequency ■ Feedback Pin Voltage 0.75V±1.5% ■ Internal compensated ■ Internal Over Current protection, Under Voltage Locked Out, Thermal shutdown ■ 0µA Shutdown Supply Current ■ 6-Lead SOT-23 package(SSOP6)
Key Specifications ■ Input Voltage ■ Ref. Precision (Ta=25 ℃) (Ta=-25~105℃) ■ Max Output Current ■ Operating Temperature ■ Max Junction Temperature 6～42 [V] ±1.5[%] ±2.0[%] 0.5 [A] (Max.) -40℃~105℃ 150℃
Packages
Applications ■ Industrial distributed power applications ■ Automotive Applications ■ Battery powered equipment ■ OA instruments
Typical Application Circuits ○Structure：Silicon Monolithic Integrated Circuit ○ This product is not designed for normal operation with in a radioactive.

Figure 1. Typical Application Circuit

Description of Blocks 1. Reference This block generates reference voltage and current. It start operation by applying EN more than 2.0V. It provides reference voltage and current to error-amp , oscillator ,and etc. 2. REG This is a gate drive voltage generator and 4.2V regulator for internal circuit power supply. 3. OSC This is a precise wave oscillation circuit with operation frequency fixed to 1.5MHz fixed. To protect from output shorted to GND, Frequency fold-back function is built in. 4. Soft Start This block does Soft Start to the output voltage of DC/DC comparator, and prevents in-rush current during Start-up. Soft Start Time depend on application and start-condition because Frequency fold-back function is built in. 5. ERROR AMP This is an error amplifier what detects output signal, and outputs PWM control signal. Internal reference voltage is set to 0.75V. Also, the BD9G101G has internal phase compensated element between input and output. 6. ICOMP This is a comparator that outputs PWM signal from current feed-back signal and error-amp output for current-mode. 7. Nch FET SW This is an 45V/800mΩ Power Nch MOSFET SW that converts inductor current of DC/DC converter. 8. UVLO This is a low voltage error prevention circuit. This prevents internal circuit error during increase of power supply voltage and during decline of power supply voltage. It monitors VCC pin voltage and internal REG voltage, And when VCC voltage becomes 5.4V and below, it turns OFF all output FET and turns OFF DC/DC comparator output, and Soft Start circuit resets. Now this Threshold has hysteresis of 200mV. 9. EN When a Voltage of 2.0V or more is applied, it turns ON, at Open or 0V application, it turns OFF. About 550kΩ Pull-down Resistance is contained within the Pin. 1 0 . O C P The current of power MOSFET is limited by this function. The power MOSFET current is sensed by current sense FET. If the current of power MOSFET is over 1.2A(typ), this function reduce duty by pulse –by- pulse and restrict the and restraint on over current. 11.TSD Circuit for preventing malfunction at high Temperature . When it detects an abnormal temperature exceeding Tj=175℃, it turns OFF DC/DC Comparator Output. The threshold of TSD has Hysteresis(25℃). If Temperature falls 150℃,the IC automatically returns.

Absolute Maximum Ratings Item Symbol Ratings Unit VCC VCC 45 V Maximum input current Imax 1.0 A BST to GND VBST 50 V BST to Lx ⊿VBST 7 V EN VEN 45 V Lx VLx 45 V FB VFB 7 V Power Dissipation Pd 0.675 (*1) W Operating Temperature Topr -40 ～+105(*2) ℃ Storage Temperature Tstg -55 ～+150 ℃ Junction Temperature Tjmax 150 ℃ (*1)During mounting of 70×70×1.6t mm 1layer board.Reduce by 5.4mW for every 1℃ increase. (Above 25℃) (*2)Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regula tor will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent d amage. thermal shutdown engages at Tj=175 ℃(typ) and disengages at Tj=155℃ (typ)
Electrical Characteristics (Unless otherwise specified Ta=25℃, VCC=24V, Vo=5V,EN=3V ) Parameter Symbol Limit Unit Condition Min Typ Max 【Circuit Current】 Stand-by Current Ist － 0 5 µA VEN=0V Operating Current Icc － 0.7 1.2 mA FB=1.2V 【Under Voltage Lock Out (UVLO)】 Threshold Voltage Vuv 5.1 5.4 5.7 V Hysteresis width Vuvhy － 200 300 mV 【Oscillator】 Switching Frequency fosc 1.3 1.5 1.7 MHz Max Duty Cycle Dmax 85 - - % 【Error AMP】 FB Pin Reference Voltage VFBN 0.739 0.750 0.761 V Ta=25 ℃ VFBA 0.735 0.750 0.765 V Ta=-25~105 ℃ FB Pin Bias Current IFB -100 0 100 nA VFB=2.0V Soft-Start Time Tsoft 1.2 4.0 - ms 【Current Comparator】 Trans-conductance G CS - 3 - A/V 【Output】 Nch MOSFET ON Resistance RonH － 800 － m Ω Min ON Time Tmin － 100 － nsec Switch Current Limit Iocp 0.85 1.2 － A 【CTL】 EN Thresohold Voltage ON VENON 2.0 － VCC V OFF VENOFF -0.3 － 0.8 V EN Input Bias Current REN 2.7 5.5 11 µA VEN=3V ◎Not designed to withstand radiation.

Operating Ratings Item Symbol Ratings Unit Min Typ Max Input Voltage VCC 6 - 42 V Output Voltage VOUT 1.0 (*2) - VCC ×0.7(*3) V Output Current IOUT - - 500 mA (*2)Restricted by minimum on pulse typ. 100nsec (*3)Restricted by maxduty ,Ron and BST-UVLO.
input and output voltage restriction The input voltage range of BD9G101G is limited by Ron, Maxduty(min85%) and preventing malfunction at low voltage between BST and LX(BST-UVLO). ①BST-UVLO BSTUVLO is the function that prevent the IC from abnormal operation that is caused by shortage of charge of High-SideFET driving. If the voltage between BST and Lx is lower than 1.5V, High-Side FET is turned off and there are new pass to charge voltage VCC to BST. BST voltage is charged by Vcc and goes over BST-UVLO threshold. As a result , BST-UVLO is turned off. The condition that BST-UVLO is working property is VCC>>(BST-UVLO threshold + Vf )+ Vout. Therefore maximum output voltage is lower than Vin -3V. ※If output voltage is higher than Vin-3V, output voltage ripple is boosted by the trigger of BSTUVLO. This is no problem in IC operation. ②Max duty , Ron Maximum output voltage is limited by maxduty(min85%) and FET Ron. In the case of Io=500mA, VCC drop down 500mA ×0.8Ω=0.6V besides maxduty. Vomax = (Vcc-Ron×Iomax)×0.85 (casually formula) Considering the negative voltage in the case of pulling diode current, Formula of maximum output voltage is Vomax = VCC×0.7. ③minimum on pulse Minimum output voltage is limited by minimum on pulse (typ 100nsec). Output voltage = frequency(typ 1.5MHz) × FET on time ×Vin If output voltage is lower than this formula , Output ripple voltage is boosted by intermittent spring. BST charging current (normal mode)

Figure 4. BST-UVLO image

Frequency fold-back function This IC has the frequency fold-back function to prevent from over current with the circuit output is shorted. The frequency fold-back has the function that the frequency is changed by FB voltage. Figure.5 shows FB voltage vs frequency Characteristics. When the output node is shorted, the IC narrows the frequency to 150kHz(typ) so that input current limiting. This IC operates on1.5MHz in case of normal mode, the voltage of FB is about 0.75V.
Start-up Characteristics When the IC is starting up, frequency reacts to the voltage of FB on the function of frequency fold back. For the Softstart is operated by internal frequency clock, according to rising to the output voltage, the Softstart rising speed is more faster. Please check the using condition and the application waveform (P.10,P13) because of the Start-up characteristics changes to the output load and the output capacitor.

Figure 5. FB voltage -frequency Characteristics

Cautions on PC Board layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VCC pin should be bypassed to ground with a low ESR ceramic bypass capacitor with B dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VCC pin, and the anode of the catch diode. See Figure.45 for a PCB layout example. In the BD9G101G, since the LX connection is the switching node, the catch diode and output inductor should be located close to the LX pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. And GND area should not be connected directly power GND, connected avoiding the high current switch paths. The additional external components can be placed approximately as shown.

Figure 45. Reference PCB layout

Power Dissipation It is shown below reducing characteristics of power dissipation to mount 70mm×70mm×1.6mmt, 1layer PCB. Junction temperature must be designed not to exceed 150℃
Power Dissipation Estimate The following formulas show how to estimate the device powe r dissipation under continuous mode operations. They should not be used if the device is working in the discontinuous conduction mode. The device power dissipation includes: 1) Conduction loss： Pcon = IOUT 2 × RonH × VOUT/VCC 2) Switching loss: Psw = 0.41 × 10–9 × VCC2 × IOUT × fsw 3) Gate charge loss： Pgc = 4.88 × 10 –9 × fsw 4) Quiescent current loss： Pq = 0.8× 10 –3 × VCC Where: IOUT is the output current (A）, RonH is the on-resistance of the high-side MOSFET（Ω）, VOUT is the output voltage (V). VCC is the input voltage (V), fsw is the switching frequency (Hz). Therefore Power dissipation of IC is the sum of above dissipation. Pd = Pcon + Psw + Pgc + Pq For given Tj, Tj =Ta + θja × Pd Where: Pd is the total device power dissipation (W), Ta is the ambient temperature (℃) Tj is the junction temperature (℃), θja is the thermal resistance of the package (℃)

Figure 46. Power Dissipation ( 70mm×70mm×1.6mmt 1layer PCB)

I/O equivalent circuit Pin. No Pin Name Pin Equivalent Circuit Pin. No Pin Name Pin Equivalent Circuit Lx GND BST VCC 4 EN s 3 FB BST VC Lx GND FB GND

Figure 47. I/O equivalent circuit

Notes for use (1) About Absolute Maximum Rating When the absolute maximum ratings of app lication voltage, operating temperature range, etc. was exceeded, there is possibility of deterioration or destruction. Also, the shor t Mode or open mode, etc. de struction condition cannot be assumed. When the special mode where absolute maximum ra ting is exceeded is assumed, please give consideration to the physical safety countermeasure for the fuse, etc. (2) About GND Electric Potential In every state, please make the electric potential of GND Pin into the minimum electrical potential. Also, include the actual excessive effect, and please do it such that the pins, excluding the GND Pin do not become the voltage below GND. (3) About Heat Design Consider the Power Dissipation (Pd) in actual state of use, and please make Heat Design with sufficient margin. (4) About short circuit between pins and erroneous mounting When installing to set board, please be mindf ul of the direction of the IC, phase diff erence, etc. If it is not installed correctly, there is a chance that the IC will be destroyed. Also, if a foreign object enters the middle of output, the middle of output and power supply GND, etc., even for the case where it is shorted, there is a change of destruction. (5) About the operation inside a strong electro-magnetic field When using inside a strong electro-magnetic field, there is a possibility of error, so please be careful. (6) About checking with Set boards When doing examination with the set board, during connection of capacitor to the pin that has low impedance, there is a possibility of stress in the IC, so for every 1 process, pl ease make sure to do electric discharge. As a countermeasure for static electricity, in the process of assembly, do grounding, and when transporting or storing please be careful. Also, when doing connection to the jig in the examination process, please make sure to turn off the power supply, then connect. After that, turn off the power supply then take it off. (7) About common impedance For the power supply and the wire of GND, lower the comm on impedance, then, as much as possible, make the ripple smaller (as much as possible make the wire thick and short, and lower the ripple from L ・C), etc., then and please consider it sufficiently. (8) In the application, when the mode wher e the VCC and each pin electrical potentia l becomes reversed exists, there is a possibility that the internal circuit will become damaged. Fo r example, during cases wherein the condition when charge was given in the external capacitor, and the VCC was short ed to GND, it is recommended to insert the bypass diode to the diode of the back current prevention in the VCC series or the middle of each Pin-VCC. (9) About IC Pin Input This IC is a Monolithic IC, and between each element, it has P+ isolation for element separation and P board. With the N layer of each element and this, the P-N junction is formed, and the parasitic element of each type is composed. For example, like the diagram below, when resistor and transistor is connected to Pin, ○When GND＞(PinA) in Resistor, when GND ＞(PinA), when GND＞(PinB) in Transistor (NPN), the P-N junction will operate as a parasitic diode. ○Also, during GND＞(Pin B) in the Transistor (NPN), through the N layer of the other elements connected to the above-mentioned parasitic diode , the parasitic NPN Transistor will operation. On the composition of IC, depending on the electrical potential, the parasitic element will become necessary. Through the operation of the parasitic element interference of circuit operation will arouse, and error, therefore destruction can be caused. Therefore please be careful about the applying of voltage lower than the GND (P board) in I/O Pin, and the way of using when parasitic element operating. Status of this document The English version of this document is fo rmal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority ～～ (Pin A) GND P Substrate N P N P＋ P＋ (Pin A) Parasitic Element Resistor Parasitic Element Transistor (NPN) ～～ GND P Substrate N P Ｎ N P＋P＋ (Pin B) B N EC GND N

Figure 48. Example of simple structure of Bipolar IC

Ordering part number B D 9 G 1 0 1 G - TR Part Number package G: SSOP6 Packaging and forming specification TR: Embossed tape and reel
External information １pin mark LOT No SSOP6 Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tapeTape Quantity Direction of feed The direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs TR 1pin

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Product Information

BD9G101G specifications and overview.

Summary

Simple Step-down Switching Regulators with Built-in Power MOSFET

Description

Simple Step-down Switching Regulators with Built-in Power MOSFET

Source title BD9G101G Datasheet(PDF) - Rohm

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