Power Management

BD9540EFV

Rohm

2ch Switching Regulators for Desktop PC

Manufacturer: Rohm

Document: 18 Pages / 502Kb

Request Quote Download Datasheet Read online HTML view

Read BD9540EFV online.

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 18

Technical content

Description BD9540EFV is a 2ch switching regulator synchronous controller that can generate low output voltages (0.75V to 5.5V). High efficiency for the switching regulator can be achieved due to its external N-MOSFET power transistor. The IC also incorporates a new technology called H 3RegTM, a Rohm proprietary control method which facilitates ultra-high transient response against changes in load. For protection and ease of us e, the IC also incorporates soft start, and short circuit protection with timer latch functions. This switching regulator is designed for DRAM and power supplies for graphics chips.
Features 1) 2ch H 3RegTM DC/DC converter synchronous controller 2) Thermal Shut Down (TSD), Under-Voltage Lock-Out (UVLO), Adjustable Over Current Protection (OCP) : detec ted Low side FET Ron, Over Voltage Protection (OVP), Short Circuit Protection (SCP) built-in 3) Soft start function to minimize rush current during startup 4) HTSSOP-B28 package 5) Built-in 5V power supply for FET driver 6) Integrated bootstrap diode
Applications LCD-TV, Game Consoles, Desktop PCs
Maximum Absolute Ratings (Ta=25℃) Parameter Symbol Limit Unit Input Voltage VIN 24 *1 V BOOT Voltage BOOT1,BOOT2 30 *1 V BOOT-SW Voltage BOOT 1-SW1, BOOT2-SW2 7 *1 V HG-SW Voltage HG1-SW1, HG2-SW2 7 *1 V LG Voltage LG1, LG2 5VReg V Output Voltage VOUT1, VOUT2 7 *1 V Output Feedback Voltage FB1, FB2 5VReg V 5VReg Voltage 5VReg 7 *1 V Current Limit Setting Voltage ILIM1, ILIM2 5VReg V Logic Input Voltage 1 EN1, EN2 24 *1 V Logic Input Voltage 2 CTL1, CTL2 7 *1 V Power dissipation 1 Pd1 1.45 *2 W Power dissipation 2 Pd2 1.85 *3 W Power dissipation 3 Pd3 3.30 *4 W Power dissipation 4 Pd4 4.70 *5 W Operating Temperature Range Topr -20 ～+100 ℃ Storage Temperature Range Tstg -55 ～+150 ℃ Junction Temperature Tjmax +150 ℃ *1 Not to exceed Pd. *2 Reduced by 11.6mW for each increase in Ta of 1℃ over 25 ℃ (when mounted on a board 70.0mm ×70mm×1.6mm Glass-epoxy PCB, 1layer, no copper foil area.) *3 Reduced by 14.8mW for increase in Ta of 1℃ over 25 ℃. (when mounted on a board 70.0mm ×70mm×1.6mm Glass-epoxy PCB, 2layers, copper foil area : 15mm×15mm.) *4 Reduced by 26.4mW for increase in Ta of 1℃ over 25 ℃. (when mounted on a board 70.0mm ×70mm×1.6mm Glass-epoxy PCB, 2layers, copper foil area : 70mm×70mm.) *5 Reduced by 37.6mW for increase in Ta of 1℃ over 25 ℃. (when mounted on a board 70.0mm ×70mm×1.6mm Glass-epoxy PCB, 4layers, copper foil area : 70mm×70mm.) No.09030EBT07

Operating Conditions (Ta=25℃) Parameter Symbol Min. Max. Unit Input voltage VIN 7.5 20 V BOOT voltage BOOT1, BOOT2 4.5 25 V SW Voltage SW1, SW2 -0.7 20 V BOOT-SW voltage BOOT1-SW 1, BOOT2-SW2 4.5 5.5 V Logic Input Voltage 1 EN1, EN2 0 20 V Logic Input Voltage 2 CTL1, CTL2 0 5.5 V Output Voltage VOUT1, VOUT2 0.7 5.5 V MIN ON Time tonmin - 100 ns *This product should not be used in a radioactive environment. *The range of the VOUT is limited by the voltage between VIN and VOUT.
Electrical characteristics (Unless otherwise noted, Ta=25℃ VCC=5V, VIN=12V, VEN1=VEN2=3V, Vout1=1.5V, Vout2=1.05V) Parameter Symbol Limit Unit Condition Min. Typ. Max. [General] VIN Bias Current IIN - 1.6 2.5 mA VIN Standby Current IIN_stb - 0 10 μA VEN1=VEN2=0V EN Low Voltage 1,2 VEN_low1,2 GND - 0.3 V EN High Voltage 1,2 VEN_high1,2 2.2 - 20 V EN Bias Current 1,2 IEN1,2 - 1.5 5.0 μA VEN1=VEN2=3V [5V Linear Regulator] 5VReg Standby Voltage 5Vreg_stb - - 0.1 V VEN1=VEN2=0V 5VReg Output Voltage 5VReg 4.8 5.0 5.2 V VIN=7.5V to 20V Ireg=0mA to 10mA Maximum Current IReg 50 - - mA [Under-Voltage Lock-Out] 5VReg Threshold Voltage 5Vreg_UVLO 3.75 4.20 4.65 V 5VReg:Sweep up 5VReg Hysteresis Voltage d5Vreg_UVLO 100 160 220 mV 5VReg:Sweep down [OVP Block] FB Threshold Voltage 1 FB_OVP1 0.92 1.02 1.12 V FB Threshold Voltage 2 FB_OVP2 0.80 0.90 1.00 V OVP delay time tOVP - 1.7 - μs [H3RegTM Control Block] ON Time1 ton1 290 390 490 ns MIN OFF Time 1 toffmin1 200 380 - ns ON Time 2 ton2 110 210 310 ns MIN OFF Time 2 toffmin2 200 380 - ns [FET Block] HG High side ON Resistance 1,2 RHGhon1,2 - 5.5 11 Ω HG Low side ON Resistance 1,2 RHGlon1,2 - 2.5 5 Ω LG High side ON Resistance 1,2 RLGhon1,2 - 4 8 Ω LG Low side ON Resistance 1,2 RLGlon1,2 - 2 4 Ω [Over Current Protection Block] Current Limit Threshold Voltage 1,2 Vilim1,2 80 100 120 mV RILIM=100k Ω [Output Voltage Detection Block] FB1 threshold(REF1) Voltage1 FB1-1 0.769 0.781 0.793 V CTL1=0V, CTL2=0V FB1 threshold(REF1) Voltage2 FB1-2 0.802 0.814 0.826 V CTL1=5V, CTL2=0V FB1 threshold(REF1) Voltage3 FB1-3 0.839 0.851 0.863 V CTL1=0V, CTL2=5V FB1 threshold(REF1) Voltage4 FB1-4 0.738 0.750 0.762 V CTL1=5V, CTL2=5V FB2 threshold(REF2) Voltage FB2 0.738 0.750 0.762 V CTL Low Voltage 1,2 VCTL_low1,2 GND - 0.5 V CTL High Voltage 1,2 VCTL_high1,2 VCC-0.5 - VCC V FB1/2 Input Current IFB1,2 -1 - 1 μA VOUT Discharge Current IVOUT1,2 5 10 - mA VOUT=1V, EN=0V [SCP Block] Threshold Voltage 1,2 Vthscp1,2 REF1,2× 0.60 REF1,2× 0.70 REF1,2× 0.80 V SCP delay time tSVP - 28 - μs

Block Diagram
Pin Configuration Thermal Protection R S Q TSD Delay H3RegTM Controller Block 5VReg GND BOOT1 HG1 SW1 LG1 PGND1 Reference Block UVLO EN2 BOOT2 HG2 SW2 LG2 5VReg 2223 OVP OVP Driver Circuit R S QH3RegTM Controller Block UVLO ILIM2 SCP TSD Driver Circuit FB1 EN1 3 FB2 1.02 FB1 OVP1 0.90 FB2 5VReg 5VReg VOUT2 EN1/UVLO TSD/OVP VOUT1 4 VOUT1 Logic Input VOUT2 VOUT1 VIN VOUT2 VIN VIN VIN EN1 5VReg UVLO ILIM1 SCP TSD REF2×0.7 FB2 REF1×0.7 FB1 SCP EN2 5VReg CTL1 8 CTL2 9 REF1 SW1 OCP SW2 OCP DAC ILIM1 ILIM2 OVP OVP2 5VReg VCC VIN PGND2 Soft Start + REF1 SS1 REF2 BG EN1 SS1 Soft Start EN2 SS2 EN2/UVLO TSD/OVP + - + REF2 SS2 TEST BD9540EFV BOOT1 1 14 15 VOUT2 EN2 BOOT2 HG1 SW1 LG1 PGND1 ILIM1 V IN 5VReg ILIM2 PGND2 LG2 SW2 HG2 EN1 VOUT1 FB1 NC GND FB2 NC CTL2 2 NC TEST 8 21 VCC CTL1

Pin Function PIN No. PIN name PIN Function

1 BOOT1 HG Driver Power Supply Pin 1

2 NC Non connection Pin

3 EN1 Enable Input Pin 1 (0 ～0.3V:OFF, 2.2～20V:ON)

4 VOUT1 Output Voltage Sence Pin 1

5 FB1 Output Voltage Feedback Pin 1

6 NC Non connection Pin

7 GND Sense GND

8 CTL1 1ch Reference Voltage Setting Control Pin 1:See P12/17

9 CTL2 1ch Reference Voltage Setting Control Pin 2:See P12/17

10 FB2 Output Voltage Feedback Pin 2

11 VOUT2 Output Voltage Sense Pin 2

12 EN2 Enable Input Pin 2 (0 ～0.3V:OFF, 2.2～20V:ON)

13 NC Non connection Pin

14 BOOT2 HG Driver Power Supply Pin 2

15 HG2 High side FET Gate Driver Pin 2

16 SW2 High side FET Source Pin 2

17 LG2 Low side FET Gate Driver Pin 2

18 PGND2 Power GND for 2ch

19 ILIM2 2ch OCP Setting Pin

20 TEST Connect to GND Pin

21 VCC Power Supply Input Pin

22 5VReg Reference Voltage Inside IC (5V Voltage Output)

23 VIN Battery Voltage Sense Pin

24 ILIM1 1ch OCP Setting Pin

25 PGND1 Power GND for 1ch

26 LG1 Low side FET Gate Driver Pin 1

27 SW1 High side FET Source Pin 1

28 HG1 High side FET Gate Driver Pin 1

reverse FIN Exposed Pad, Connect to GND

Reference Data 0.5 1.5 2.5 -20 0 20 40 60 80 100 Ta [℃] IIN [mA] 100 0.01 0.1 1 10 IOUT [A] Efficiency [%] 100 110 120 130 -20 0 20 40 60 80 100 Ta [℃] VILIM [mV] Fig.1 Transient Respnse (VIN=12V VOUT2=1.05V) Fig.5 VOUT wake up (Io=0A) Fig.6 VOUT wake up (Io=4A) Fig.2 Transient Respnse (VIN=12V VOUT2=1.05V) (2μs/div) VOUT2 50[mV/div] SW1 10[V/div] (2μs/div) (2μs/div) Fig.7 OCP and SCP Fig.8 Ta-VILIM Fig.9 IOUT-Efficiency Fig.3 Transient Respnse (VIN=12V VOUT1=3.3V) Fig.4 Transient Respnse (VIN=12V VOUT1=3.3V) (2μs/div) RILIM=100kΩ SW2 10[V/div] IOUT2 2[A/div] VOUT2 50[mV/div] SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div] VOUT1 50[mV/div] SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div] VOUT1 50[mV/div] SW1 10[V/div] SW2 10[V/div] IOUT2 2[A/div] EN 50[V/div] VOUT 0.5[V/div] SW 10[V/div] IL 2[A/div] EN 50[V/div] VOUT 0.5[V/div] SW 10[V/div] IL 2[A/div] 1msec(typ) 1msec(typ) HG, LG 20[V/div] VOUT 1[V/div] IL 5[A/div] VIN=12V VMOSFET:MP6K61 Vo=1.8V Vo=1.2V 28μsec(typ) Fig.10 Ta-IIN Fig.11 Ta-IIN_STB Fig.12 V IN-IIN -20 0 20 40 60 80 100 Ta [℃] IIN_STB [μA] 0.5 1.5 2.5 0 5 10 15 20 VIN [V] IIN [mA] VIN=12V VCC=VREG5V EN1=EN2=3V VIN=12V VCC=VREG5V EN1=EN2=0V VCC=VREG5V EN1=EN2=3V

Reference Data Fig.13 V IN-IIN_STB Fig.15 VIN-5VREG Fig.14 Ta-5VREG Fig.16 VEN‐IEN 4.8 4.9 5.1 5.2 -20 0 20 40 60 80 100 Ta [℃] 5VREG [V] 048 1 2 1 6 2 0 VEN [V] IEN [μA] VCC=VREG5V EN1=EN2=0V 048 1 2 1 6 2 0 VIN [V] IIN_STB [μA] 048 1 2 1 6 2 0 VIN [V] 5VREG [V] Fig.17 VIN-VOUT1 Fig.18 VIN-VOUT2

Pin Descriptions ・EN1 (3 pin) / EN2 (12 pin) When the input voltage on the EN pin reaches at least 2.2V, the switching regulator becomes active. At voltages less than 0.3 V, the switching regulator becomes inactive, and the input current drops to 10μA or less. Thus the IC can be controlled from 2.5V, 3.3V or 5V power supplies. ・5VReg (22 pin) 5.0V reference voltage output pin. If at least 2.2V is supplied to either the EN1 or EN2 pin, the reference output is switched on. This pin supplies 5.0V at up to 10mA. Inserting a 4.7μF capacitor (with a X5R or X7R rating) between the 5VReg and GND pins is recommended. ・ILIM1 (24 pin) / ILIM2 (19 pin) The IC monitors the voltage between the SW pin and PGND pin as a control for the output current protection (OCP) mechanism. The voltage at which OCP engages is determined by the resistance value connected to the ILIM pin. This also allows for compatibility with FETs of various RON values. ・VIN (23 pin) The IC determines the duty cycles internally based upon the in put voltage on this pin. Theref ore, variations in voltage on this pin can lead to highly unstable operation. This pin also ac ts as the voltage input to t he internal switching regulator block, and is sensitive to the impedance of the power supply. Attaching a bypass capacitor or RC filter on this pin as appropriate for the application is recommended. ・BOOT1 (1 pin) / BOOT2 (14 pin) This pin supplies voltage used for driving the high-side FET. Maximum absolute ratings are 25V from GND and 5.5V from SW. BOOT voltage swings between VIN + 5VReg and 5VReg during active operation. ・HG1 (28 pin) / HG2 (15 pin) This pin supplies voltage used for driv ing the gate of the high-side FET. Th is voltage swings between BOOT and SW. High-speed gate driving for the high side FET can be achieved due to its low on-resistance (5.5 Ω when HG = high, 2.5 Ω when HG = low) of the driver. ・SW1 (27 pin) / SW2 (16 pin) This pin acts as the source connection to the high-side FET. Maximum absolute rating is 20V from GND. SW voltage swings between VIN and GND. ・LG1 (26 pin) / LG2 (17 pin) This pin supplies voltage used for driv ing the gate of the low-side FET. Th is voltage swings between VDD and PGND. High-speed gate driving for the low-side FET can be achieved due to its low on-resistance (4Ω when LG = high, 2Ω when LG = low) of the driver. ・PGND1 (25 pin) / PGND2 (18 pin) This pin acts as the ground connection to the source of the low-side FET. ・GND (7 pin) This is the ground pin for all internal analog and digital power supplies. ・VOUT1 (4 pin) / VOUT2 (11 pin) This is the output voltage sense pin; this pin features an integrated discharge FET used to discharge the output capacitor when status is set to OFF. ・FB1 (5 pin) / FB2 (10 pin) This is the output feedback pin. While the internal reference vo ltage of channel 2 is fixed at 0.750V, the internal reference voltage of channel 1 is adjustable depending on the input conditions of the CTL1 and CTL2 pins. ・Vcc (21 pin) This is the power supply pin for all internal circuitry. This pin can be supplied directly by a 5V source, or via an RC filter (10 Ω, 0.01μF) from the 5VReg pin. ・CTL1 (8 pin) / CTL2 (9 pin) These pins allow for the adjustment of t he internal voltage reference (REF1) for channel 1. The pins recognize logic High at VCC-0.5 V or above, and logic Low at 0.5 V or below. Refer to the voltage adjustment table for REF1 on page 12.

Explanation of Operation The BD9540EFV is a 2ch switching regulator cont roller incorporating ROHM’s proprietary H3RegTM CONTROLLA control system. When VOUT drops due to a rapi d load change, the system quickly restor es VOUT by extending the TON time interval. H3RegTM control (Normal operation) (VOUT drops due to a rapid load change)
Timing Chart ・Soft Start Function Rush current: IIN = Co×V OUT 1ms [A] tON= VOUT VIN × 1 f [sec]・・・(1) ・・・(2) When FB falls below the threshold voltage (REF), a drop is detected, activating the H3RegTM CONTROLLA system. HG output is determined by the formula above. (See P13) LG output operates until FB voltage falls below REF voltage after HG becomes OFF. When FB (VOUT) drops due to a rapid load change, and the voltage remains below REF after the programmed tON time interval has elapsed, the system quickly restores V OUT by extending the tON time, improving transient response. Soft start is utilized when the EN pin is set high. Current control takes effect at startup, enabling a moderate “ramping start” on the output voltage. Soft start time is 1msec. And input current is determined via formula (2) below. (Co: All capacitors connected with V OUT) FB REF HG LG EN IIN 1msec VOUT FB REF HG Io LG

Timing Chart ・Over current protection circuit ・Timer Latch Type Short Circuit Protection ・Output Over Voltage Protection When output voltage rises to or above the OVP threshold voltage (1ch:1.02V, 2ch:0. 9V), output over-voltage protection engages after the set time (1.7 μs) has elapsed. During this protection period, the low-side FET opens completely for maximum reduction of output voltage (LG = high, HG = low). Output voltage can be restored either by reconnecting the EN pin or disabling UVLO. During normal operation, when FB falls below REF, HG switches high during for the period of time t ON (P8). However, if the current of the low-side FET exceeds the I LIMIT threshold, HG will switch off until it becomes below ILIMIT. tON tON HG LG IL tON tON Short protection engages when output falls to or belo w REF × 0.7. When the programmed time period (28 μs) elapses, output is latched off to prevent damage to the IC. Output voltage can be restored either by reconnecting the EN pin or disabling UVLO. FB HG LG EN/UVLO 28μs REF×0.7 HG LG OVP threshod voltage Switching VOUT 1.7μs ILIMIT

External Component Selection 1. Inductor (L) selection ※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease system efficiency. When selecting an inductor, be sure to a llow enough margin to assure that peak current does not exceed the inductor’s rated current value. ※To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance. 2. Output Capacitor (CO) Selection Also, give due consideration to the conditions in formula (7) below for output capacitance, bearing in mind that output rise time must be established within the soft start time frame: Note: an improper output capacitor may cause startup malfunctions. 3. Input Capacitor (Cin) Selection A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency. ΔI (VIN-VOUT)×VOUT ΔIL=0.3×IOUTmax. [A]・・・(4) (VIN -VOUT)×VOUT ΔVOUT=ΔIL×ESR+ESL×ΔIL/TON・・・(6) Co≦ 1ms×(Limit-IOUT) VOUT ・・・(7) Input Capacitor IRMS=IOUT× VOUT (VIN-VOUT) VIN [A]・・・(8) Where VIN=2×VOUT, IRMS= IOUT ΔIL VIN IL L Co VOUT Output Ripple Current VIN L Co VOUT ESR Output Capacitor VIN L Co VOUT Cin ESL The inductance value has a major influence on output ripple current. As formula (3) below indicates, the greater the inductance o r switching frequency, the lower the ripple current. The proper output ripple current setting is about 30% of maximum output current. (ΔIL: output ripple current; f: switch frequency) When determining a proper output capacitor, be sure to factor in the equivalent series resistance and equivalent series inductance required to set the output ripple voltage to 20mV or more. Also, make su re the capacitor’s voltage rating is high enough for the set output voltage (including ripple). Output ripple voltage is determined as in formula (6) below. (ΔIL: Output ripple current; ESR: CO equivalent series resistance, ESL: equivalent series inductance) Tss: Soft start time Limit: Over current detection IOUT : Output current In order to prevent transient spikes in voltage, the input capacitor selected must have a low enough ESR resistance to fully support a large ripple current on the output. The formula for ripple current IRMS is given in equation (8) below: LG SW HG LG SW HG LG SW HG

www.rohm.com 2009.04 - Rev.B © 2009 ROHM Co., Ltd. All rights reserved. 4. MOSFET Selection 5. Determining Detection Resistance Pmain = P RON + PGATE + PTRAN Psyn = PRON + PGATE VIN-VOUT VIN ×RON×IOUT2+5VReg×f×VDD VIN L Co VOUT synchronous switch main switch Main MOSFET power dissipation is computed as follows: (Ron: On-resistance of FET; Qg: FET gate capacitance; f: Switching frequency; Crss: FET inverse transfer function; IDRIVE: Gate peak current) Synchronous MOSFET power dissipation is computed as follows: = ・・・(10) VOUT VIN ×RON×IOUT2+Qg(High)×f×5VReg+ VIN 2×Crss×IOUT×f IDRIVE = ・・・(9) Qg loss is also incurred as internal power dissipation in the IC: For example: If Qg(High) = 20nq, Qg(Low) = 50nq, f = 300kHz, P IC(DRIVE) = Qg(High) ×f + Qg(Low)×f ×(VIN-5VReg) ・・・(11)= PIC(DRIVE) = 20n ×300k +50n×300k ×(12-5) = 0.147W The over-current protection function is controlled via the voltage detected between the SW and PGND pins – i.e., the ON-resistance of the synchronous FET. The current limit value is determined by formula (12) below: 10k RILIM ×RON ILIM= (RILIM: Resistance for setting over-current protection limit, RON: Low side FET On-resistance) VIN L Co VOUT [A]・・・(12) PGND SW RILIM

www.rohm.com 2009.04 - Rev.B © 2009 ROHM Co., Ltd. All rights reserved. 6. Output Voltage Setting The IC will try to maintain output voltage such that REF≒VFB. However, the actual output voltage will also reflect the average ripple voltage value. The output voltage is set via a resistive voltage divider between the output and the FB pin. The formula for output voltage is given in (13) below: O u t p u t v o l t a g e = × It is recommended that R1 and C1 be connected in parallel to the FB pin. In low output ripple applications (ΔV < 20 mV), add Radd and Cadd as shown in the above application circuit. For value settings, refer to the tool provided separately. REF voltage (for 2ch) is fix ed at 0.750 V; however, REF voltage (for 1ch) can be adjusted via the CTL input conditions. REF1 voltage setting table CTL1 CTL2 REF1 L L 0.781V H L 0.814V L H 0.851V H H 0.750V R1+R2 H3RegTM CONTROLLA S RQ Driver Circuit Output voltage FB R1 ESR REF VIN Cadd (for Low Ripple) Radd (for Low Ripple)

www.rohm.com 2009.04 - Rev.B © 2009 ROHM Co., Ltd. All rights reserved. 7. Relationship between output voltage and Ton duration Both 1ch and 2ch of BD9540EFV are synchr onous rectification type of switching co ntrollers operated at fixed-frequency. The Ton duration for each channel depends on the output voltage settings, as described by the following formulas. Ton1 = Ton2 = Thus from the above Ton duration, the frequency of the applied condition is Frequency = However with actual applications, there exists a rising and falling time of the SW due to the gate capacitance of the external MOSFET and the switching speed, which may vary the above parameters. Thus please also verify those parameters experimentally. 8. Relationship between output current and frequency BD9540EFV is a fixed-Ton type of switching controller. When the output current increases, the switching loss of the coil and MOSFET also increases and hence the switching frequency speeds up. The loss of the coil and MOSFET is determined as Taking the above losses into the frequency equation, then T (=1/Freq) becomes However since the parasitic resistance of the layout pattern exists in actual applications and affects the parameter, please also verify experimentally. VOUT1 VOUT2 VOUT VIN ① Loss of coil = IOUT 2 × DCR ② Loss of high-side MOSFET = IOUT 2 × Ronh × VIN ③ Loss of low-side MOSFET = IOUT 2 × Ronn × (1- VOUT ) VIN × IOUT × Ton VOUT × IOUT + ① + ② + ③ (Ronh : on-resistance of high-side MOSFET, Ronn : on resistance of low-side MOSFET) VOUT VIN × 1 Ton [kHz]・・・(16)

I/O Equivalent Circuits 1pin, 14pin (BOOT1, BOOT2) 3pin, 12pin (EN1, EN2) 22pin (5VReg) 8pin 9pin (CTL1, CTL2) 28pin, 15pin (HG1, HG2) 27pin, 16pin (SW1, SW2) 26pin, 17pin (LG1, LG2) 20pin (TEST) 24pin, 19pin (ILIM1, ILIM2) 5pin, 10pin (FB1, FB2) 21pin (VCC) 4pin, 11pin (VOUT1, VOUT2) 23pin (VIN) BOOT HG SW BOOT BOOT 300KΩ HG SW 5VReg 2MΩ 1MΩ BOOT VIN 100KΩ 5VReg 300KΩ 300KΩ 400KΩ 5VReg

Operation Notes (1) Absolute Maximum Ratings Use of the IC in excess of absolute maximum ratings (suc h as the input voltage or operating temperature range) may result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode) when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC. (2) Power Supply Polarity Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the power supply lines. An external power diode can be added. (3) Power Supply Lines In order to minimize noise, PCB layout should be designed such that separate, low-impedance power lines are routed to the digital and analog blocks. Additionally, a coupling capacitor should be inserted between all power input pins and the ground terminal. If electrolytic capacitors are used, keep in mind that their capacitance c haracteristics are reduced at low temperatures. (4) GND voltage The potential of the GND pin must be the minimum potential in the system in all operating conditions. (5) Thermal design Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions. (6) Inter-pin Shorts and Mounting Errors Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by poor soldering or foreign objects may result in damage to the IC. (7) Operation in Strong Electromagnetic Fields Using this product in strong electromagnetic fields ma y cause IC malfunction. Caution should be exercised in applications where strong electromagnetic fields may be present. (8) ASO - Area of Safe Operation When using the IC, ensure that operating conditions do not exceed absolut e maximum ratings or ASO of the output transistors. (9) Thermal shutdown (TSD) circuit The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used after this function has activated, or in applications where the operation of this circuit is assumed. (10)Testing on application boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from a jig or fixture during the eval uation process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. TSD ON Temp. [°C] (typ.) Hy steresis Temp. [°C] (typ.) BD9540EFV 175 15

www.rohm.com 2009.04 - Rev.B © 2009 ROHM Co., Ltd. All rights reserved. (11) Regarding input pins of the IC This monolithic IC contains P+ isolation and P substrat e layers between adjacent elements in order to keep them isolated. PN junctions are formed at the intersection of th ese P layers with the N layers of other elements, creating parasitic diodes and/or transistors. For example (refer to the figure below):  When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode  When GND > Pin B, the PN junction operates as a parasitic transistor Parasitic diodes occur inevitably in the structure of the IC , and the operation of these parasitic diodes can result in mutual interference among circuits, operational faults, or phy sical damage. Accordingly, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (a nd thus to the P substrate) should be avoided. (12)Ground Wiring Pattern When using both small-signal and large- current GND traces, the two ground trac es should be routed separately but connected to a single ground potential within the applicati on in order to avoid variations in the small-signal ground caused by large currents. Also ensur e that the GND traces of external components do not cause variations on GND voltage.

Power Dissipation Resistor Transistor (NPN) N N N P+ P + P P substrate GND Parasitic element Pin A N N P+ P+ P P substrate GND Parasitic element Pin B C B E N GND Pin A Parasitic element Pin B Other adjacent elements E B C GND Parasitic element Example of IC structure ①Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 1 layer No copper foil area. θj-a=86.2℃/W ②Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 2 layers, Copper foil area : 15mm×15mm, θj-a=67.6℃/W ③Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 2 layers, Copper foil area :: 70mm×70mm, θj-a=37.9℃/W ④Mounted on board 70mm×70mm×1.6mm glass-epoxy PCB, 4 layers, Copper foil area :: 70mm×70mm, θj-a=26.6℃/W Power dissipation :Pd [W] Ambient temperature :Ta [℃] 0 25 50 75 100 125 150 5.0 2.0 1.0 ④4.70W ②1.85W ①1.45W 3.0 ③3.30W 4.0

Ordering part number B D 9 5 4 0 E F V - E 2 Part No. Part No. Package EFV : HTSSOP-B28 Packaging and forming specification E2: Embossed tape and reel (Unit : mm) HTSSOP-B28 0.08 M 0.08 S S 1.0±0.2 0.5±0.15 +6° −4° 0.17 +0.05 -0.03 1528 141 (2.9) 4.4±0.1 (5.5) (MAX 10.05 include BURR) 0.625 6.4±0.2 9.7±0.1 1PIN MARK 1.0MAX 0.65 0.85±0.05 0.08±0.05 0.24 +0.05 -0.04 ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tape (with dry pack)Tape Quantity Direction of feed The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs Direction of feed Reel 1pin

R0039Awww.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Notice ROHM Customer Support System http://www.rohm.com/contact/ Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. Notes N o c o p y i n g o r r e p r o d u c t i o n o f t h i s d o c u m e n t , i n p a rt o r i n w h o l e , i s p e r m i t t e d w i t h o u t t h e consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, commu- nication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. T h e P r o d u c t s a r e n o t d e s i g n e d o r m a n u f a c t u r e d t o b e u s e d w i t h a n y e q u i p m e n t , d e v i c e o r system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.

Product Information

BD9540EFV specifications and overview.

Summary

2ch Switching Regulators for Desktop PC

Description

2ch Switching Regulators for Desktop PC

Source title BD9540EFV Datasheet(PDF) - Rohm

Related Parts

More parts from the same family.

Browse manufacturer