Power Management

BD9488F-XX

Rohm

Boost 1channel white LED driver For large LCDs

Manufacturer: Rohm

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BD9488F_14 ROHM | Alldatasheet

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○Product structure：Silicon monolithic integrated circuit ○ This product is not designed protection against radioactive rays TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003TSZ22111・14・001 www.rohm.com Boost 1channel white LED driver For large LCDs BD9488F

General Description BD9488F is a high efficiency driver for white LEDs and designed for large LCDs. This IC is built-in a boost DCDC converters that employ an array of LEDs as the light source. BD9488F has some protect function against fault conditions, such as the over-voltage protection (OVP), the over current limit protection of DCDC (OCP), LED over current protection (LEDOCP), the open detection of LED string. Therefore BD9488F is available for the fail-safe design over a wide range output voltage.
Features  Current mode DCDC converter  Vout discharge circuit as shutdown  LED protection circuit (OPEN protection, LED OCP protection)  LED protect detection as small PWM dimming signal  Over-voltage protection (OVP) for the output voltage.  Adjustable soft start time constant  The wide range of analog dimming 0.2V-3.5V  The built-in transformation circuit from pulse to DC  2 PWM dimming signal  The UVLO detection for the input voltage of the power stage  FAIL logic output
Applications  TV, PC display and other LCD backlight system.
Key Specifications  Input voltage range: 9.0V to 18.0V  DCDC oscillation frequency: 150kHz (RT=100k Ω)  Active current consumption: 1.2mA(Typ.)  Operating temperature range: -40 ℃ to +85 ℃
Package(s) W(Typ.) x D(Typ.) x H(Max.) SOP18 11.20mm x 7.80mm x 2.01mm Pin pitch 1.27mm F i g u r e 1 . S O P 1 8
Typical Application Circuit(s) F igure 2. Typical application circuit OVP DIMOUT GATE ISENSE CS RT STB PWM1 VCC TC54 UVLO SS VIN Css FB PWM2 ADIM_P ADIM VCC FAILB GND

Absolute Maximum Ratings (Ta=25℃) Parameter Symbol Ratings Unit Input voltage Vccmax 20 V STB pin voltage STB VCC V OVP, UVLO, SS, RT, ISENSE, FB, CS, TC54 pin voltage OVP, UVLO, SS, RT, ISENSE, FB, CS, TC54 7 V PWM1, PWM2, FAILB, ADIM, ADIM_P pin voltage PWM1, PWM2, FAILB, ADIM, ADIM_P 20 V DIMOUT, GATE pin voltage DIMOUT, GATE VCC V Power Dissipation Pd 687 (*1) mW Operating Temperature Range Topr -40 to +85 ℃ Junction Temperature Tjmax 150 ℃ Storage Temperature Range Tstg -55 to +150 ℃ *1 Pd derated at 5.5 mW/℃ for temperature above Ta=25℃, mounted on 70mm×70mm×1.6mm 1 layer glass-epoxy PCB.
Operation range Parameter Symbol Range Unit VCC Power source voltage VCC 9.0 to 18.0 V DC/DC oscillation frequency fsw 50 to 800 kHz The effective range of ADIM signal VADIM 0.2 to 3.5 V PWM input frequency range FPWM 90 to 100k Hz
P i n C o n f i g u r a t i o n ●Package dimension, marking diagram Figure 3-1. Pin configuration Figure 3-2. Package dimension OVP UVLO SS FAILB PWM1 RT CS ADIM TC54 FB ISENSE STB VCC GATE GND DIMOUT PWM2 ADIM_P BD9488F Lot No.

1.1 Electrical character (Unless otherwise specified Ta=25℃，VCC=12V) Parameter Symbol Limit Unit Condition Min. Typ. Max. 【Total current consumption】 Circuit current Icc － 1.2 1.8 mA VSTB=3V, PWM1=PWM2=0V Standby current IST － 0 3 μA VSTB=0V 【UVLO block】 Operation voltage（VCC） VUVLO_VCC 6.5 7.5 8.5 V VCC=SWEEP UP Hysteresis Voltage（VCC） VUHYS_VCC 150 300 600 mV VCC=SWEEP DOWN UVLO release voltage VUVLO 2.88 3.00 3.12 V VUVLO=SWEEP UP UVLO hysteresis voltage VUHYS 250 300 350 mV VUVLO=SWEEP DOWN UVLO pin leak current UVLO_LK -2 0 2 μA VUVLO=4V 【DC/DC block】 ISENSE threshold voltage 1 VLED1 1.47 1.50 1.53 V VADIM=1.5V ISENSE threshold voltage 2 VLED2 3.33 3.50 3.67 V VADIM=5.0V (as mask analog dimming) ISENSE threshold voltage 3 VLED3 -2 - +2 % VADIM=0.7V Oscillation frequency FCT 142.5 150 157. 5 KHz RT=100kohm GATE pin MAX DUTY output NMAX_DUTY 90 95 99 % RT=100kohm GATE pin ON resistance (as source) RONSO 3.0 6.0 12.0 Ω ION=-10mA GATE pin ON resistance (as sink) RONSI 1.2 2.5 5.0 Ω ION=10mA RT pin voltage VRT 1.0 1.5 2.0 V RT=100kohm SS pin source current ISSSO -4.20 -3.0 -2.14 μA VSS=2V SS pin Low output voltage VSS_L - 0.20 0.50 V VSTB=0V, Ioss=50uA Soft start ended voltage VSS_END 2.7 3.0 3.3 V SS=SWEEP UP FB source current IFBSO -140 -100 -60 μA VISENSE=0.2V, VADIM=1.0V, VFB=1.0V FB sink current IFBSI 60 100 140 μA VISENSE=2.0V, VADIM=1.0V, VFB=1.0V OCP detect voltage VCS 360 400 440 mV CS=SWEEP UP 【DC/DC protection block】 OVP detect voltage VOVP 2.88 3.00 3.12 V VOVP SWEEP UP OVP detect hysteresis VOVP_HY S 50 100 150 mV VOVP SWEEP DOWN OVP pin leak current OVP_LK -2 0 2 μA VOVP=4V

1.2 Electrical character (Unless otherwise specified Ta=25℃，VCC=12V) Parameter Symbol Limit Unit Condition Min. Typ. Max. 【LED protection block】 LED OCP detect voltage VLEDOCP 3.8 4.0 4.2 V VISENSE=SWEEP UP LED OPEN detect voltage VOPEN 0. 05 0.10 0.15 V VISENSE=SWEEP DOWN 【Analog dimming block】 ADIM_P pin HIGH voltage ADIM_PH 2.0 - 3.8 V ADIM_P pin LOW voltage ADIM_PL -0.3 - 0.8 V ADIM_P pin input mask voltage ADIM_PPU 4.2 - 18 V ADIM_P pin pull-down resistance RADIM_P 130 200 300 k Ω VADIM_P=3.0V ADIM pin output voltage H ADIMH 3.201 3.30 3.399 V ADIM_P=3.3V ADIM pin output voltage L ADIML - 0.0 0.05 V ADIM_P=0.0V ADIM pin output resistance ADIMR 6.6 10 15 k Ω ADIM pin leak current ILADIM -2 0 2 μA VADIM=4V, ADIM_P=5.0V ISENSE pin leak current IL_ISENSE -2 0 2 μA VISENSE=4V 【Dimming signal output block】 DIMOUT source on-resistance RONSO 6.0 12.0 24.0 Ω ION=-10mA DIMOUT sink on-resistance RONSI 1.7 3.5 7.0 Ω ION=10mA 【TC54 block】 TC54 output voltage VTC 54 5.2 5.4 5.6 V IO=0mA TC54 available current |ITC54| 100 - - μA TC54_UVLO detect voltage TC54_TH 2.232 2.4 2.568 V VSTB=H, TC54=SWEEP DOWN TC54_UVLO hysteresis TC54_HYS 50 100 200 mV VSTB=H->L, TC54=SWEEP UP TC54 discharge current TC54_DIS 5 10 15 μA VSTB=H->L, TC54=4V 【STB block】 STB pin HIGH voltage STBH 2.2 - 19 V VSTB=SWEEP UP STB pin LOW voltage STBL -0.3 - 0.8 V VSTB=SWEEP DOWN STB pin input current ISTB 2.0 3.0 4.5 μA VSTB=3.0V 【PWM block】 PWMｘ pin HIGH Voltage PWM_H 2.0 - 18 V VPWMｘ=SWEEP UP PWMｘ pin LOW Voltage PWM_L -0.3 - 0.8 V VPWMｘ=SWEEP DOWN PWMｘ pin Pull Down resistance RPWM 130 200 300 kΩ VPWMｘ=3.0V 【FAIL block (OPEN DRAIN)】 FAILB pin on-resistance RFAIL 0.75 1.5 3.0 k Ω VFAIL=1.0V FAILB pin leak current ILFAIL -2 0 2 μA VFAIL=15V

1.3 Pin number, pin name, pin function No. name IN/OUT function rating[V] 1 OVP In Over voltage protection detection pin -0.3 to 7 2 UVLO In Under voltage lock out detection pin -0.3 to 7 3 SS Out Slow start setting pin -0.3 to 7 4 RT Out For DC/DC switching frequency setting pin -0.3 to 7 5 PWM1 In External PWM dimming signal input pin1 -0.3 to 20 6 PWM2 In External PWM dimming signal input pin2 -0.3 to 20 7 FAILB Out Abnormality detection output pin -0.3 to 20 8 ADIM In/Out ADIM signal input-output pin -0.3 to 20 9 ADIM_P In ADIM pulse signal input pin -0.3 to 20

10 GND - -

11 DIMOUT Out Dimming signal pin for driving MOSFET -0.3 to VCC 12 GATE Out DC/DC switching output pin -0.3 to VCC 13 STB In IC On/OFF pin -0.3 to VCC 14 VCC - Power supply pin -0.3 to 20 15 ISENSE In Current detection input pin -0.3 to 7 16 FB In/Out Error amplifier output pin -0.3 to 7

17 CS In DC/DC output current detect pin,

OCP input pin -0.3 to 7 18 TC54 Out 5.4V output pin, shutdown timer pin -0.3 to 7

2.1.1 Pin ESD Type OVP UVLO SS OVP 50k Internal vol. SS Internal vol. RT PWM1, PWM2 FAILB ADIM ADIM_P DIMOUT GATE STB ISENSE ISENSE 10k Internal vol. Figure 4-1. Internal equivalent circuit

2.4 Pin function description ○Pin1: OVP The OVP terminal is the input for over-voltage protection of out put voltage. As OVP is more than 3.0V, the over-voltage protection (OVP) will work. At the moment of this detection, the BD9488 stops the switching of the output GATE and starts to count up the abnormal interval, but IC doesn't reach latch off state instantaneously until the detection continues up to the number of counts of GATE terminals, wh ich depend on the kind of abnormality. (Please refer to the time chart in the section 3.5.7) The OVP pin is high impedance, because the internal resistance to a certain bias is not connected. So, the bias by the external components is required, even if OVP function is not used, because the open connection of this pin is not fixed the potential. The setting examples is separately described in the section 3.4.6, ”external components selection, how to set OVP” ○Pin2: UVLO Under voltage lock out pin for the input voltage of the power stage. More than 3.0V(typ.), IC starts the boost operation and stops lower than 2.7V(typ.). The UVLO pin is high impedance, because the internal resistance to a certain bias is not connected. So, the bias by the external components is required, even if UVLO function is not used, because the open connection of this pin is not fixed the potential. The setting examples is separately described in the section 3.4.5, ”external components selection, how to set UVLO” ○Pin3: SS The pin which sets soft start interval of DC/DC converter. It performs the constant current charge of 3.0 μA to external capacitance Css(OPEN to 4.7μF). The switching duty of GATE output will be limited during 0V to 3.0V of the SS voltage. So the equality of the soft start interval can be expressed as following Tss = 1.0*106*Css Css: the external capacitance of the SS pin. Regarding of the logic of SS=L (SS=L) = (PWM1andPWM2 have not asserted H since ResetB=L->H) or (latch off state) where ResetB = (STB=H) and (VCCUVLO=H) and (UVLO=H) and (TC54UVLO=H) As the capacitor of SS pin is smaller than a bout 1nF, it is necessary to notice if the inrush current I(Vin) as turning-on is too large, and if the masking interval of OPEN detection is too short. Please refer to the time chart on soft start behavior in the section 3.7.4 ○Pin4: RT DC/DC switching frequency setting pin. RT set the oscillation frequency inside IC. ○The relationship between the frequency and RT resistance value (ideal) The oscillation setting range from 50kHz to 800kHz. The setting examples is separately described in the section 3.4.4, ”external components selection, how to set DCDC oscillation frequency” ○Pin5, Pin6: PWM1, PWM2 The ON / OFF terminal of the LED driver. LED lights when both PWM signal are high (DIMOUT = H). The Duty signal of this pin can control the PWM dimming. The high / low level of PWM pins are following. State PWM input voltage PWM1=H or PWM2=H PWM=2.0V to 18.0V PWM1=L or PWM2=L PWM=‐0.3V to 0.8V PWM1 and PWM2 have the functional difference, and GATE pin outputs only by the logic of PWM1. This is why only boost operation continues while PWM1=H, PWM2 =L. In this case, the adequate confirmation is required not to be over voltage of the output voltage Vout. ] [] [ 15000  kkHz fR SW RT

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. small considering of this input frequency, the error of LED current can be cause. over shoot of LED current, as PWM turns from low to high. by the resistor connected to RT. Please refer to the <RT> pin description for the frequency setting. ON/OFF setting terminal for IC, which can be used to perform a reset at shutdown. Please reset this pin after latch off. activated. After the positive edge of PWM is input , BD9488 starts the boost operation. Power supply pin of IC. Input range is from 9V to 18.0V. detected. If that states c ontinues 130k clock of GATE pin, IC will latch off. insufficient output voltage Vout. the analog dimming signal (pin ADIM) or 3.5V. is hold to the external capacitance. Figure 14. ISENSE pin circuit

DC / DC current mode Feedback terminal
Inductor current limit (OCP) terminal

than 0.4V, the switching operation will be stopped compulsorily. / how to set OCP”, for detail explanation. calculation. Because the current Id flow not only Rcs but also Cs, as the CS pin voltage move according to Id. This is the 5.4V (TYP.) output pin that is used for internal power supply. Available current is 100uA. Figure 15. CS pin circuit

3.2 The detection condition list of the protection (TYP. Condition) Protection Detection pin Detect condition Release condition Timer operation Protection type pin condition PWM1 and PWM2 SS LED OPEN ISENSE ISENSE < 0.1V H(4count) SS>3.0V ISENSE > 0.1V 130k count Latch off LED OCP ISENSE ISENSE > 4.0V - - ISENSE < 4.0V 130k count Latch off UVLO UVLO UVLO<2.7V - - UVLO >3.0V NO Auto recovery TC54 UVLO TC54 TC54<2.4V - - TC54>2.5V NO Auto recovery VCC UVLO VCC VCC<7.2V - - VCC>7.5V NO Auto recovery OVP OVP OVP>3.0V - - OVP<2.9V 4 count Latch off OCP CS CS>0.4V - - - NO Pulse by Pulse To reset the latch type protection, please input of STB logic to ‘L’ once. Otherwise the detection of VCCUVLO, TC54UVLO is required. The count number in the table suggests the oscillation frequency of DCDC converter.
3.3 The behavior list of the protection Protect Function The operation of the protection DC/DC Gate output Dimming transistor (DIMOUT) logic Soft Start FAILB pin LED OPEN Stops after latch L after latch discharge after latch L after latch LED OCP Stops immediately H immediately, L after latch discharge after latch L after latch STB Stops immediately L if TC54<2.4V discharge immediately OPEN UVLO Stops immediately immediately L discharge immediately immediately L TC54 UVLO Stops immediately immediately L discharge immediately immediately L VCC UVLO Stops immediately immediately L discharge immediately immediately L OVP Stops immediately immediately L discharge after latch L after latch OCP Stops immediately Normal operation Not discharge OPEN Please refer to the timing chart in the section 3.7 for the detail.

3.4 External components selection
3.4.1 The start up operation and the setting of Soft Start external capacitance The below explanations are the start up sequency of BD9488. F i g u r e 2 1 . t h e t u r n - o n w a v e f o r m F i g u r e 2 2 . t h e t u r n - o n c i r c u i t ○The explanation of start up sequency ①When STB is H, the internal bias voltage of TC54 rising. ②With the first PWM=H, BD9488 enables output the boost pulse, and the SS start to charge to the external capacitance. At this moment, the voltage of FB will be the same as SS voltage internally regardless of the PWM logic. ③The FB=SS voltage reach the bottom voltage of saw-toothed wave and the DC/DC start to output the pulse signal. Therefore the boost of VOUT is started. ④VOUT is boosted to fixed level, and the LED current is rising. ⑤When the LED current reached to fixed level, FB is removed from SS internally. The start up operation completed. ⑥IC start the normal operation by sensing the voltage of ISENSE pin. When SS is more than 3.0V, even if the LED current does not flows, the clamped circuit of SS and FB is off, and the protect detection of OPEN starts. ○The setting method of SS external capacitance As above desribed, DC/DC stops when the PWM1=L. It means the boost operation only enabled within PWM1=H duration and SS time will be extented while boost with samll PWM duty. Also the SS time is affected by the output capacitance, the LED current and application conditions. Tss is defined as the time for the SS voltage to reach to the FB feedback voltage. Please set the Tss longer than Trise_min, which is the start up time of the minimum PWM duty. When the FB voltage during LED turns on is expressed VFB, the equality on Tss is the following. So please set the external capacitance to meet the Tss>>Trise_min. ] [] [ 3 ] [ ] [SecA V VFB F CT ss ss  LED_OK SS=FB Circuit SS FB OSC DRIVER COMP GATE ISENSE VOUTILED PWM PWM=L : STOP 3uASS SLOPE DQ PWM Css DIMOUT STB SS SLOPE PWM GATE VOUT ILED LED_OK FB OSC

3.4.4. how to set DCDC oscillation frequency RRT which connects to RT pin set the oscillation frequency of DCDC. ○ the relationship between OSC and R RT (ideal) where fsw is the oscillation frequency of DCDC [kHz] This equation is an ideal equation in which correction factors are not applied. The adequate verification with an actual set needs to be performed to set frequency precisely. [setting example] If DCDC oscillation frequency is 200kHz, we can calculate the R RT as below. Ideal RT RRT GATE CS GND Rcs Frequency (fsw)

Figure 25. RT pin setting example

3.4.5. how to set UVLO Under voltage lock out pin for the input voltage of the power stage. More than 3. 0V(typ.), IC starts boost operation and stops lower than 2.7V(typ.). The UVLO pin is high impedance, because the internal resistance to a certain bias is not connected. So, the bias by the external components is required, even if UVLO function is not used, because the open connection of this pin is not fixed the potential. The resistor value can be calculated by the below formula, if the VIN voltage is monitored, and that is divided by the resistor R1, R2 like the below diagram. ○UVLO detection equality If VIN decreases, R1, R2 value is expressed the following formula by the VINdet, the detect voltage of UVLO. ○UVLO release equality By using the R1, R2 in the above equality, the release voltage of UVLO can be expressed as following. [setting example] If the normal input voltage, VIN is 24V, the detect voltage of UVLO is 18V, R2 is 30k ohm, R1 is calculated as following. By using these R1, R2, the release voltage of UVLO, VINcan can be calculated as following. ] [] [ 2 k R k RVVINCAN UVLO CUVLO VIN ON/OFF 2.7V/3.0V ] [] [ . V V VINk R R DET 7 2 7 22 1 ] [ .] [ . V VkV V V VINk R R DET 0 1707 2 7 2 18307 2 7 22 1 ] [ . ] [] [ ] [ ] [ .] [ .] [ k kVk R k R k RVVINCAN 0 2030 30 0 1700 32 2 10 3 

Figure 26. UVLO setting example

3.4.6. how to set OVP The OVP terminal is the input for over-voltage protection of output voltage. The OVP pin is high impedance, because the internal resistance to a certain bias is not connected. So, the bias by the external components is required, even if OVP function is not used, bec ause the open connection of this pin is not fixed the potential. The resistor value can be calculat ed by the below formula, if the VOUT voltage is monitored, and that is divided by the resistor R1, R2 like the below diagram. ○OVP detection equality If the VOUT is boosted abnormally, VOVPdet is the detect voltage of OVP, R1, R2 can be expressed by the following formula. ○OVP release equality By using the R1, R2 in the above equality, the release voltage of OVP, VOVPcan can be expressed as following. [setting example] If the normal output voltage, VOUT is 40V, the detect voltage of OVP is 48V, R2 is 10k ohm, R1 is calculated as following. By using these R1, R2, the release voltage of OVP, VOVPcan can be calculated as following. ] [] [ 0 . 3 V V VOVPk R R DET ] [] [ 2 k R k RVVOVPCAN ] [ 150] [ 3 V VkV V V VOVPk R R DET k kVk R k R k RVVOVPCAN  OVP COVP VOUT OVP 2.9V/3.0V

Figure 27. OVP setting example

3.4.7. how to set the interval until latch off BD9488 built in the counter by latch off time, that is performed by counting the oscillation clock which is set by the RT pin. Since the common oscillation circuit is used for counting, the interval until latch off is corresponding to the 130k clock, which the GATE pulse output continuously. Please refer the time chart of the operation from the detect abnormality to the latch off in the section 3.7. ○latch off time BD9488 starts the counting up from the detection of each abno rmal state, falls to the latch off state when the following interval has passed. Only PWM=L input does not reset the timer counter, if the abnormal state continues. Where LATCHTIME is the interval until latch off state R RT is the connected resistor of RT pin. [setting example] If the resistor of RT pin is 100k ohm, the timer latch interval is as following. [sec] 10 5 . 1 ] [130 10 5 . 1 ] [2 710     k RkRLATCH RTRT TIME sec] [ 866 10 5 . 1 ] [ 100130 10 5 . 1 ] [130 77 mkkk RkLATCH RT TIME     

3.5. DCDC parts selection 3.5.1. how to set OCP / the calculation method for the current rating of DCDC parts BD9488 stops the switching by the OCP detect, when the CS pin voltage is more than 0.4V. The resistor value of CS pin, RCS need to be considered by the coil L current. And the current rating of DCDC external parts is required more than the peak current of the coil. It is shown below that the calculation method of the coil peak current, the selection method of Rcs (the resistor value of CS pin) and the current rating of the external DCDC parts. (the calculation method of the coil peak current, Ipeak) At first, since the ripple voltage at CS pin depend on the application condition of DCDC, those put onto the equality to calculate as following. The output voltage = VOUT [V] LED total current = IOUT [A] The DCDC input voltage of the power stage = VIN [V] The efficiency of DCDC =η[%] And then, the averaged input current IIN is calculated by the following equality And the ripple current of the inductor L ( ΔIL[A]) can be calculated by using DCDC the switching frequency, fsw, as following. On the other hand, the peak curr ent of the inductor Ipeak can be expressed as the following equality. … (1) Therefore, the bottom of the ripple current Imin is o r 0 As Imin>0, that operation mode is CCM (Continuous Current Mode), otherwise another mode is DCM (Discontinuous Current Mode). (the selection method of Rcs) Ipeak flows into Rcs and that caus e the voltage signal to CS pin. (Please refer the right timing chart) That peak voltage VCSpeak is as following. As this VCSpeak reaches to 0.4V, the DCDC output stops the switching. Therefore, Rcs value is necessary to meet the under condition. (the current rating of the external DCDC parts) The peak current as the CS voltage reaches to OCP level (0.4V) is defined as Ipeak_det. … ( 2 ) The relation among Ipeak (equality (1)), Ipeak_det (equality (2)) and the current rating of parts is required to meet the following Please make the selection of the external parts to meet the above condition such as FET, Inductor, diode. [setting example] The output voltage = VOUT [V] = 40V LED total current = IOUT [A] = 0.48V The DCDC input voltage of the power stage = VIN [V] = 24V ] [[%] ] [ ] [ ] [AV V A I V VI IN OUTOUT IN ] [] [ ] [ ] [ ] [ ]) [ ] [ (AHz f V V H L V V V V V VIL SWOUT ININOUT    Δ ] [V Ipeak RcsVCS peak    det _peakpeak I I The current rating of parts ] [ 4 . 0 ] [V V Ipeak Rcs VIN VOUT GATE CS GND Rcs IL L IOUTfsw ] [] [ Im A ILA I inIN   ] [2 ] [] [ AA ILA I IpeakIN   ] [] [ ] [ 4 . 0 det _ ARcs VI peak  IIN （A) (t) 0.4V (t) （V) (V)VCS[V] IL[A] ΔIL (t) N[V] Ipeak Imin VCSpeak

Figure 28. Coil current waveform

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F The efficiency of DCDC =η[%] = 90% The averaged input current IIN is calculated as the following. And the ripple current of the inductor L ( ΔIL[A]) can be calculated if the switchin g frequency, fsw = 200kHz, the inductor, L=100μH. Therefore the inductor peak current, Ipeak is The calculation result of the peak current If Rcs is assume to be 0.3 ohm The Rcs value confirmation The above condition is met. And Ipeak_det, the current OCP works is If the current rating of the used parts is 2A, The current rating confirmation of DCDC parts This inequality meets the above relationship. The parts selection is proper. And Imin, the bottom of the IL ripple current can be calculated as following. This inequality implies the operation is the continuous current mode. ] [ 48 . 0 ] [ 40 [%] ] [ ] [ ] [] [ AV A V V V A I V VA I IN OUTOUT IN     ] [ 48 . 0] [ 10 200 ] [ 40 ] [ 10 100 ] [ ] [ ] [ ] [ ]) [ ] [ (

36 AHzV H

   Δ ] [ 13 . 12 ] [] [ AAA AA ILA I IpeakIN     ] [] [     A A A AA ILA I IINMIN V VAIpeak RcsVCS peak 4 . 0 ] [ 339 . 0 ] [ 13 . 1 ] [ 3 . 0   ] [ 4 . 0 det _ AVI peak   det _peakpeak I I The current rating ] [ 0 . 2 ] [ 33 . 1 ] [ 13 . 1A AA 

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F 3.5.4. MOSFET selection Though there is no problem if the absolute maximum rating is larger than the rated current of the inductor L, or is larger than the sum of the tolerance voltage of COUT and the rectifying diode VF. The product with small gate capacitance (injected charge) needs to be selected to achieve high-speed switching. * One with over current protection setting or higher is recommended. * The selection of one with small on resistance results in high efficiency. 3.5.5. Rectifying diode selection A schottky barrier diode which has current ability higher than the rated current of L, the reverse voltage larger than the tolerance voltage of COUT, and the low forward voltage VF especially needs to be selected.

3.6. Loop compensation A current mode DCDC converter has each one pole (phase lag) fp due to CR filter composed of the output capacitor and the output resistance (= LED current) and zero (phase lead) fZ by the output capacitor and the ESR of the capacitor. Moreover, a step-up DCDC converter has RHP zero (right-half plane zero point) fZRHP which is unique with the boost converter. This zero may cause the unstable feedback. To avoid this by RHP zero, the loop compensation that the cross-over frequency fc set as following, is suggested. fc = fZRHP /5 (f ZRHP: RHP zero frequency) Considering the response speed, the below calculated constant is not always optimized completely. It needs to be adequately verified with an actual device.

Figure 31. the circuit of output stage and the error amplifier with an actual device in consideration of vary from parts to parts since phase margin is decreased.

1 Ff RC

3.7. Timing chart 3.7.1 starting up 1 (STB inputs and PWM signal succeeds) V5UVLO VCC 7.5V STB GATE PWM1 andPWM2 TC54 2.5V SS 3.0V 2.4V 2.5V OFF SS NormalSTANDBY OFF SS STANDBY (Reset) FAILB 1.1V 1.1V (*1)…TC54 starts up if STB turns from L to H. The pin SS is not charged in the state that the PWM signal is not input, the boost is not started. (*2)…The charge of the pin SS starts by the positive edge of PWM=L to H, and the soft start starts. The GATE pulse outputs only during PWM=H. And as the SS is less than 1.1V, the pulse does not output. The pin SS continues charging in spite of the assertion of PWM and OVP. (*3)…The soft start interval will end if the voltage of the pin SS, Vss reaches to 3.0V. By this time, BD9488 boost Vout where the set LED current flows. It is started to monitor the abnormal detection of OPEN. (*4)…As STB=L, instantaneously the boost operation is stopped. (GATE=L, SS=L) On the other hand, the discharge circuit works in the interval “STB=L and V5UVLO=H”. Please refer to the time chart in the section 3.7.3 for details. (*5)…As STB=H again, the boost operation restarts by the next PWM=L to H. It is the same operation as the timing of (*1). Please refer to the section 3.4.1 for the setting of soft start external capacitance.

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F 3.7.2 starting up 2 (PWM signal inputs and STB succeeds) VCC 7.5V STB GATE V5UVLO TC54 SS 3.0V OFF SS OFF SS STANDBY (Reset) ON 2.5V 2.4V 2.5V FAILB PWM1 andPWM2 1.1V 1.1V (*1)…TC54 starts up if STB turns from L to H. (*2)…At the moment the release of V5UVLO (the UVLO of the pin TC54), or the time of the positive edge of PWM=L to H, the soft start starts. The GATE pulse outputs only during PWM1=H. And as the SS is less than 1.1V, the pulse does not output. The pin SS continues charging in spite of the assertion of PWM and OVP. (*3)…The soft start interval will end if the voltage of the pin SS, Vss reaches to 3.0V. By this time, BD9488 boost Vout where the set LED current flows. It is started to monitor the abnormal detection of OPEN. (*4)…As STB=L, instantaneously the boost operation is stopped. (GATE=L, SS=L) On the other hand, the discharge circuit works in the interval “STB=L and V5UVLO=H”. Please refer to the time chart in the section 3.7.3 for details. (*5)…As STB=H again, it is the same operation as the timing of (*1).

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F 3.7.3 turn off V5UVLO STB TC54 2.4V DIMOUT GATE Vout SS ON Dischange OFF (*1) (*2) PWM1 andPWM2 (*1)…As STB pin turns High to Low, BD9488F stops the boost operation, starts the discharge of TC54. (*2)…During STB=L and V5UVLO=H, the DIMOUT asserts the same logic of PWM. TC54=5.4V is discharged until 2.4V by the constant current 10uA. And IC turns off. Vout need to be disc harged adequately so that LED does not turns on drastically at the next start up. For detailed instructions, please refer the section 3.4.2 “how to shutdown and set TC54 capacitance”

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F 3.7.4 the soft start function (*1)…The SS pin charge does not start by just STB=H. “PWM1=H and PWM2=H” is required to start the soft start. In the low SS voltage, the GATE pin duty is depend on the SS voltage. And as the SS is less than 1.1V, the pulse does not output. (*2)…By the low STB=L, the SS pin is discharged immediately. (*3)…As the STB recovered to STB=H, The SS charge starts immediately by the logic “PWM1 and PWM2=H” in this chart. (*4)…The SS pin is discharged immediately by the UVLO=L. (*5)…The SS pin is discharged immediately by the VCCUVLO=L (*6)…The SS pin is discharged immediately by the TC54UVLO=L (*7)…The SS pin is not discharged by the abnormal detecti on of the latch off type such as OVP until the latch off

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F 3.7.5 the OVP detection (*1)…As OVP is detected, the output GATE =L, DIMOUT=L, and the CP counter starts (*2)…If OVP is released within 4 clock of CP counter of the GATE pin frequency, the boost operation restarts. (*3)…As the OVP is detected again, the boost operation is stopped. (*4)…As the OVP detection continues up to 4 count by the CP counter, IC will be latched off. (*5)…As the latched off, the boost operation doesn't restart even if OVP is released. (*6)…The STB=L input can make IC reset. In this chart, DIMOUT asserts high by the discharge function in the paragraph 3.7.3. (*7)…It normally starts as STB turns L to H. (*8)…The operation of the OVP detection is not related to the logic of PWM.

3.7.6 LED OPEN detection

(*1)…During starting up, even if the nor mality, ISENSE<0.1V because of the low Vout. Therefore the OPEN detection will be masked for the soft start period. (*2)…In the same way, as PWM=L, ISENSE<0.1V bec ause of DIMOUT=L. OPEN will be masked, too. (*3)…Though the OPEN is detected if ISENSE< 0.1V as the PWM=H, it is not judg ed immediately to abnormal state. The behavior of GATE, FAILB keeps the normal operation. (*4)…The CP counter will start if the OPEN detection continues 4 clock of the GATE frequency. The count stops if ISENSE>0.1V. (*5)…When the OPEN detection continues up to 130k count with the CP counter, IC will be latched off. At this time, it asserts GATE=L, DIMOUT=L, FAILB=L for the first time. (*6)…The latch off state can be reset by the STB=L. (*7)…It normally starts by STB=L to H, in this figure.

3.7.7 LED OCP detection

(*1)…If ISENSE>4.0V, LEDOCP is detect ed, it becomes GATE=L. To detect LE DOCP continuously, The DIMOUT is compulsorily high, regardless of the PWM dimming signal. (*2)…When the LEDOCP releases within the GATE frequency 130k counts of the CP counter, the boost operation restarts. (*3) …As the LEDOCP is detected again , the boost operation is stopped, too. (*4)…If the LEDOCP detection continues up to 130k count with the CP counter, IC will be latched off. (*5)…Once IC is latched off, the boost operation doesn't restart even if the LEDOCP releases. (*6)…The latch off state can be reset by the STB=L. In this chart, DIMOUT asserts high by the discharge function in the paragraph 3.7.3. (*7)…It normally starts by STB=L to H. (*8)…The operation of the LEDOCP detection is not related to the logic of the PWM.

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F 3.7.8 the spontaneous detection OVP and OPEN. STB 3.0V 3.0V 2.9V CP COUNTOR OVP SS GATE DIMOUT FAILB START END START END4count 4count NORMAL OFF NORMAL （Reset） COUNTOR Latch offSTATE 0.1V 0.1V 0.1V INSENSE COUNTOR Latch off 1.1V (*1)…The time chart shows the OPEN detects faster and does not reach to the latch off state. The DIMOUT asserts high. (*2)…If OPEN and OVP is detected spontaneously , OVP has the priority, and GATE=L, DIMOUT=L. (*3)…IC will be latched off by the OVP factor. (*4)…The latch off state is reset by the STB=L. (*5)…The OVP has the priority too, in the case the OVP is detected first and the OPEN succeeds.

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital bloc k from affecting the analog block. Furthermore, connect a capacitor to ground at all po wer supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground trac es of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Thermal Consideration Should by any chance the power dissipation rating be exceed ed the rise in temperature of the chip may result in deterioration of the properties of the ch ip. The absolute maximum rating of the Pd stated in this specification is when the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy b oard. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. Recommended Operating Conditions These conditions represent a range within which the expected characteristics of the IC can be approximately obtained. The electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give s pecial consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under Strong Electromagnetic Field Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction. 9. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always dischar ge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assemb ly and use similar precautions during transport and storage. 10. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PC B. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few.

TSZ02201-0F1F0C100040-1-2© 2012 ROHM Co., Ltd. All rights reserved. 27.May 2014 Rev.003 www.rohm.com TSZ22111・15・001 BD9488F Operational Notes – continued 11. Unused Input Pins Input pins of an IC are of ten connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unc onnected, the electric field from th e outside can easily charge it. The small charge acquired in this way is enough to produce a signifi cant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line. 12. Regarding the Input Pin of the IC This monolithic IC contains P+ isolat ion and P substrate layers between adjac ent elements in order to keep them isolated. P-N junctions are formed at the intersection of t he P layers with the N layers of other elements, creating a parasitic diode or transistor. For example (refer to figure below): When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical dam age. Therefore, conditions that cause these diodes to operate, such as applying a voltage lower than the GND voltage to an input pin (a nd thus to the P substrate) should be avoided. Figure xx. Example of monolithic IC structure 13. Ceramic Capacitor When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others. 14. Area of Safe Operation (ASO) Operate the IC such that th e output voltage, output current, and power dissipation are all within the Area of Safe Operation (ASO). 15. Thermal Shutdown Circuit(TSD) This IC has a built-in thermal shutdown circuit that pr events heat damage to the IC. Normal operation should always be within the IC’s power dissipation rating. If however th e rating is exceeded for a continued period, the junction temperature (Tj) will rise which will activate the TSD circui t that will turn OFF all output pins. When the Tj falls below the TSD threshold, the circuits are automatically restored to normal operation. Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the TSD circuit be used in a set desi gn or for any purpose other t han protecting the IC from heat damage. 16. Over Current Protection Circuit (OCP) This IC incorporates an integrated over current protection circuit that is acti vated when the load is shorted. This protection circuit is effective in pr eventing damage due to sudden and unexpecte d incidents. However, the IC should not be used in applications characterized by continuous operation or transitioning of the protection circuit.

Ordering Information B D 9 4 8 8 F XX Part Number Package F:SOP18 Packaging and forming specification XX: Please confirm the formal name to our sales.
Physical Dimension Tape and Reel Information
Marking Diagram (TOP VIEW) (Unit : mm) SOP18 0.3MIN 1.27 11.2±0.2 0.15±0.1 0.4±0.1 7.8±0.31.8±0.1 0.11 5.4±0.2 (MAX 11.55 include BURR) 0.1 ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tapeTape Quantity Direction of feed The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2000pcs Direction of feed Reel 1pin SOP18(TOP VIEW) BD9488F Part Number Marking LOT Number 1PIN MARK

Revision History

11.Jul.2012 001 New Release 29.Dec.2013 002 p.2 The rating of STB pin is changed from 20V to VCC. p.5 The rating of STB pin is changed from 20V to VCC. p.6 In the equivalent circuit of ST B pin, the Diode of VCC side is added. 27. May 2014 003 p.9,20 In OVP explanation, “ove r-voltage protection and short circuit protection” is changed to “over-voltage protection”.

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Minimum Package Quantity 2000 Packing Type Taping Constitution Materials List inquiry RoHS Yes BD9488F - Web Page Distribution Inventory

Product Information

BD9488F-XX specifications and overview.

Summary

Boost 1channel white LED driver For large LCDs

Description

Boost 1channel white LED driver For large LCDs

Source title BD9488F-XX Datasheet(PDF) - Rohm

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