BD9130NV-E2

BD9130NV-E2 ROHM | Alldatasheet

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www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･14･001 Datasheet 2.7V to 5.5V, 2.0A 1ch Synchronous Buck Converter integrated FET BD9130NV

• General Description ROHM’s high efficiency step-down switching regulator BD9130NV is a power supply designed to produce a low voltage including 1 volts from 5.5/3.3 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load.
• Features ■ Offers fast transient response with current mode PWM control system. ■ Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) and SLLMTM(Simple Light Load Mode) ■ Incorporates soft-start function. ■ Incorporates thermal protection and ULVO functions. ■ Incorporates short-current protection circuit with time delay function. ■ Incorporates shutdown function
• Key Specifications  Input voltage range: 2.7V to 5.5V  Output voltage range: 1.0V to 2.5V  Output current: 2.0A (Max.)  Switching frequency: 1MHz(Typ.)  Pch FET ON resistance: 200mΩ(Typ.)  Nch FET ON resistance: 160mΩ(Typ.)  Standby current: 0μA (Typ.)  Operating temperature range: -25℃ to +105℃
• Package SON008V5060: 5.00mm x 6.00mm x 1.00mm
• Applications Power supply for LSI including DSP , Micro computer and ASIC
• Typical Application Circuit Fig.1 Typical Application Circuit ○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet

• Pin Configuration
• Pin Description Pin No. Pin name PIN function

1 ADJ Output voltage detect pin

2 VCC VCC power supply input pin

3 ITH GmAmp output pin/Connected phase compensation capacitor

4 GND Ground

5 PGND Nch FET source pin

6 SW Pch/Nch FET drain output pin

7 PVCC Pch FET source pin

8 EN Enable pin(Active High)

• Block Diagram ADJ 1 VCC 2 ITH 3 GND 4 8 EN

7 PVCC

5 PGND

(TOP View) Fig.2 Pin Configuration Fig.3 Block diagram

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet

• Absolute Maximum Ratings Parameter Symbol Limits Unit VCC Voltage VCC -0.3 to +7 *1 V PVCC Voltage PVCC -0.3 to +7 *1 V EN Voltage VEN -0.3 to +7 V SW,ITH Voltage VSW,VIT H -0.3 to +7 V Power Dissipation 1 Pd1 900*2 mW Power Dissipation 2 Pd2 3900*3 mW Operating temperature range Topr -25 to +105 ℃ Storage temperature range Tstg -55 to +150 ℃ Maximum junction temperature Tjmax +150 ℃ *1 Pd should not be exceeded. *2 Derating in done 7.2mW/℃ for temperatures above Ta=25℃, Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB. *3 Derating in done 31.2mW/℃ for temperatures above Ta=25℃, Mounted on JESD51-7.
• Operating Ratings (Ta=25℃) Parameter Symbol Limits Unit Min. Typ. Max. VCC Voltage VCC *4 2.7 *5 3.3 5.5 V PVCC Voltage PVCC *4 2.7 *5 3.3 5.5 V EN Voltage VEN 0 - VCC V SW average output current Isw *4 - - 2.0 A Output voltage Setting Range VOUT 1.0 - 2.5 V *4 Pd should not be exceeded. *5 In case set output voltage 1.6V or more, VccMin. = Vout + 1.3V.
• Electrical Characteristics◎ (Ta=25℃, VCC=PVCC=3.3V, EN=VCC, R1=10kΩ, R2=5kΩ, unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Conditions Standby current ISTB - 0 10 μA EN=GND Bias current ICC - 250 400 μA EN Low voltage VENL - GND 0.8 V Standby mode EN High voltage VENH 2.0 VCC - V Active mode EN input current IEN - 1 10 μA VEN=3.3V Oscillation frequency FOSC 0.8 1 1.2 MHz Pch FET ON resistance RONP - 200 400 mΩ PVCC=3.3V Nch FET ON resistance RONN - 160 350 mΩ PVCC=3.3V ADJ Voltage VADJ 0.788 0.800 0.812 V Output voltage VOUT - 1.200 - V ITH sink current ITHSI 10 20 - μA VADJ=1.0V ITH source current ITHSO 10 20 - μA VADJ=0.6V UVLO threshold voltage VUVLO1 2.400 2.500 2.600 V VCC=3→0V UVLO release voltage VUVLO2 2.425 2.550 2.700 V VCC=0→3V Soft start time TSS 0.5 1 2 ms Timer latch time TLATCH 1 2 3 ms SCP/TSD operated Output Short circuit Threshold Voltage VSCP - VOUT×0.5 VOUT×0.7 VOUT VOUT=1.2→0V

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet

• Typical Performance Curves Fig.4 Vcc-Vout Fig.5 Ven-Vout Fig.7 Ta-Vout Fig.6 Iout-Vout

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Fig.8 Efficiency Fig.9 Ta-Fosc Fig.11 Ta-VEN Fig.10 Ta-RONN RONP

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Fig.12 Ta-Icc Fig.13 Vcc-Fosc Fig.15 SW waveform Io=10mA Fig.14 Soft start waveform

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Fig.16 SW waveform Io=200mA Fig.17 Transient response Io=1A→2A(10μs) Fig.18 Transient response Io=2A→1A(10μs)

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet

• Application Information Operation BD9130NV is a synchronous rectifying step -down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLMTM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be d issipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P .N junction shoot-through protection circuit limits the shoot -through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P -channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current I L increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from I L) and a voltage feedback control signal (FB), and issue s a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N -channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. ・SLLMTM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allow s linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Curr ent Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency. Fig.19 Diagram of current mode PWM control OSC Level Shift Driver Logic R Q S IL SW ITH Current Comp Gm Amp. SET RESET FB Load SENSE VOUT VOUT Fig.20 PWM switching timing chart Fig.21 SLLMTM switching timing chart Current Comp SET RESET SW VOUT PVCC GND GND GND IL(AVE) VOUT(AVE) SENSE FB Current Comp SET RESET SW VOUT PVCC GND GND GND VOUT(AVE) SENSE FB IL Not switching IL

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Description of Operations ・Soft-start function EN terminal shifted to “High” activates a soft -starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50mV (Typ.) is provided to prevent output chattering. Fig.22 Soft start, Shutdown, UVLO timing chart ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recov ered by restarting EN or by re -unlocking UVLO. Fig.23 Short-current protection circuit with time delay timing chart t2=TLATCH Output OFF latch EN VOUT Output Short circuit Threshold Voltage IL Standby mode Operating mode Operating mode EN Timer latch EN Standby mode IL Limit t1<TLATCH Hysteresis 50mV Tss Tss Tss Soft start Standby mode Operating mode Standby mode Operating mode Standby mode Operating mode Standby mode UVLO EN UVLO UVLO VCC EN VOUT

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Information on Advantages Advantage 1：Offers fast transient response with current mode control system. Voltage drop due to sudden change in load was reduced by about 50%. Fig.24 Comparison of transient response Advantage 2： Offers high efficiency for all load range. ・For lighter load: Utilizes the current mode control mode called SLLM TM for lighter load, which reduces various dissipation such as switching dissipation (P SW), gate charge/discharge dissipation, ESR dissipation of output capacitor (P ESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load. Achieves efficiency improvement for lighter load. ・For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of P-channel MOS FET : 200mΩ(Typ.) ON resistance of N-channel MOS FET : 160mΩ(Typ.) Achieves efficiency improvement for heavier load. Offers high efficiency for all load range with the improvements mentioned above. Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated. Reduces a mounting area required. Fig.26 Example application DC/DC Convertor Controller RITH L Co VOUT CITH VCC Cin 10mm 15mm RITH CITH CIN CO L Fig.25 Efficiency VOUT IOUT VOUT IOUT 110mV Conventional product (Load response IO=0.1A→0.6A) BD9139NV (Load response IO=1A→2A) ・Output capacitor Co required for current mode control: 22μF ceramic capacitor ・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor (BD9130NV:Co=22μF, L=2.2μH) 0.001 0.01 0.1 1 100 PWM SLLMTM ①inprovement by SLLMTM system ②improvement by synchronous rectifier Efficiency η[%] Output current Io[A] 29mV

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Switching Regulator Efficiency Efficiency ŋ may be expressed by the equation shown below: Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows: Dissipation factors: 1) ON resistance dissipation of inductor and FET：PD(I2R) 2) Gate charge/discharge dissipation：PD(Gate) 3) Switching dissipation：PD(SW) 4) ESR dissipation of capacitor：PD(ESR) 5) Operating current dissipation of IC：PD(IC) 1)PD(I2R)=IOUT2×(RCOIL+RON) (R COIL[Ω]：DC resistance of inductor, R ON[Ω]：ON resistance of FET, I OUT[A]：Output current.) 2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET,f[H]：Switching frequency,V[V]：Gate driving voltage of FET) 4)PD(ESR)=IRMS2×ESR (I RMS[A]：Ripple current of capacitor,ESR[Ω]：Equivalent series resistance.) 5)PD(IC)=Vin×ICC (I CC[A]：Circuit current.) Consideration on Permissible Dissipation and Heat Generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of induc tor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. If VCC=3.3V, VOUT=1.8V, RONP=0.2Ω, RONN=0.16Ω IOUT=2A, for example, D=VOUT/VCC=1.8/3.3=0.545 =0.109+0.0728 =0.1818[Ω] As R ONP is greater than R ONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. η= VOUT×IOUT Vin×Iin ×100[%]= POUT Pin ×100[%]= POUT POUT+PDα ×100[%] Vin2×CRSS×IOUT×f IDRIVE 3)PD(SW)= (CRSS[F]：Reverse transfer capacitance of FET,IDRIVE[A]：Peak current of gate.) 0 25 50 75 100 125 150 2.0 3.0 4.0 ②0.90W ①3.9W 105 1.0 ③0.64W Fig.27 Thermal derating curve (SON008V5060) P=IOUT2×RON RON=D×RONP+(1-D)RONN D：ON duty (=VOUT/VCC) RCOIL：DC resistance of coil RONP：ON resistance of P-channel MOS FET RONN：ON resistance of N-channel MOS FET IOUT：Output current Power dissipation:Pd [W] Ambient temperature:Ta [℃] ①for SON008V5060 JEDEC 4 layer board 76.2×114.3×1.6mm θj-a=32.1℃/W ②for SON008V5060 ROHM standard 1 layer board 70×70×1.6mm θj-a=138.9℃/W ③ IC only θj-a=195.3℃/W

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Selection of Components Externally Connected 1. Selection of inductor (L) * Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=3.3V, VOUT=1.8V, f=1MHz, ΔIL=0.2×2A=0.4A, for example,(BD9130NV) * Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) 3. Selection of input capacitor (Cin) A low ESR 10μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. The inductance si gnificantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. ΔIL= (VCC-VOUT)×VOUT Appropriate ripple current at output should be 20% more or less of the maximum output current. ΔIL=0.2×IOUTmax. [A]・・・(2) (VCC-VOUT)×VOUT (ΔIL: Output ripple current, and f: Switching frequency) Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)： ΔVOUT=ΔIL×ESR [V]・・・(4) (ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor) *Rating of the capacitor should be determined allowing sufficient margin against output voltage. A 22μF to 100μF ceramic capacitor is reco mmended. Less ESR allows reduction in output ripple voltage. Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5): IRMS=IOUT× VOUT(VCC-VOUT) VCC [A]・・・(5) When Vcc is twice the VOUT, IRMS= IOUT Fig.29 Output capacitor (3.3-1.8)×1.8 < Worst case > IRMS(max.) IRMS=2× 1.8(3.3-1.8) 3.3 =0.99[ARMS] Fig.30 Input capacitor ΔIL VCC IL L Co VOUT Fig.28 Output ripple current IL VCC L Co VOUT ESR VCC L Co VOUT Cin If VCC=3.3V, VOUT=1.8V, and IOUTmax.=2A, (BD9130NV)

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. Gain [dB] Phase [deg] Fig.31 Open loop gain characteristics A -90 A -90 fz(Amp.) Fig.32 Error amp phase compensation characteristics fp= 2π×RO×CO fz(ESR)= 2π×ESR×CO Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. fp(Min.)= 2π×ROMax.×CO 1 [Hz]←with lighter load fp(Max.)= 2π×ROMin.×CO 1 [Hz] ←with heavier load Zero at power amplifier fz(Amp.)= 2π×RITH×CITH GND,PGND SW VCC,PVCC EN VOUT ITH VCC VOUT Cin RITH CITH L ESR CO RO VOUT Fig.33 Typical application fz(Amp.)= fp(Min.) 2π×RITH×CITH 1 = 2π×ROMax.×CO fp(Min.) fp(Max.) fz(ESR) IOUTMin. IOUTMax. Gain [dB] Phase [deg] Increasing capacitance of th e output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.)

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet 5. Determination of output voltage The output voltage VOUT is determined by the equation (6): VOUT=(R2/R1+1)×VADJ・・・(6) V ADJ: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required. Adjustable output voltage range : 1.0V to 2.5V Use 1 kΩ to 100 kΩ resistor for R1. If a resistor of the resistance higher than 100 kΩ is used, check the assembled set carefully for ripple voltage etc. Cautions on PC Board Layout Fig.36 Layout diagram ① For the sections drawn with heavy line, use thick conductor pattern as short as possible. ② Lay out the input ceramic capacitor C IN closer to the pins PVCC and PGND, and the o utput capacitor Co closer to the pin PGND. ③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. SON008V5060 (BD9130NV) has thermal FIN on the reverse of the package. The package thermal performance may be en hanced by bonding the FIN to GND plane which take a large area of PCB. Fig.34 Determination of output voltage Fig.35 minimum input voltage in each output voltage SW ADJ L Co R2 Output The lower limit of input voltage depends on the output voltage. Basically, it is recommended to use in the condition : VCCmin = VOUT+1.3V. Fig.34. shows the necessary output current value at the lower limit of input voltage. (DCR of inductor : 0.1Ω) This data is the characteristic value, so it’ doesn’t guarantee the operation range, Vo=2.5V Vo=2.0V Vo=1.8V 2.7 2.9 3.1 3.3 3.5 3.7 3.9 0 0.5 1 1.5 2 OUTPUT CURRENT : IOUT[A] IN PU T VOL TAGE : VCC [V] ADJ VCC ITH GND EN PVCC SW PGND VCC RITH GND Co CIN VOUT EN L CITH

www.rohm.com TSZ02201-0J3J0AJ00130-1-2 TSZ22111･15･001 BD9130NV Datasheet Recommended Components Lists on Above Application Symbol Part Value Manufacturer Series L Coil 2.2uH TDK LTF5022-2R2N3R2 CIN Ceramic capacitor 22uF Kyocera CM32X5R226M10A CO Ceramic capacitor 22uF Kyocera CM316B226M06A CITH Ceramic capacitor VOUT=1.0V 680pF murata GRM18 Serise VOUT=1.2V 560pF murata GRM18 Serise VOUT=1.5V 470pF murata GRM18 Serise VOUT=1.8V 330pF murata GRM18 Serise VOUT=2.5V 330pF murata GRM18 Serise RITH Resistance VOUT=1.0V 10kΩ Rohm MCR03 Serise VOUT=1.2V 12kΩ Rohm MCR03 Serise VOUT=1.5V 15kΩ Rohm MCR03 Serise VOUT=1.8V 18kΩ Rohm MCR03 Serise VOUT=2.5V 18kΩ Rohm MCR03 Serise * The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode established between the SW and PGND pins.

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• I/O Equivalence Circuit Fig.37 I/O equivalence circuit EN ・EN pin ・SW pin PVCC SW PVCC PVCC ITH ・ITH pin VCC ・ADJ pin ADJ

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• Operational Notes 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating te mperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assemblin g processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals This is a monolithic IC with P + isolation between P-substrate and each element as illustrated below. This P -layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 38. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P -substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Fig.38 Simplified structure of monorisic IC 8. Ground wiring pattern If small -signal GND and large -current GND are provided, It will be recommended to separate the large -current GND pattern from the small -signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 9. Selection of inductor It is reco mmended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, in case output voltage is set 1.6V or more, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between ext ernal devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range. Status of this document The Japanese version of th is document is formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority.

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• Ordering Information B D 9 1 3 0 N V - E2 Package NV : SON008V5060 Packaging and forming specification E2: Embossed tape and reel (SON008V5060)
• Physical Dimension Tape and Reel Information Marking Diagram SON008V5060 (TOP VIEW) B D 9 1 3 0 Part Number Marking LOT Number 1PIN MARK

Notice - Rev.001 Notice

• Precaution for circuit design 1) The products are designed and produced for applicatio n in ordinary electronic equipment (AV equipment, OA equipment, telecommunication equipment, home appliances, amusement equipment, etc.). If the products are to be used in devices requiring extremel y high reliability (medical equipment, transport equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or operational error may endanger human life and sufficient fail-safe measures, please consult with the ROHM sales staff in advance. If product malfunctions may re sult in serious damage, including that to human life, sufficient fail-safe measures must be taken, including the following: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits in the case of single-circuit failure 2) The products are designed for use in a standard environment and not in any spec ial environments. Application of the products in a special environment can deteriorate product per formance. Accordingly, verification and confirmation of product performance, prior to use, is recommended if used under the following conditions: [a] Use in various types of liquid, includin g water, oils, chemicals, and organic solvents [b] Use outdoors where the products are exposed to direct sunlight, or in dusty places [c] Use in places where the products are exposed to sea winds or corrosive gases, including Cl 2, H2S, NH3, SO2, and NO2 [d] Use in places where the products are exposed to static electricity or electromagnetic waves [e] Use in proximity to heat-producing componen ts, plastic cords, or other flammable items [f] Use involving sealing or coating the prod ucts with resin or other coating materials [g] Use involving unclean solder or use of water or water-soluble cleaning agents for cleaning after soldering [h] Use of the products in places subject to dew condensation 3) The products are not radiation resistant. 4) Verification and confirmation of performance characte ristics of products, after on-board mounting, is advised. 5) In particular, if a transient load (a large amount of load applied in a short per iod of time, such as pulse) is applied, confirmation of performance characteristics after on-boar d mounting is strongly recomm ended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 6) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual ambient temperature. 7) Confirm that operation temper ature is within the specified range described in product specification. 8) Failure induced under deviant condition from what def ined in the product specification cannot be guaranteed.
• Precaution for Mounting / Circuit board design 1) When a highly active halogenous (chlori ne, bromine, etc.) flux is used, the remainder of fl ux may negatively affect product performance and reliability. 2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the Company in advance. Regarding Precaution for Mounting / Circuit board design, please specially refer to ROHM Mounting specification
• Precautions Regarding Application Examples and External Circuits 1) If change is made to the constant of an external circuit, allow a sufficient margin due to variations of the characteristics of the products and external components, including transient characteristics, as well as static characteristics. 2) The application examples, their constants, and other types of information cont ained herein are applicable only when the products are used in accordance with standard methods . Therefore, if mass production is intended, sufficient consideration to external conditions must be made.

Notice - Rev.001

• Precaution for Electrostatic This product is Electrostatic sensitive product, which may be damaged due to Electrostatic discharge. Please take proper caution during manufacturing and st oring so that voltage exceeding Product ma ximum rating won't be applied to products. Please take special care under dry condition (e.g. Grounding of human body / equipment / so lder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
• Precaution for Storage / Transportation 1) Product performance and soldered connections may deteriorate if the products are stored in the following places: [a] Where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] Where the temperature or humidity exceeds those recommended by the Company [c] Storage in direct sunshine or condensation [d] Storage in high Electrostatic 2) Even under ROHM recommended storage c ondition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm sol derability before using products of which storage time is exceeding recommended storage time period . 3) Store / transport cartons in the correct direction, whic h is indicated on a carton as a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4) Use products within the specified time after opening a dry bag.
• Precaution for product label QR code printed on ROHM product label is only for internal us e, and please do not use at cust omer site. It might contain a internal part number that is inconsistent with an product part number.
• Precaution for disposition When disposing products please dispose them properly with a industry waste company.
• Precaution for Foreign exchange and Foreign trade act Since concerned goods might be fallen under controlled goods prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export.
• Prohibitions Regarding Industrial Property 1) Information and data on products, including application exam ples, contained in these specifications are simply for reference; the Company does not guarantee any industrial pr operty rights, intellectual property rights, or any other rights of a third party regarding this information or data. Accordingly, the Company does not bear any responsibility for: [a] infringement of the intellectual property rights of a third party [b] any problems incurred by the use of the products listed herein. 2) The Company prohibits the purchaser of its products to exercise or use the in tellectual property rights, industrial property rights, or any other rights that either belong to or are controlled by the Company, other than the right to use, sell, or dispose of the products.