BD86123AEFJ | DigiCamel IC Datasheet

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Block Diagram VREG OSC IBIAS UVLO TSD SLOP E SoftStart LOGIC OCP SCP S R VIN SW PGND FB AGN D PWM ERR COMP EN OVP
Pin Description No. Symbol Description 1 PGND Power Ground pin. Power ground return for switching circuit. 2 VIN Input voltage supply pin. 3 EN Enable input control. Active high. 4 AGND Analog Ground pin. Electrically needs to be connected to PGND. 5 FB Converter feedback input. Connect to output voltage with feedback resistor divider. 6 COMP Error amplifier output, and input to the output switch current comparator. External loop compensation pin. 7 SW Switch node connection between high-side Pch FET and Low-side Nch FET. 8 SW Switch node connection between high-side Pch FET and Low-side Nch FET. Thermal Pad Back side Thermal pad of the package. Must be soldered to ac hieve appropriate dissipation. Must be connected to AGND.

Figure 3. Block diagram

Absolute maximum ratings (Ta=25℃) Parameter Symbol Ratings Unit Condition Input supply voltage V IN 20 V SW terminal voltage V SW 20 V EN terminal voltage VEN 20 V Power dissipation Pd 3760* mW 70mm×70mm, thickness 1.6mm, and 4 layer glass epoxy substrates Operating temperature Topr -40～+85 ℃ Storage temperature Tstg -55 ～+150 ℃ Maximum Junction temperature Tjmax 150 ℃ FB, COMP terminal voltage V LVPINS 7 V * Operating at higher than Ta=25 ℃, 30.08mW shall be reduced per 1℃
Operating conditions Parameter Symbol Ratings Unit Min. Typ. Max. Input supply voltage VIN 4.5 - 18.0 V Output current IOUT - - 5.0 A Output voltage range V RANGE VIN×0.08* - V IN×0.8 V

Electrical characteristics (Unless otherwise noted Ta=25℃, VIN=12V, VEN = 3V) Parameter Symbol Limits UNIT Condition Min. Typ. Max. VIN supply current (operating) I Q_active - 1.5 2.5 mA V FB= 0.75V, VEN= 5V VIN supply current (standby) I Q_stby - 1.0 10.0 μA V EN = 0V Reference voltage (VREF) V FB 0.792 0.800 0.808 V FB-COMP Short (Voltage follower) FB input bias current I FB - 0 2 μA Oscillation frequency f OSC 500 550 600 kHz High side FET ON resistance R ONH - 90 - m Ω VIN= 12V , ISW = -1A Low side FET ON resistance R ONL - 50 - m Ω VIN= 12V , ISW = -1A SW leak current I LSW - 0 5 μA V IN= 18V , VSW = 18V Switch Current Limit I LIMIT 3.7 - - A Min duty Min_duty - - 8 % UVLO voltage V UVLO 3.8 4.1 4.4 V V IN Sweep up UVLO hysteresis V UVLOHYS - 0.3 - V EN terminal H threshold voltage V ENH 2.0 - - V EN terminal L threshold voltage V ENL - - 0.8 V Soft Start Time T SS 3.0 5.0 7.0 msec
V FB :FB terminal voltage, VEN :EN terminal voltage,
Current capability should not exceed Pd.

Functional descriptions

1 Enable control

The device can be controlled ON/OFF by EN terminal voltage. An internal circuit starts when VEN reaches 2.0V. Figure 16. ON/OFF transition wave form in EN controlling

2 Protection function

The FB terminal voltage is compared with internal reference voltage VREF. Table 1. output short circuit protection function Figure 17. SCP Timing chart

TSZ02201-0J2J0D100280-1-2© 2012 ROHM Co., Ltd. All rights reserved. continues, output changes to low voltage and the state is fixed. Table 2. output over voltage protection function Figure 18. OVP Timing chart

TSZ02201-0J2J0D100280-1-2© 2012 ROHM Co., Ltd. All rights reserved. 04.Sep.2012 Rev.001 www.rohm.com TSZ22111・15・001 2-5 Over current protection function The over current protection function has been achieved by limiting the current that flows on high side MOSFET. Output current is limited by cycle-by-cycle. When an abnormal state continues, the output is fixed in a low level. 2-6 Error detection (off latch) release method BD86123A enters the state of off latch when the protection function operates. To release the off latch state, the VIN terminal voltage should be changed to less than UVLO level (=3.8V [typ] ) or, the EN terminal voltage falls below VENL.voltage.

Application Example(s) PGND VIN EN AGND SW SW COMP FB VOUT (3.3V) BD86123AEFJ L 4.7μH VIN (12V) R_UP 7.5kΩ R_DW 2.4kΩ Cin 10.1μF Cout 44μF Ccomp 1500pF Rcomp 33kΩ C_UP 33pF

Figure 21. Application circuit However, the best values of Application Components are different between applications. please confirm actual application and decide values finally.

TSZ02201-0J2J0D100280-1-2© 2012 ROHM Co., Ltd. All rights reserved. important for a good load-transient response and good stability. The example of DC/DC converter application bode plot is shown below. cross over frequency shows good stability but worse response speed. The 1/10 of switching frequency for the cross over frequency shows a good performance at most applications. The compensation resistor RCMP can be on following formula. ROUT by inserting the phase advance. The phase advance can be added by the zero on compensation resistor RCMP and capacitor CCMP. Making Fz= FCRS / 6 gives a first-order estimate of CCMP. confirmation actual application, please decide values finally. Figure 25. Figure 26.

I/O equivalence circuit(s) 5.FB 7,8.SW 3.EN 6.COMP Figure 27. ＥＮＶＩＮ 250ｋΩ 725ｋΩ ＡＧＮＤＶＩＮＣＯＭＰＶＲＥＧ 2ｋΩ 2ｋΩ 0.5ｋΩ 0.5ｋΩ ＡＧＮＤＶＩＮＦＢＡＧＮＤ 20ｋΩ 10ｋΩ 10ｋΩ ＳＷＰＧＮＤＶＩＮ

Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in Figure 26. , a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage to input and output pins.

Figure 28. Example of a Simple Monolithic IC Architecture

TSZ02201-0J2J0D100280-1-2© 2012 ROHM Co., Ltd. All rights reserved. 04.Sep.2012 Rev.001 www.rohm.com TSZ22111・15・001 9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) Thermal shutdown circuit (TSD) This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) EN control speed Chattering happens if standing lowering speed is slow when standing of EN pin is lowered. The reverse current in which the input side and the pressure operation are done from the output side is generated when chattering operates with the output voltage remained, and there is a case to destruction. Please set to stand within 100µs when you control ON/OFF by the EN signal. Status of this document The Japanese version of this document is formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority

Power Dissipation
Ordering Information B D 8 6 1 2 3 A E F J - E 2 Part Number Package EFJ: HTSOP-J8 Packaging and forming specification E2: Embossed tape and reel
Physical Dimension Tape and Reel Information
Marking Diagram(s)(TOP VIEW) HTSOP-J8(TOP VIEW) 86123A Part Number Marking LOT Number 1PIN MARK (Unit : mm) HTSOP-J8 0.08 S 0.08 M S 1.0MAX 0.85±0.05 1.27 0.08±0.08 0.42 +0.05 -0.04 1.05±0.2 0.65±0.15 4°+6° −4° 0.17 +0.05 -0.03 234 568 (MAX 5.25 include BURR) 0.545 (3.2) 4.9±0.1 6.0±0.2 (2.4) 3.9±0.1 1PIN MARK ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tapeTape Quantity Direction of feed The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs Direction of feed Reel 1pin On 70  70  1.6 mm glass epoxy PCB (1) 1-layer board (Backside copper foil area 0 mm 0 mm) (2) 2-layer board (Backside copper foil area 15 mm  15 mm) (3) 2-layer board (Backside copper foil area 70 mm  70 mm) (4) 4-layer board (Backside copper foil area 70 mm  70 mm)

History Date Revision Changes 04.Sep.2012 001 New Release

Product Information

BD86123AEFJ specifications and overview.

Summary

4.5V to 18V, 3A 1ch Synchronous Buck Converter

Description

4.5V to 18V, 3A 1ch Synchronous Buck Converter

Source title BD86123AEFJ Datasheet(PDF) - Rohm

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