BD6563FV-LB ROHM | Alldatasheet
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Technical content
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved.
- General Description BD6563FV-LB is 3-ch gate driver to drive gate of IGBT/MOSFET from 5V input signals. Output signals consist of each high side and low side drive signals in order to make ON/OFF timing control easy. 1 input signal generates 2 output signals which are high side output and low side output signal for 1 channel drive. High side output signal outputs "H" level and high impedance and low side output signal outputs "L" signal and high impedance.
- Features Three-Channel Gate Drivers Separated Turn ON and Turn OFF Output
- Applications Low-side IGBT/MOSFET Gate Drive for DCDC Converter Low-side IGBT/MOSFET Gate Drive for Inverter
- Key Specifications Output-side supply voltage(max.): 30V Input-side supply voltage: 3.0V to 5.5V Output peak current( ≦1us): ±0.6A Input-Output delay time (at VDD=3.3V):380ns(Max.) Input-Output delay time (at VDD=5.0V):345ns(Max.) Operating temperature range: -25 ℃ to +125 ℃
- Package W(Typ.) x D(Typ.) x H(Max.) SSOP-B16 5.00mm x 6.40mm x 1.35mm
- Typical Application Circuit
Figure 1. Typical Application Circuit
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved.
- Pin Configuration
- Pin Description Pin No. Pin Name Function
1 VCC Output-side power supply pin
2 VDD Input-side power supply pin
3 LGND Input-side ground pin
4 IN1 Control input 1 pin
5 IN2 Control input 2 pin
6 IN3 Control input 3 pin
7 LGND Input-side ground pin
8 VCC Output-side power supply pin
9 OUT_L3 Low-side output 3 pin
10 OUT_H3 High-side output 3 pin
11 PGND Output-side ground pin
12 OUT_L2 Low-side output 2 pin
13 OUT_H2 High-side output 2 pin
14 PGND Output-side ground pin
15 OUT_L1 Low-side output 1 pin
16 OUT_H1 High-side output 1 pin
Figure 2. Pin configuration
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved.
- Block Diagram
Figure 3. Block Diagram
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved. 13.JUL.2012 Rev.002 www.rohm.com TSZ22111・15・001
- Absolute Maximum Ratings Parameter Symbol Limits Units Output-side supply voltage V CCMAX 30 V Input-side supply voltage V DDMAX 7 V INX *1 pin input voltage V INXMAX -0.3 to VDD+0.3 V OUT_HX / OUT_LX *1 pin output voltage VOUTHXMAX VOUTLXMAX -0.3 to VCC+0.3 V OUT_HX *1 pin output current (Peak 1us) IOUTHXMAX -0.6* 2 A OUT_LX *1 pin output current (Peak 1us) IOUTLXMAX +0.6* 2 A Power dissipation P d 0.87* 3 W Operating temperature range T OPR -25 to +125 ℃ Storage temperature range T stg -55 to +150 ℃ Junction temperature T jmax +150 ℃ *1 X=1,2,3 *2 Should not exceed Pd and Tj=150 C. *3 Derate above Ta=25 C at a rate of 7.0mW/C. Mounted on a glass epoxy of 70 mm 70 mm 1.6 mm.
- Recommended Operating Ratings Parameter Symbol Min. Max. Units Output-side supply voltage V CC 10 25 V Input-side supply voltage V DD 3.0 5.5 V INX *1 high level input voltage V DD V DD×0.7 - V INX *1 low level input voltage V DD - V DD×0.3 V *1 X=1,2,3
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved. 13.JUL.2012 Rev.002 www.rohm.com TSZ22111・15・001
- Electrical Characteristics (Unless otherwise specified Ta=-25℃ to 125 ℃, V DD=3.0V to 5.5V, VCC=10V to 25V) Parameter Symbol Min. Typ. Max. Unit Conditions INX *1 pull-down resistance R INX 25 50 100 k Ω Output-side circuit current 1 I CC1 - 0.32 1 mA IN1=IN2=IN3=0V Output-side circuit current 2 I CC2 - 0.43 1 mA IN1=IN2=IN3=25kHz, Duty=50% Input-side circuit current 1 I DD1 - 0 10 uA IN1=IN2=IN3=0V Input-side circuit current 2 I DD2 - 25 100 uA IN1=IN2=IN3=25kHz, Duty=50% High level output voltage V OUTHX VCC-2.0 VCC-1.0 VCC-0.4 V I OUTHX=-100mA Low level output voltage V OUTLX 0.15 0.4 1.0 V I OUTLX=100mA Output delay time H 1 t PLHX1 170 250 330 ns V DD =5.0V Output delay time L 1 t PHLX1 185 265 345 ns V DD =5.0V Delay matching 1, OUT_HX and OUT_LX tPLHX1 – tPHLX1 *1 ⊿tPLHX1-PHLX1 -30 -15 0 ns V DD =5.0V Output delay time H 2 t PLHX2 170 250 330 ns V DD =3.3V Output delay time L 2 t PHLX2 220 300 380 ns V DD =3.3V Delay matching 2, OUT_HX and OUT_LX tPLHX2 – tPHLX2 *1 ⊿tPLHX2-PHLX2 -80 -50 0 ns V DD =3.3V Delay matching, OUT_H1,OUT_H2,OUT_H3 t PLHX – tPLHY *1 ⊿tPLH -20 0 20 ns Delay matching, OUT_L1,OUT_L2,OUT_L3 tPHLX – tPHLY *1 ⊿tPHL -20 0 20 ns
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved. 13.JUL.2012 Rev.002 www.rohm.com TSZ22111・15・001
- I/O equivalence circuits Pin No. Name I/O equivalence circuits Function 4, 5, 6 IN1, IN2, IN3 Control input X pin 9, 12, 15 OUT_L1, OUT_L2, OUT_L3 Low-side output X pin 10, 13, 16 OUT_H1, OUT_H2, OUT_H3 High-side output X pin OUT_H1, OUT_H2, OUT_H3 PGND VCC OUT_L1, OUT_L2, OUT_L3 PGND VCC IN1, IN2, IN3 LGND VDD
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved.
- Operational Notes (1) Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus maki ng impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. (2) Connecting the power supply connector backward Connecting of the power supply in reverse polarity c an damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. (3) Power supply Lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and s upply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. (4) GND Potential The potential of LGND pin and PGND pin must be minimum potential in all operating conditions. (5) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (6) Inter-pin shorts and mounting errors When attaching to a printed circuit boar d, pay close attention to the directi on of the IC and displacement. Improper attachment may lead to destruction of the IC. There is also possibility of destruction from short circuits which can be caused by foreign matter entering between outputs or an output and the power supply or GND. (7) Operation in a strong electric field Use caution when using the IC in the pr esence of a strong electromagnetic field as doing so may cause the IC to malfunction. (8) Inspection of the application board During inspection of the application board, if a capacitor is connected to a pin with low impedance there is a possibility that it could cause stress to the IC, therefore an electrical discharge should be performed after each process. Also, as a measure again electrostatic discharge, it should be earthed during the assembly process and special care should be taken during transport or storage. Furt hermore, when connecting to the jig dur ing the inspection process, the power supply should first be turned off and then removed before the inspection. (9) Input terminal of IC Between each element there is a P+ isolatio n for element partition and a P substrate. This P layer and each element’s N layer make up the P-N junction, and various parasitic elements are made up. For example, when the resistance and transistor are connected to the terminal as shown in figure 65, ○When GND>(Terminal A) at the resistance and GND >(Terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. ○Also, when GND>(Terminal B) at the transistor (NPN), The parasitic NPN transistor operates with the N layers of other elements close to the aforementioned parasitic diode. Because of the IC’s structure, the creation of parasitic elements is inevitabl e from the electrical potential relationship. The operation of parasitic elements causes interferenc e in circuit operation, and can lead to malfunction and destruction. Therefore, be careful not to use it in a way which causes the para sitic elements to operate, such as by applying voltage that is lower than the GND (P substrate) to the input terminal. (10) Ground Wiring Patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's refer ence point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern potential of any external components, either. The Japanese version of this document is formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document formal version takes priority Resistor Transistor (NPN) N N N P+ P + P P substrate GND Parasitic element Terminal A N N P+ P+ P P substrate GND Parasitic element Terminal B C B E N GND Terminal A Terminal B Other adjacent elements E B C GND Parasitic element Parasitic element
Figure 30. Pattern Diagram of Parasitic Element
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved. 13.JUL.2012 Rev.002 www.rohm.com TSZ22111・15・001
- Ordering Information B D 6 5 6 3 F V - LBE2 Part Number Package FV : SSOP-B16 Packaging and forming specification E2: Embossed tape and reel
- Physical Dimension Tape and Reel Information
- Marking Diagram SSOP-B16 (TOP VIEW) 1PIN MARK Product Name. LOT No. D6563 (Unit : mm) SSOP-B16 4.4±0.2 6.4±0.31.15±0.1 0.10 0.65 0.3Min. 5.0±0.2 0.22±0.1 0.15±0.1 0.1 ∗ Order quantity needs to be multiple of the minimum quantity. <Tape and Reel information> Embossed carrier tapeTape Quantity Direction of feed The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs Direction of feed Reel 1pin
TSZ02201-0717ABZ00030-1-2© 2012 ROHM Co., Ltd. All rights reserved. 13.JUL.2012 Rev.002 www.rohm.com TSZ22111・15・001
- Revision History Date Revision Changes 05.JUL.2012 001 New Release 13.JUL.2012 002 Page 1 : Change Key Specifications ‘Output peak current’ Page 4 : Change Absolute Maximum Ratings ‘OUT_HX pin output current’ Page 4 : Change Absolute Maximum Ratings ‘OUT_LX pin output current’
Notice - Rev.003 © 2012 ROHM Co., Ltd. All rights reserved. Notice
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Notice - Rev.003 © 2012 ROHM Co., Ltd. All rights reserved.
- Precaution for Mounting / Circuit board design 1) When a highly active halogenous (chlori ne, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification
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