FAN5026_11 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
/square4 Highly Flexible, Dual Synchronous Switching PWM Controller that Includes Modes for: - DDR Mode with InIphase Operation for Reduced Channel Interference - 90° PhaseIshifted, TwoIstage DDR Mode for Reduced Input Ripple - Dual Independent Regulators, 180° Phase Shifted /square4 Complete DDR Memory Power Solution - VTT Tracks V DDQ/2 - VDDQ/2 Buffered Reference Output /square4 Lossless Current Sensing on LowISide MOSFET or Precision OverICurrent Using Sense Resistor /square4 VCC UnderIVoltage Lockout /square4 Wide Input Range: 3V to 16V /square4 Excellent Dynamic Response with Voltage Feedforward and Average CurrentIMode Control /square4 PowerIGood Signal /square4 Supports DDRIII and HSTL /square4 28ILead ThinIShrink SmallIOutline Package
Applications
/square4 DDR V DDQ and V TT Voltage Generation /square4 PC Dual Power Supply /square4 Server DDR Power /square4 Desktop Computer /square4 Graphics Cards
Description
The FAN5026 PWM controller provides high efficiency and regulation for two output voltages adjustable i n the range of 0.9V to 5.5V required to power I/O, chipIs ets, and memory banks in highIperformance computers, setItop boxes, and VGA cards. Synchronous rectification and hysteretic operation at light loa ds contribute to high efficiency over a wide range of loads. Efficiency is enhanced by using MOSFET R DS(ON) as a currentIsense component. Feedforward ramp modulation, averageIcurrent mode control, and internal feedback compensation provide fast response to load transients. OutIofIphase oper ation with 180Idegree phase shift reduces input current ripple. The controller can be transformed into a complete DDR memory power supply solution by activating a designated pin. In DDR Mode, one of th e channels tracks the output voltage of another chann el and provides output current sink and source capabil ity — essential for proper powering of DDR chips. The buffered reference voltage required by this type of memory is also provided. The FAN5026 monitors these outputs and generates separate PGx (power good) signals when the softIstart is completed and the ou tput is within ±10% of the set point. OverIvoltage protection prevents the output voltage from exceeding 120% of the set point. Normal operat ion is automatically restored when overIvoltage conditi ons cease. UnderIvoltage protection latches the chip of f when output drops below 75% of the set value after the softIstart sequence for this output is completed. A n adjustable overIcurrent function monitors the outpu t current by sensing the voltage drop across the lowe r MOSFET. If precision currentIsensing is required, a n external currentIsense resistor may be used. Related Resources /square4 Application Note — AN-6002 Component Calculations and Simulation Tools
Ordering Information
FAN5026MTCX I40 to +85°C 28ILead ThinIShrink SmallIOutline Pack age (TSSOP) Tape and Reel
Figure 3. TSSOP-28
6 BOOT1
BOOT . Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.
23 BOOT2
11 ILIM1 Current Limit 1. A resistor from this pin to GND sets the current limit.
14 VIN
synchronizes the channels 90° out of phase.
16 PG2 /
out of regulation or in a fault condition.
18 ILIM2 /
Current Limit 2 . When not in DDR Mode, a resistor from this pin to G ND sets the current limit. Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2 .
28 VCC
Figure 4. IC Block Diagram
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 5 FAN5026 — Dual DDR / Dual-Output PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not rec ommended. In addition, extended exposure to stresses above th e recommended operating conditions may affect devic e reliability. The absolute maximum ratings are stres s ratings only. Symbol Parameter Min. Max. Unit VCC V CC Supply Voltage 6.5 V VIN V IN Supply Voltage 18 V BOOT, SW, ISNS, HDRV 24 V BOOTx to SWx 6.5 V All Other Pins I0.3 V CC +0.3 V TJ Junction Temperature I40 +150 ºC TSTG Storage Temperature I65 +150 ºC TL Lead Temperature (Soldering,10 Seconds) +300 ºC Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recomme nded operating conditions are specified to ensure optima l performance to the datasheet specifications. Fair child does not recommend exceeding them or designing to Absolute M aximum Ratings. Symbol Parameter Min. Typ. Max. Unit VCC V CC Supply Voltage 4.75 5.00 5.25 V VIN V IN Supply Voltage 16 V TA Ambient Temperature I40 +85 °C ΘJA Thermal Resistance, Junction to Ambient 90 °C/W
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 6 FAN5026 — Dual DDR / Dual-Output PWM Controller
Electrical Characteristics
Recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Power Supplies IVCC V CC Current LDRV, HDRV Open, V SEN Forced Above Regulation Point 2.2 3.0 µA Shutdown (ENI0) 30 µA ISINK V IN Current, Sinking V IN = 15V 10 30 µA ISOURCE V IN Current, Sourcing V IN = 0V I15 I30 µA ISD V IN Current, Shutdown 1 µA VUVLO UVLO Threshold Rising V CC 4.30 4.55 4.75 V Falling 4.10 4.25 4.45 V VUVLOH UVLO Hysteresis 300 mV Oscillator fosc Frequency 255 300 345 KHz VPP Ramp Amplitude VIN = 16V 2 V VIN = 5V 1.25 V VRAMP Ramp Offset 0.5 V G Ramp / V IN Gain VIN ≤ 3V 125 mV/V 1V < V IN < 3V 250 mV/V Reference and Soft-Start VREF Internal Reference Voltage 0.891 0.900 0.909 V ISS SoftIStart Current At Startup 5 µA VSS SoftIStart Complete Threshold 1.5 V PWM Converters Load Regulation I OUTX from 0 to 5A, V IN from 5 to 15V I2 +2 % ISEN V SEN Bias Current 50 80 120 nA UVLO TSD UnderIVoltage Shutdown % of Set Point, 2µs Noise F ilter 70 75 80 % UVLO OverIVoltage Threshold % of Set Point, 2µs Noi se Filter 115 120 125 % ISNS OverICurrent Threshold RILIM = 68.5K Ω, Figure 12 112 140 168 µA Minimum Duty Cycle 10 % Output Drivers HDRV Output Resistance Sourcing 12 15 Ω Sinking 2.4 4.0 LDRV Output Resistance Sourcing 12 15 Ω Sinking 1.2 2.0 Power-Good Output and Control Pins Lower Threshold % of Set Point, 2µs Noise Filter I 86 I94 % Upper Threshold % of Set Point, 2µs Noise Filter 1 08 116 % PG Output Low IPG = 4mA 0.5 V Leakage Current V PULLUP = 5V 1 µA PG2/REF2OUT Voltage DDR = 1, 0 mA < I REF2OUT ≤10mA 99.00 1.01 % VREF2 DDR, EN Inputs VINH Input High 2 V VINL Input Low 0.8 V
Figure 5. DDR Regulator Application Table 1. DDR Regulator BOM
- C6 = 2 X 180µF in parallel.
- Suitable for typical notebook computer applicati on of 4A continuous, 6A peak for V
Section and use AN-6002 for design calculations.
Figure 6. Dual Regulator Application Table 2. Dual Regulator BOM
- If currents above 4A continuous are required, us e single SOI8 packages. For more information, refer to the
Power MOSFET Selection Section and AN-6002 for design calculations.
where t0.9 is in seconds if C SS is in µF. is forced into PWM Mode during softIstart. The following discussion refers to Figure 12. amplitude at maximum load current and line voltage. accuracy is affected if R SENSE is close to 100Ω. multiply I LOAD(MAX) by the inductor ripple current (e.g. its operating die temperature below 125°C. Figure 11. Improving Current-Sensing Accuracy low value resistor (e.g. 10m Ω ).
clamp is disabled and the maximum duty cycle is 87% . Figure 12. Current Limit / Summing Circuits MOSFET has decreased to less than approximately 1V. conduction or shootIthrough. where R O is load resistance; CO is load capacitance.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 13 FAN5026 — Dual DDR / Dual-Output PWM Controller Over-Voltage / Under-Voltage Protection Should the V SNS voltage exceed 120% of V REF (0.9V) due to an upper MOSFET failure or for other reasons , the overIvoltage protection comparator forces LDRV HIGH. This action actively pulls down the output vo ltage and, in the event of the upper MOSFET failure, eventually blows the battery fuse. As soon as the o utput voltage drops below the threshold, the OVP comparat or is disengaged. This OVP scheme provides a ”soft” crowbar function, which accommodates severe load transients and does not invert the output voltage when activated — a common problem for latched OVP schemes. Similarly, if an output shortIcircuit or severe loa d transient causes the output to drop to less than 75 % of the regulation set point, the regulator shuts down. Over-Temperature Protection The chip incorporates an overItemperature protectio n circuit that shuts the chip down if a die temperatu re of about 150°C is reached. Normal operation is restore d at die temperature below 125°C with internal powerIon reset asserted, resulting in a full softIstart cycl e. Design and Component Selection Guidelines As an initial step, define the operating input volt age range, output voltage, and minimum and maximum load currents for the controller. Setting the Output Voltage The internal reference voltage is 0.9V. The output is divided down by a voltage divider to the VSEN pin ( for example, R5 and R6 in Figure 5). The output voltage therefore is: V9 . 0V V9 . 0 OUT − = (10) To minimize noise pickup on this node, keep the resistor to GND (R6) below 2K; for example, R6 at 1.82K Ω . Then choose R5: ( )( ) = K24. 39 . 0 9 . 0VK82. 1 5R OUT (11) For DDR applications converting from 3.3V to 2.5V o r other applications requiring high duty cycles, the duty cycle clamp must be disabled by tying the converter ’s FPWM to GND. When converter’s FPWM is at GND, the converter’s maximum duty cycle is greater than 90%. When using as a DDR converter with 3.3V input, set up the converter for inIphase synchronization b y tying the VIN pin to +5V. Output Inductor Selection The minimum practical output inductor value keeps t he inductor current just on the boundary of continuous conduction at some minimum load. Industry standard practice is to choose the minimum current somewhere from 15% to 35% of the nominal current. At light lo ad, the controller can automatically switch to Hysteret ic Mode to sustain high efficiency. The following equa tions select the proper value of the output filter induct or: ESR V 12I OUT MIN ×=∆ = (12) where ∆I is the inductor ripple current and ∆VOUT is the maximum ripple allowed: IN OUT SW OUTIN V V If VV L ×∆× = (13) for this example, use: KHz300f A5 . 1A6•%25I 5 . 2V,12V SW OUTIN ==∆ (14) therefore: µH4 . 4L ≈ (15) Output Capacitor Selection The output capacitor serves two major functions in a switching power supply. Along with the inductor, it filters the sequence of pulses produced by the switcher and it supplies the load transient currents. The requireme nts are usually dictated by ESR, inductor ripple curren t ( ∆I), and the allowable ripple voltage ( ∆V): I VESR ∆ ∆< (16) In addition, the capacitor’s ESR must be low enough to allow the converter to stay in regulation during a load step. The ripple voltage due to ESR for the convert er in Figure 6 is 120mV PP. Some additional ripple appears due to the capacitance value itself: SWOUT f8C IV ×× ∆=∆ (17) which is only about 1.5mV for the converter in Figu re 6 and can be ignored. The capacitor must also be rated to withstand the R MS current, which is approximately 0.3 X ( ∆I), or about 400mA, for the converter in Figure 6. HighIfrequenc y decoupling capacitors should be placed as close to the loads as physically possible Input Capacitor Selection The input capacitor should be selected by its rippl e current rating.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 15 FAN5026 — Dual DDR / Dual-Output PWM Controller GATEDRIVER SPCC )SW(G DRIVER )SW(G RR VV Q I Q ts (28) Most MOSFET vendors specify Q GD and Q GS. Q G(SW) can be determined as: THGSGD)SW(G QQQQ −+= (29) where Q TH is the gate charge required to get the MOSFET to it’s threshold (V TH ). For the highIside MOSFET, V DS = V IN , which can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET’s gate power (PGATE ) in calculating the power dissipation required for the FAN5026: SWCCGATEG fVQP ××= (30) where Q G is the total gate charge to reach V CC . Low-Side Losses Q2, however, switches on or off with its parallel Schottky diode conducting, therefore V DS ≈ 0.5V. Since PSW is proportional to V DS , Q2’s switching losses are negligible and Q2 is selected based on R DS(ON) only. Conduction losses for Q2 are given by: ( ) )ON(DSOUTCOND RID1P 2 ××−= (31) where R DS(ON) is the R DS(ON) of the MOSFET at the highest operating junction temperature, and: IN OUT V V D = (32) is the minimum duty cycle for the converter. Since D MIN < 20% for portable computers, (1ID) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (P D(MAX) ) is a function of the maximum allowable die temperature of the lowIsi de MOSFET; the ΘJA, and the maximum allowable ambient temperature rise: JA )MAX(A)MAX( J )MAX(D TT P Θ = (33) ΘJA depends primarily on the amount of PCB area that can be devoted to heat sinking (see Application Note AN-1029, Maximum Power Enhancement Techniques for SO-8 Power MOSFETs for SO-8 MOSFET thermal information) Layout Considerations Switching converters, even during normal operation, produce short pulses of current that could cause substantial ringing and be a source of EMI if layou t constraints are not observed. There are two sets of critical components in a DCID C converter. The switching power components process large amounts of energy at high rates and are noise generators. The lowIpower components responsible fo r bias and feedback functions are sensitive to noise. A multiIlayer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedica te another solid layer as a power plane and break this plane into smaller islands of common voltage levels . Notice all the nodes that are subjected to highIdV/ dt voltage swing; such as SW, HDRV, and LDRV. All surrounding circuitry tends to couple the signals f rom these nodes through stray capacitance. Do not overs ize copper traces connected to these nodes. Do not plac e traces connected to the feedback components adjacen t to these traces. It is not recommended to use highI density interconnect systems, or microIvias, on the se signals. The use of blind or buried vias should be limited to the lowIcurrent signals only. The use of normal thermal vias is at the discretion of the des igner. Keep the wiring traces from the IC to the MOSFET ga te and source as short as possible and capable of handling peak currents of 2A. Minimize the area wit hin the gateIsource path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components, like the softIsta rt capacitor and currentIsense resistors, as close as possible to the respective pins of the IC. The FAN5026 utilizes advanced packaging technology with lead pitch of 0.6mm. HighIperformance analog semiconductors utilizing narrow lead spacing may require special considerations in design and manufacturing. It is critical to maintain proper cleanliness of the area surrounding these devices.
Figure 18. 28-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide specifically the warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/.
© 2005 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5026 • Rev. 1.0.8 17 FAN5026 — Dual DDR / Dual-Output PWM Controller