BALFHB-WL-05D3 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 13
Technical content
Features
- QFN STM32WL sub-GHz wireless microcontrollers impedance matched balun and Tx harmonics filter
- Optimized for QFN STM32WL sub-GHz wireless microcontrollers in low power mode and dedicated to 4-layers PCB
- 50 Ω nominal input / conjugate matched balun to QFN STM32WL
- 50 Ω nominal impedance on antenna side Tx and Rx
- Deep Tx rejection harmonic filter
- Low insertion loss
- Small footprint
- Low profile ≤ 630 μm after reflow
- High RF performance
- RF BOM and area reduction
- ECOPACK2 compliant component
Applications
- STM32WL sub-GHz wireless microcontrollers
- LPWAN-compliant radio solution, enabling the following modulations: LoRa®, (G)FSK, (G)MSK, and BPSK
Description
STMicroelectronics BALFHB-WL-05D3 is an ultra-miniature balun. This device integrates a matching network, balun, and harmonics filter. Matching impedance has been customized for the STM32WL sub-GHz wireless microcontrollers. It is using STMicroelectronics IPD technology on a nonconductive glass substrate, which optimizes RF performances. Product status BALFHB-WL-05D3 50 Ω nominal input / conjugate match balun to QFN-4L STM32WL in low power mode, 862-928 MHz with integrated harmonic filter BALFHB-WL-05D3 Datasheet DS14104 - Rev 2 - December 2022 For further information contact your local STMicroelectronics sales office.
1 Characteristics
Table 1. Absolute maximum ratings (Tamb = 25 °C) Table 2. Impedances (Tamb = 25 °C) Table 3. Electrical characteristics and RF performances (Tamb = 25 °C)
1.1 RF measurements (Rx balun)
Figure 1. Insertion loss (dB) Figure 2. Return loss on antenna (dB)
0 RL_RX_ANT
Figure 3. Amplitude imbalance (dB) Figure 4. Phase imbalance (°)
1.2 RF measurements (Tx filter)
Figure 5. Transmission wide band with harmonics Figure 6. Insertion loss (dB) Figure 7. Return loss on antenna (dB)
2 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
2.1 CSPG 8 bumps package information
Figure 8. CSPG 8 bumps package outline (bottom view - bumps up) (in µm) Table 4. CSPG 8 bumps dimensions (in µm)
Package information
2.2 CSPG 8 bumps packing information
Figure 9. Marking Figure 10. Top view Table 5. Pads description top view (pads down)
Figure 11. Tape and reel outline Table 6. Tape and reel mechanical data
- AN2348 Flip-Chip: “Package description and recommendations for use” BALFHB-WL-05D3 CSPG 8 bumps packing information DS14104 - Rev 2 page 7/13
3 PCB assembly recommendations
3.1 Land pattern
Figure 12. QFN-4L PCB recommended land pattern Layout example using STM32WL in QFN package / 4 layers PCB for low power mode. Figure 13. QFN-4L PCB stack-up recommendations
3.2 Stencil opening design
Figure 14. Footprint - 3 mils stencil -non solder mask Figure 15. Footprint - 3 mils stencil - solder mask defined
3.3 Solder paste
- Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
- “No clean” solder paste is recommended.
- Offers a high tack force to resist component movement during high speed.
- Use solder paste with fine particles: powder particle size 20-38 µm.
3.4 Placement
- Manual positioning is not recommended.
- It is recommended to use the lead recognition capabilities of the placement system, not the outline
- Standard tolerance of ±0.05 mm is recommended.
- 1.0 N placement force is recommended. Too much placement force can lead to squeezed out solder paste
and solder paste that could cause open solder joints or badly centered packages.
- To improve the package placement accuracy, a bottom side optical control should be performed with a high
- For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder
paste printing, pick and place and reflow soldering by using optimized tools.
3.5 PCB design preference
- To control the solder paste amount, the closed via is recommended instead of open vias.
- The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is
recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away.
3.6 Reflow profile
Figure 16. ST ECOPACK® recommended soldering reflow profile for PCB mounting Note: Minimize air convection currents in the reflow oven to avoid component movement.
- AN2348 Flip-Chip: “Package description and recommendations for use” BALFHB-WL-05D3 Reflow profile DS14104 - Rev 2 page 10/13
4 Ordering information
Table 7. Ordering information
Ordering information
DS14104 - Rev 2 page 11/13
Revision history
Table 8. Document revision history 14-Oct-2022 1 Initial release. 21-Dec-2022 2 Updated Table 1. Absolute maximum ratings (Tamb = 25 °C).
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