B58031 TDK | Alldatasheet

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Capacitors for fast-switching semiconductors Series/Type: Low profile (LP) series Ordering code: B58031* Date: 2017-02-15 Version: 5.0  EPCOS AG 2016. Reproduction, publication and dissemination of this publication, enclosures hereto and the information contained therein without EPCOS' prior express consent is prohibited. EPCOS AG is a TDK Group Company. Content of header bars 1 and 2 of data sheet will be automatically entered in headers and footers! Please fill in the table and then change the color to "white". This ensures that the table disappears (invisible) for the customer PDF. Don't change formatting when entering or pasting text in the table and don't add any cell or line in and to it! Identification/Classification 1 (header 1 + top left bar): CeraLink™ Identification/Classification 2 (header 2 + bottom left header bar): Capacitor for fast-switching semiconductors Ordering code: (top right header bar) B58031* Series/Type: (bottom right header bar) Low profile (LP) series Preliminary data (optional): Department: PPD MT IC Date: 2017-02-15 Version: 5.0 Prepared by: Javier Martinez Signed by : Monika Stadlober, Axel Pecina

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 2 of 24 Important notes at the end of this document.

Applications

  • Power converters and inverters
  • DC link/ snubber capacitor for power converters and inverters

Features

  • High ripple current capability
  • High temperature robustness
  • Low equivalent serial inductance (ESL)
  • Low equivalent serial resistance (ESR)
  • Low power loss
  • Low dielectric absorption
  • Optimized for high frequencies up to several MHz
  • Increasing capacitance with DC bias up to operating voltage
  • High capacitance density
  • Minimized dielectric loss at high temperatures
  • Qualification based on AEC-Q200 rev. D
  • Suitable for reflow soldering only Construction
  • RoHS-compatible PLZT ceramic (lead lanthanum zirconium titanate)
  • Copper inner electrodes
  • Silver outer electrodes
  • Silver coated copper-invar lead frame General technical data Dissipation factor tan𝛿 < 0.02 Insulation resistance Rins, typ > 1 GΩ Operating device temperature Tdevice -40 … +150 °C Weight of device approx.. 1.3 g

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 3 of 24 Important notes at the end of this document. Electrical specifications and ordering codes Lead type Vpk, max V VR V Vop V Cnom, typ µF Ceff, typ µF µF Ordering code L-style 650 500 400 1 0.6 0.35 ±20% B58031I5105M062 J-style 650 500 400 1 0.6 0.35 ±20% B58031U5105M062 L-style 1000 700 600 0.5 0.25 0.14 ±20% B58031I7504M062 J-style 1000 700 600 0.5 0.25 0.14 ±20% B58031U7504M062 L-style 1300 900 800 0.25 0.13 0.07 ±20% B58031I9254M062 J-style 1300 900 800 0.25 0.13 0.07 ±20% B58031U9254M062 Typical values ESR

0 VDC,

0.5 VRMS,

25 °C, 1 MHz ESR 25 °C, 1 kHz ESL Iop 100 kHz TA = 85 °C Iop 100 kHz TA = 105 °C mΩ Ω nH ARMS ARMS VR 500 V 12 3 2.5 11.4 9.7 VR 700 V 29 9 2.5 7.1 6.5 VR 900 V 45 14 2.5 5.1 4.6 1) Normal operating current without forced cooling at Tdevice = 150 °C. Higher values permissible at reduced lifetime. Packaging All types are delivered on 330-mm reel with 1000 pieces.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 4 of 24 Important notes at the end of this document. Dimensional drawings L-style Recommended solder pads Dimensions in mm J-style

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 5 of 24 Important notes at the end of this document. Polarity VR = 500 V L-style J-style Polarity VR = 700 V L-style J-style Polarity VR = 900 V L-style J-style Marking of components Manufacturer’s logo CeraLink™ type Nominal capacitance Rated voltage

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 6 of 24 Important notes at the end of this document. Typical characteristics as a function of temperature and voltage VR = 500 V (VAC = 0.5 VRMS, frequency = 1 kHz) All given temperatures are device temperatures. The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100% values correspond to Ceff,typ and tan δ which are given on page 2 and 3 of this data sheet. 5004003002001000 120 110 100 Voltage [VDC] Capacitance [%] -25 125 T [°C] 1501251007550250-25-50 120 110 100 Temperature [°C] Capacitance [%] 400 500 [VDC] Bias 5004003002001000 600 500 400 300 200 100 Voltage [VDC] Dissipation factor [%] -25 125 T [°C] 1501251007550250-25-50 600 500 400 300 200 100 Temperature [°C] Dissipation factor [%] 400 500 [VDC] Bias 5004003002001000 500 400 300 200 100 Voltage [VDC] ESR [%] -25 125 T [°C] 1501251007550250-25-50 600 500 400 300 200 100 Temperature [°C] ESR [%] 400 500 [VDC] Bias

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 7 of 24 Important notes at the end of this document. Typical capacitance values as a function of voltage VR = 500 V 5004003002001000 225 200 175 150 125 100 Voltage [VDC] Capacitance [%] large signal small signal Variable Large signal capacitance: Quasistatic (slow variation of the voltage), 25 °C The nominal capacitance is defined as the large signal capacitance at Vop. See glossary for further information. Small signal capacitance:

0.5 VRMS, 1 kHz, 25 °C

The effective capacitance is defined as the small signal capacitance at Vop. Typical impedance and ESR as a function of frequency VR = 500 V 100000001000000100000100001000 1000 100 0.1 0.01 0.001 Frequency [Hz] |Z|, ESR [Ohm] Z ESR Variable VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C Typical permissible current as a function of frequency VR = 500 V 100806040200 Frequency [kHz] Normal Operation Current [Arms] 85.0 105.0 Tamb Measurement performed at Vop. The values correspond to a device temperature of 150 °C. No forced cooling was used. Aging The capacitance has an aging behavior which shows a decrease of capacitance with time. The typical aging rate is about 2.5% per logarithmic decade in hours.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 8 of 24 Important notes at the end of this document. Typical characteristics as a function of temperature and voltage VR = 700 V (VAC = 0.5 VRMS, frequency = 1 kHz) All given temperatures are device temperatures. The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100% values correspond to Ceff, typ and tan δ which are given on page 2 and 3 of this data sheet. 7006005004003002001000 130 120 110 100 Voltage [VDC] Capacitance [%] -25 125 T/°C 150100500-50 140 120 100 Temperature [°C] Capacitance [%] 600 700 [VDC] Bias 7006005004003002001000 600 500 400 300 200 100 Voltage [VDC] Dissipation factor [%] -25 125 T/°C 150100500-50 600 500 400 300 200 100 Temperature [°C] Dissipation factor [%] 600 700 [VDC] Bias 7006005004003002001000 500 400 300 200 100 Voltage [VDC] ESR [%] -25 125 T/°C 150100500-50 600 500 400 300 200 100 Temperature [°C] ESR [%] 600 700 [VDC] Bias

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 9 of 24 Important notes at the end of this document. Typical capacitance values as a function of voltage VR = 700 V 7006005004003002001000 200 175 150 125 100 Voltage [VDC] Capacitance [%] large signal * V small signal * Bias [V] Variable Large signal capacitance: Quasistatic (slow variation of the voltage), 25 °C The nominal capacitance is defined as the large signal capacitance at Vop. See glossary for further information. Small signal capacitance: The effective capacitance is defined as the small signal capacitance at Vop. Typical impedance and ESR as a function of frequency VR = 700 V 10000000100000010000010000 100 0.1 0.01 0.001 Frequency [Hz] |Z|, ESR [Ohm] |Z| [Ohm] ESR [Ohm] Variable VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C Typical permissible current as a function of frequency VR = 700 V 100806040200 Frequency [kHz] Normal Operation Current [Arms] 85.0 105.0 Tamb Scatterplot of Oven Temp : 85.0; Oven Temp : 106.0 vs Freq [kHz] Measurement performed at Vop. The values correspond to a device temperature of 150 °C. No forced cooling was used. Aging The capacitance has an aging behavior which shows a decrease of capacitance with time. The typical aging rate is about 2.5% per logarithmic decade in hours.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 10 of 24 Important notes at the end of this document. Typical characteristics as a function of temperature and voltage VR = 900 V (VAC = 0.5 VRMS, frequency = 1 kHz) All given temperatures are device temperatures. The curves show the relative changes of the capacitance, dissipation factor and ESR. The 100% values correspond to Ceff, typ and tan δ which are given on page 2 and 3 of this data sheet. 9008007006005004003002001000 140 120 100 Voltage [VDC] Capacitance [%] -25 125 T/°C 150100500-50 130 120 110 100 Temperature [°C] Capacitance [%] 800 900 Bias [V] 9008007006005004003002001000 700 600 500 400 300 200 100 Voltage [VDC] Dissipation Factor [%] -25 125 T/°C 150100500-50 700 600 500 400 300 200 100 Temperature [°C] Dissipation Factor [%] 800 900 Bias [V] 9008007006005004003002001000 500 400 300 200 100 Voltage [VDC] ESR [%] -25 125 T/°C 150100500-50 600 500 400 300 200 100 Temperature [°C] ESR [%] 800 900 Bias [V]

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 11 of 24 Important notes at the end of this document. Typical capacitance values as a function of voltage VR = 900 V 9008007006005004003002001000 200 175 150 125 100 Voltage [VDC] Capacitance [%] large signal small signal Variable Large signal capacitance: Quasistatic (slow variation of the voltage), 25 °C The nominal capacitance is defined as the large signal capacitance at Vop. See glossary for further information. Small signal capacitance: The effective capacitance is defined as the small signal capacitance at Vop. Typical impedance and ESR as a function of frequency VR = 900 V 100000001000000100000100001000 10000 1000 100 0.1 0.01 Frequency [Hz] |Z|, ESR [Ohm] |Z| [Ohm] ESR [Ohm] Variable VDC = 0 V, VAC = 0.5 VRMS, Tdevice = 25 °C Typical permissible current as a function of frequency VR = 900 V 100806040200 Frequency [kHz] Normal Operation Current [Arms] 85.0 105 Tamb Measurement performed at Vop. The values correspond to a device temperature of 150 °C. No active cooling was used. Aging The capacitance has an aging behavior which shows a decrease of capacitance with time. The typical aging rate is about 2.5% per logarithmic decade in hours.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 12 of 24 Important notes at the end of this document. Reliability A. Preconditioning:  Reflow solder the capacitor on a PCB using the recommended soldering profile  Check of external appearance  Measurement of electrical parameters Rins, C0, tan δ o Apply Vpk,max for 7 seconds and measure Rins at room temperature: Isolation resistance (@ Vpk,max, 7 s, 25 °C) Rins > 100 MΩ o Measure C0 and tan δ within 10 minutes to 1 hour afterwards: Initial capacitance (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C) Dissipation factor (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C) B. Performance of a specific reliability test. C. After performing a specific test:  Check the external appearance again  Repeat the measurement of the electrical parameters o Apply Vpk,max for 7 seconds and measure Rins at room temperature: Isolation resistance (@ Vpk,max, 7 s, 25 °C) Rins > 10 MΩ o Measure C and tan δ: Change of initial capacitance (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C) | Δ C / C0 | < 15% o Dissipation factor (@ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C) tan δ < 0.05 Test Standard Test conditions Criteria External appearance Visual inspection with magnifying glass No defects that might affect performance High temperature operating life MIL-STD-202, method 108 150 °C, VR, 1000 hours No mechanical damage | Δ C / C0 |, tan δ and Rins within defined limits Biased humidity MIL-STD-202, method 103 85 °C, 85% rel. hum., VR, 1000 hours No mechanical damage | Δ C / C0 |, tan δ and Rins within defined limits Temperature shock IEC 60384-9, 4.8 -55 °C to +150 °C 20 seconds transfer time 15 minutes dwell time 1000 cycles No mechanical damage | Δ C / C0 |, tan δ and Rins within defined limits Terminal strength test AEC-Q200-005 Apply a force of 17.7 N for 60 seconds No detaching of termination. No rupture of ceramic | Δ C / C0 |, tan δ and Rins within defined limits

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 13 of 24 Important notes at the end of this document. Test Standard Test conditions Criteria Tensile strength test (unsoldered) Apply a force of 10 N in the shown direction. Ceramic body is clamped : No detaching of termination. No rupture of ceramic | Δ C / C0 |, tan δ and Rins within defined limits Board flex AEC-Q200-005 Bending of 2 mm for 60 seconds Dimensions in mm No mechanical damage | Δ C / C0 |, tan δ and Rins within defined limits Vibration MIL-STD-202, method 204 5 g/ 20 min, 12 cycles, 3 axis

10 Hz to 2000 Hz

| Δ C / C0 |, tan δ and Rins within defined limits Mechanical shock MIL-STD-202, method 213 Acceleration 400 m/s² Half sine pulse duration 6 milliseconds 4000 bumps No mechanical damage | Δ C / C0 |, tan δ and Rins within defined limits Reflow test 3 times recommended reflow soldering profile No mechanical damage Proper solder coating of contact areas | Δ C / C0 |, tan δ and Rins within defined limits Leaching test (lead frame only) MIL-STD-202, method 210, condition B Dip test of contact areas in solder bath (260 °C for 10 seconds) No damage of lead frame silver coating Solderability (lead frame only) J-STD-002, method A @ 235 °C, category 3 Dip test of contact areas in solder bath (235 °C for 5 ± 0.5 seconds) > 95% wettability of lead frame Resistance to solvent Dipping and cleaning with isopropanol Marking must be legible | Δ C / C0 |, tan δ and Rins within defined limits Geometry Using a caliper Within specified tolerance in the chapter construction

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 14 of 24 Important notes at the end of this document. Packaging The CeraLink™ will be delivered in a blister tape (taping to IEC 60286-3). Blister tape for L-style terminal Blister tape for J-style terminal

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 15 of 24 Important notes at the end of this document. Part orientation for L-style terminal Part orientation for J-style terminal Taping information Trailer: There is a minimum of 160 mm of carrier tape with empty compartments and sealed by the cover tape. Leader: There is a minimum of 400 mm of cover tape, which includes at least 100 mm of carrier tape with empty compartments. Dimensions in mm Fixing peeling strength (top tape) The peeling strength is 0.1 … 1.3 N.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 16 of 24 Important notes at the end of this document. Reel packing Dimensions in mm L-style terminal J-style terminal A 330 ±2 330 ±2 B 100 ±1 62 ±1 D 20.2 min. 19.1 min. W 24.2 +2 16.4 +2

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 17 of 24 Important notes at the end of this document. Recommended reflow soldering profile Profile feature SAC, Sn95.5Ag3.8Cu0.7 @ N2 atmosphere Preheat and soak - Temperature min - Temperature max - Time Tsmin Tsmax tsmin to tsmax 150 °C 200 °C 60 … 120 seconds Average ramp-up rate TL to Tp 3 °C/ second max. Liquidus temperature Time at liquidus temperature TL tL 217 °C 60 … 150 seconds Peak package body temperature Tp 1) 245 °C … 260 °C max.2) Time (tp)3) within 5 °C of specified classification temperature (Tc) 30 seconds3) Average ramp-down rate Tp to TL 6 °C/ second max. Time 25 °C to peak temperature maximum 8 minutes 1) Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum. 2) Depending on package thickness. For details please refer to JEDEC J-STD-020D. 3) Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Notes: All temperatures refer to topside of the package, measured on the package body surface. Max. number of reflow cycles: 3 After the soldering process, the capacitance is lowered. Applying VR to the device will re-establish the capacitance. The components are suitable for reflow soldering to JEDEC J-STD-020D.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 18 of 24 Important notes at the end of this document. General technical information Storage  Only store CeraLink™ capacitors in their original packaging. Do not open the package prior to processing.  Storage conditions in original packaging: temperature −25 °C to +45 °C, relative humidity ≤ 75% annual average, maximum 95%, dew precipitation is inadmissible.  Do not store CeraLink™ capacitors where they are exposed to heat or direct sunlight. Otherwise the packaging material may be deformed or CeraLink™ may stick together, causing problems during mounting.  Avoid contamination of the CeraLink™ surface during storage, handling and processing.  Avoid storing CeraLink™ devices in harmful environments where they are exposed to corrosive gases (e.g. SOx, Cl).  Use CeraLink™ as soon as possible after opening factory seals such as polyvinyl-sealed packages.  Solder CeraLink™ components within 6 months after shipment from EPCOS. Handling  Do not drop CeraLink™ components or allow them to be chipped.  Do not touch CeraLink™ with your bare hands - gloves are recommended.  Avoid contamination of the CeraLink™ surface during handling.  The CeraLink™ was tested to withstand the board flex test defined in the AEC-Q200 rev. D, method 005.  The CeraLink™ uses copper lead frames to prevent mechanical stress to the ceramic. Too much bending causes open mode. Avoid high mechanical stress like twisting after soldering on a PCB.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 19 of 24 Important notes at the end of this document. Mounting  Do not subject CeraLink™ devices to mechanical stress when encapsulating them with sealing material or overmolding with plastic material. Encapsulation may lead to worse heat dissipation too. Please ask for further information.  Do not scratch the electrodes before, during or after the mounting process.  Make sure contacts and housings used for assembly with CeraLink™ components are clean before mounting.  The surface temperature of an operating CeraLink™ can be higher than the ambient temperature. Ensure t hat adjacent components are placed at a sufficient distance from a CeraLink™ to allow proper cooling.  Avoid contamination of the CeraLink™ surface during processing. Soldering  The use of mild, non-activated fluxes for soldering is recommended, as well as proper cleaning of the PCB.  Complete removal of flux is recommended to avoid surface contamination that can result in an instable and/or high leakage current.  Use resin-type or non-activated flux.  Bear in mind that insufficient preheating may cause ceramic cracks.  Rapid cooling by dipping in solvent is not recommended, otherwise a component may crack.  Excessive usage of solder paste can reduce the mechanical robustness of the device, whereas insufficient solder may cause the CeraLink™ to detach from the PCB. Use an adequate amount of solder paste, but on the landing pads only.  If an unsuitable cleaning fluid is used, flux residue or foreign particles may stick to the CeraLink™ surface and deteriorate its insulation resistance. Insufficient or improper cleaning of the CeraLink™ may cause damage to the component.  Excessive washing like ultrasonic cleaning, can affect the connection between the ceramic chip and the outer electrode. To avoid this, we give the following recommendation: o Power: 20 W/l max. o Frequency: 40 kHz max. o Washing time: 5 minutes max.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 20 of 24 Important notes at the end of this document. Glossary Initial capacitance C0: Is the value at the origin of the hysteresis without any applied direct voltage. Effective capacitance Ceff: Occurs at Vop and is measured with an applied ripple voltage of 0.5 VRMS and 1 kHz. The CeraLink™ is designed to have its highest capacitance value at the operating voltage Vop. Nominal capacitance Cnom: Is the value derived by the tangent of the mean hysteresis as the derivation of the mean hysteresis is dQ/dV ~ C.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 21 of 24 Important notes at the end of this document. Symbols and terms AC Alternating current C0 Initial capacitance @ 0 VDC, 0.5 VRMS, 1 kHz, 25 °C Ceff,typ Typical effective capacitance @ Vop, 0.5 VRMS, 1 kHz, 25 °C Cnom,typ Typical nominal capacitance @ Vop, quasistatic, 25 °C. See glossary (page 20) for definition of the nominal capacitance DC Direct current ESL Equivalent serial inductance ESR Equivalent serial resistance Iop Operating ripple current, root mean square value of sinusoidal AC current LP Low profile PCB Printed circuit board PLZT Lead lanthanum zirconium titanate Rins Insulation resistance Rins, typ Insulation resistance @ Vop, t > 240 s, 25 °C SAC Tin silver copper alloy; lead-free solder paste TA Ambient temperature tan δ Dissipation factor @ 0 Vdc, 0.5 Vrms 1 kHz, 25°C Tdevice Device temperature. Tdevice = TA + ΔT (ΔT defines the self-heating of the device due to applied current). Vop Operating voltage VR Rated voltage VRMS Root mean square value of sinusoidal AC voltage Vpk,max Maximum peak operating voltage @ Vpk,max, 25 °C, 7 s ΔT Increase of temperature during operation

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 22 of 24 Important notes at the end of this document. Cautions and warnings General Not for use in resonant circuits, where a voltage of alternating polarity occurs. Not for AC applications. Consult your EPCOS representative for further details. If used in snubber circuits, ensure that the sum of all voltages remains at the same polarity. Some parts of this publication contain statements about the suitability of our CeraLink™ components for certain areas of application, including recommendations about incorporation/design-in of these products into customer applications. The statements are based on our knowledge of typical requirements often made of our CeraLink™ devices in the particular areas. We nevertheless expressly point out that such statements cannot be regarded as binding statements about the suitability of our CeraLink™ components for a particular customer application. As a rule, EPCOS is either unfamiliar with individual customer applications or less familiar with them than the customers themselves. For these reasons, it is always incumbent on the customer to check and decide whether the CeraLink™ devices with the properties described in the product specification are suitable for use in a particular customer application.  Do not use EPCOS CeraLink™ components for purposes not identified in our specifications.  Ensure the suitability of a CeraLink™ in particular by testing it for reliability during design-in. Always evaluate a CeraLink™ component under worst-case conditions.  Pay special attention to the reliability of CeraLink™ devices intended for use in safety-critical applications (e.g. medical equipment, automotive, spacecraft, nuclear power plant). Design notes  Consider derating at higher operating temperatures. As a rule, lower temperatures and voltages increase the life time of CeraLink™ devices.  If steep surge current edges are to be expected, make sure your design is as low-inductive as possible.  In some cases the malfunctioning of passive electronic components or failure before the end of their service life cannot be completely ruled out in the current state of the art, even if they are operated as specified. In applications requiring a very high level of operational safety and especially when the malfunction or failure of a passive electronic component could endanger human life or health (e.g. in accident prevention, life-saving systems, or automotive battery line applications such as clamp 30), ensure by suitable design of the application or other measures (e.g. installation of protective circuitry, fuse or redundancy) that no injury or damage is sustained by third parties in the event of such a malfunction or failure.  Specified values only apply to CeraLink™ components that have not been subject to prior electrical, mechanical or thermal damage. The use of CeraLink™ devices in line-to-ground applications is therefore not advisable, and it is only allowed together with safety countermeasures such as thermal fuses.

CeraLink™ B58031* Capacitor for fast-switching semiconductors Low profile (LP) series PPD MT IC 2017-02-15 Please read Cautions and warnings and Page 23 of 24 Important notes at the end of this document. Operation  Use CeraLink™ only within the specified operating temperature range.  Use CeraLink™ only within specified voltage and current ranges.  The CeraLink has to be operated in a dry atmosphere, which must not contain any additional chemical vapors or substances.  Environmental conditions must not harm the CeraLink™. Use the capacitors under normal atmospheric conditions only. A reduction of the oxygen partial pressure to below 1 mbar is not permissible.  Prevent a CeraLink™ from contacting liquids and solvents.  Avoid dewing and condensation.  During operation, the CeraLink™ can produce audible noise due to its piezoelectric characteristic.  EPCOS CeraLink™ components are mainly designed for encased applications. Under all circumstances avoid exposure to: o direct sunlight o rain or condensation o steam, saline spray o corrosive gases o atmosphere with reduced oxygen content This listing does not claim to be complete, but merely reflects the experience of EPCOS AG. Display of ordering codes for EPCOS products The ordering code for one and the same EPCOS product can be represented differently in data sheets, data books, other publications, on the EPCOS website, or in order-related documents such as shipping notes, order confirmations and product labels. The varying representations of the ordering codes are due to different processes employed and do not affect the specifications of the respective products. Detailed information can be found on the Internet under www.epcos.com/orderingcodes

The following applies to all products named in this publication: 1. Some parts of this publication contain statements about the suitability of our products for certain areas of application . These statements are based on our knowledge of typical requirements that are often placed on our products in the are as of application concerned. We nevertheless expressly point out that such statements cannot be regarded as binding statements about the suitability of our products for a particular customer application. As a rule, EPCOS is either unfamiliar with individua l customer applications or less familiar with them than the customers themselves. For these reasons, it is always ultimately incumbent on the customer to check and decide whether an EPCOS product with the properties described in the product specification is suitable for use in a particular customer application. 2. We also point out that in individual cases, a malfunction of electronic components or failure before the end of their usual service life cannot be completely ruled out in the current state of the art, even if they are operated as specified. In customer applications requiring a very high level of operational safety and especially in customer applications in which the malfunction or failure of a n electronic component could endanger human life or health (e.g. in accident prevention or life-saving systems), it must therefore be ensured by means of suitable design of the customer application or other action taken by the customer (e.g. installation of protective circuitry or redundancy) that no injury or damage is sustained by third parties in the event of malfunction or failure of an electronic component. 3. The warnings, cautions and product-specific notes must be observed. 4. In order to satisfy certain technical requirements, some of the products described in t his publication may contain substances subject to restrictions in certain jurisdictions (e.g. because they are classed as hazardous). Useful information on this will be found in our Material Data Sheets on the Internet (www.epcos.com/material). Should you have any more detailed questions, please contact our sales offices. 5. We constantly strive to improve our products. Consequently, the products described in this publication may change from time to time . The same is true of the corresponding product specifications. Please check therefore to what extent product descriptions and specifications contained in this publication are still applicable before or when you place an order. We also reserve the right to discontinue production and delivery of products. Consequently, we cannot guarantee that all products named in this publication will always be available. The aforementioned does not apply in the case of individual agreements deviating from the foregoing for customer-specific products. 6. Unless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms of Delivery for Products and Services in the Electrical Industry” published by the German Electrical and Electronics Industry Association (ZVEI). 7. The trade names EPCOS, CeraDiode, CeraLink, CeraPad, CeraPlas, CSMP, CSSP, CTVS, DeltaCap, DigiSiMic, DSSP, ExoCore, FilterCap, FormFit, LeaXield, MAGicCharge, MiniBlue, MiniCell, MKD, MKK, MotorCap, PCC, PhaseCap, PhaseCube, PhaseMod, PhiCap, PQSine, SIFERRIT, SIFI, SIKOREL, SilverCap, SIMDAD, SiMic, SIMID, SineFormer, SIOV, SIP5D, SIP5K, TFAP, ThermoFuse, WindCap are trademarks registered or pending in Europe and in other countries. Further information will be found on the Internet at www.epcos.com/trademarks.