DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Page No. : 1/11 RS6515 2A, 20V, 400KHz DC/DC Asynchronous Step‐Down Converter General Description The RS6515 is a high‐efficiency asynchronous step‐down DC/DC converter that can deliver up to 2A output current from 4.75V to 20V input supply. The RS6515's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Cycle‐by‐cy cle current limit provides protection against shorted outputs and soft‐start eliminates input current surge during start‐up. The RS6515 also provides output under voltage protection and thermal shutdown protection. The low current (<30μA) shutdown mode provides output disconnection, enabling easy power management in battery‐powered systems. Features Applications

  • 2A Output Current
  • Up to 93% Efficiency
  • Integrated 100mΩ Power MOSFET Switches
  • Fixed 385KHz Frequency
  • Cycle‐by‐Cycle Over Current Protection
  • Thermal Shutdown function
  • Wide 4.75V to 21V Operating Input Range
  • Output Adjustable from 0.92V to 18V
  • Programmable Under Voltage Lockout
  • Available in an MSOP‐10(EP) Package
  • RoHS Compliant an d 100% Lead (Pb)‐Free and Green (Halogen Free with Commercial Standard)
  • PC Motherboard, Graphic Card
  • LCD Monitor
  • Set‐Top Boxes
  • DVD‐Video Player
  • Telecom Equipment
  • ADSL Modem
  • Printer and other Peripheral Equipment
  • Microprocessor core supply
  • Networking power suppl y
  • Pre‐Regulator for Linear Regulators
  • Green Electronics/Appliances Application Circuits INPUT ON OUTPUT 10nF 10uF/35V 0.1uF R3 5.6KΩ 8.2nF C6 (Optional) B340A RS6515‐ADMS 2 10 7 BSIN SW SS FB GND EN COMP 25.8KΩ 1% L1 15uH 10KΩ 1% 22uF/6.3V OFF 4.75V to 21V CERAMIC x2 3.3V/2A CERAMIC x2 This integrated circuit can be damaged by ESD. Orister Corporation recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage becaus e very small parametric changes could cause the device not to meet its published specifications. DS‐RS6515‐08 JULY, 2010 www.Orister.com

Page No. : 2/11 ON OUTPUT INPUT RS6508‐ADS 1 8 5 BSIN SW SS FB GND EN COMPC4 0.1uF 22uF/6.3V C110uF/35V 10nF L1 15uH B340A 5.6KΩ 25.8KΩ 1% 10KΩ 1% C6 (Optional) 8.2nF OFF 4.75V to 21V 3.3V/2A CERAMIC x2 CERAMIC x2 Pin Ass ignments MSOP‐10(EP) SOP‐8 PACKAGE PIN SYMBOL DESCRIPTION 1 ‐ NC No Connect. 2 1 BS Bootstrap. This capacitor (C5) is needed to drive the power switch’s gate above the supply voltage. It is connected between the SW and BS pins to form a floating supply across the power switch driver. The voltage across C5 is about 5V and is supplied by the internal +5V su pply when the SW pin voltage is low. 3 ‐ NC No Connect. 4 2 IN Supply Voltage. The RS6515 operates from a 4.75V to 20V unregulated input. C1 is needed to prevent large voltage spikes from appearing at the input. 5 3 SW Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high‐side switch. 6,11 4 GND Ground. 7 5 FB Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage divider from the output voltage to ground. The feedback threshold is 0.92V. See Setting the Output Voltage. 8 6 COMP Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required. See Compensation. 9 7 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. For automatic startup, leave EN unconnected. MSOP‐10(EP) SOP‐8 10 8 SS Soft‐Start. Connect SS to an external capacitor to program the soft‐start. If unused, leave it open. DS‐RS6515‐08 JULY, 2010 www.Orister.com

Page No. : 3/11

Ordering Information

RS6515‐XX Y Z XX is nominal output voltage : AD : ADJ Y is package & Pin Assignments designator : MS : MSOP‐10(EP) S : SOP‐8 Z is Lead Free designator : P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package G: Green (Halogen Free with Commercial St andard) Block Diagram Absolute Maximum Ratings Symbol Parameter Range Units VIN Supply Voltage ‐ 0.3 to +21 V VSW SW Pin Voltage ‐ 0.3 to VIN +0.3 V VBS Boot Strap Voltage VSW ‐0.3 to VSW +6 V VFB Feedback Voltage ‐ 0.3 to +6 V VEN Enable/UVLO Voltage ‐ 0.3 to +6 V VCOMP Comp Voltage ‐ 0.3 to +6 V VSS SS Voltage ‐ 0.3 to +6 V TJ Junction Temperature 150 oC TOPR Operating Temperature Range ‐ 20 to +85 oC TSTG Storage Temperature Range ‐ 65 to +150 oC TLEAD Lead Temperature 260 oC DS‐RS6515‐08 JULY, 2010 www.Orister.com

Page No. : 4/11 DS‐RS6515‐08 JULY, 2010 www.Orister.com Electrical Characteristics (VIN=12V, TA=25°C, unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit VIN Input Voltage ‐ 4.75 ‐ 20 V VFB Feedback Voltage 4.75V ≤ VIN ≤ 21V 0.898 0.925 0.952 V RDS(ON)1 Upper Switch On Resistance ‐ ‐ 0.22 ‐ Ω RDS(ON)2 Lower Switch On Resistance ‐ ‐ 10 ‐ Ω ISw Upper Switch Leakage VEN = 0V, VSW = 0V ‐ ‐ 10 uA ILIM Current Limit (NOTE 1) ‐ 3.0 ‐ ‐ A GCS Current Sense Transconductance Output Current to Comp Pin Voltage ‐ ‐ 1.95 ‐ A/V AVEA Error Amplifier Voltage Gain ‐ ‐ 400 ‐ V/V GEA Error Amplifier Transconductance ‐ 550 830 1150 uA/V FS Oscillator Frequency ‐ ‐ 400 ‐ KHz FOSC1 Short Circuit Frequency VFB = 0V ‐ 240 ‐ KHz ‐ Soft‐Start Pin Equivalent Output Resistance ‐ ‐ 9 ‐ KΩ DMAX Maximum Duty Cycle VFB = 1.0V ‐ 90 ‐ % tON Minimum On Time ‐ ‐ 100 ‐ ns ‐ EN Shutdown Threshold ICC＞100uA 0.7 1.0 1.3 V ‐ Enable Pull Up Current VEN = 0V ‐ 1.0 ‐ uA ‐ EN UVLO Threshold Rising VIN Rising 2.35 2.50 2.65 V ‐ EN UVLO Threshold Hysteresis ‐ ‐ 210 ‐ mV ISD Supply Current (Shutdown) VIN ≤0.4V ‐ 23 36 uA IQ Supply Current (Quiescent) VEN ≥3V ‐ 1.1 1.3 mA TSD Thermal Shutdown ‐ ‐ 160 ‐ oC Notes: 1. Slope compensation changes current limit above 40% duty cycle. 2. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of th e specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. 3. Devices are ESD sensitive. Handling precaution is recommended. 4. The device is not guaranteed to function outside its operating conditions. 5. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51‐7 thermal measurement standard.

output current can be up to 2A. The resistive divider allows the FB pin to sense the output voltage as shown in Figure 1. Figure 1. Output Voltage Setting

1 R1 VV FBOUT

Where VFB is the feedback reference voltage (0.92V typ.). capacitor. If a 0.1μF capacitor is used to set the soft‐start and its period will be 13ms(typ.). The inductor value an d operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance.

Page No. : 6/11 Inductor Core Selection The inductor type must be selected once the value for L is known. Generally speaking, high efficiency converters can not afford the core loss found in low cost powdered iron cores. So, the more expensive ferrite or mollypermalloy cores will be a better choice. The selected inductance rather th an the core size for a fixed inductor value is the key for actual core loss. As the inductance increases, core losses decrease. Unfortunately, increase of the inductance requires more turns of wire and therefore the copper losses will increase. Ferrite designs are preferred at high switching frequency due to the characteristics of very low core l osses. So, design goals can focus on the reduction of copper loss and the saturation prevention. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. The previous situation results in an abrupt increase in inductor ripple current and c onsequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy. However, they ar e usually more expensive than the similar powdered iron inductors. The rule for inductor choice mainly depends on the price vs. size requirement and any radiated field/EMI requirements. C IN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by： V V VI I OUT IN IN OUT MAXOUTRMS    ) ( This formula has a maximum at V IN = 2VOUT, where IRMS = IOUT/2. This simple worst‐case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, a 10μF x 2 Lo w ESR ceramic capacitor is recommended. For the recommended capacitor, please refer to table 3 for more detail. The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT , is determined by： OUT LOUT fC 8 1ESR I V The output ripple will be highest at the maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density th an other types. Although Tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost‐sensitive applications for ripple current rating and long term reliability considerations. Ceramic cap acitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. DS‐RS6515‐08 JULY, 2010 www.Orister.com

cause a voltage spike at VIN large enough to damage the part. diode forward voltage and recovery times, use a Schottky diode. is greater than the maximum load current. rating is greater than the maximum load current. value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Table 1. Suggested Inductors for Typical Application Circuit Table 2. Suggested Capacitors for CIN and COUT Table 3. Schottky Rectifier Selection Guide

Page No. : 8/11 MSOP‐10(EP) Dimension NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash, protrusion. D. This package is designed to be soldered to a thermal pad on the board. E. Falls within JEDEC MO‐187 variation BA‐T. DS‐RS6515‐08 JULY, 2010 www.Orister.com

Page No. : 9/11 SOP‐8 Dimension NOTES: F. All linear dimensions are in millimeters (inches). G. This drawing is subject to change without notice. H. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0.15) per end. J. Falls within JEDEC MS‐012 variation AA. DS‐RS6515‐08 JULY, 2010 www.Orister.com

Page No. : 10/11 Soldering Methods for Orister’s Products 1. Storage environment: Temperature=10oC~35oC Humidity=65%±15% 2. Reflow soldering of surface‐mount devices Figure 1: Temperature profile tP tL Ramp-down Ramp-up Tsmax Tsmin Critical Zone TL to TP tS Preheat TL TP t 25oC to Peak Time Temperature Profile Feature Sn‐Pb Eutectic Assembly Pb‐Free Assembly Average ramp‐up rate (TL to TP) <3oC/sec <3oC/sec Preheat ‐ Temperature Min (Tsmin) ‐ Temperature Max (Tsmax) ‐ Time (min to max) (ts) 100oC 150oC 60~120 sec 150oC 200oC 60~180 sec Tsmax to TL ‐ Ramp‐up Rate <3oC/sec <3oC/sec Time maintained above: ‐ Temperature (TL) ‐ Time (tL) 183oC 60~150 sec 217oC 60~150 sec Peak Temperature (TP) 240oC +0/‐5oC 260oC +0/‐5oC Time within 5oC of actual Peak Temperature (tP) 10~30 sec 20~40 sec Ramp‐down Rate <6oC/sec <6oC/sec Time 25oC to Peak Temperature <6 minutes <8 minutes 3. Flow (wave) soldering (solder dipping) Products Peak temperature Dipping time Pb devices. 245oC 5oC 5sec 1sec Pb‐Free devices. 260oC +0/‐5oC 5sec 1sec DS‐RS6515‐08 JULY, 2010 www.Orister.com

Page No. : 11/11 DS‐RS6515‐08 JULY, 2010 www.Orister.com Important Notice: © Orister Corporation Orister cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an Orister product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. Orister reserves the right to make changes to their products or specifications or to discontinue an y product or service without notice. Except as provided in Orister’s terms and conditions of sale, Orister assumes no liability whatsoever, and Orister disclaims any express or implied warranty relating to the sale and/or use of Orister products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pa tent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent Orister deems necessary to su pport this warranty. Specific testing of all parameters of each device is not necessarily performed. Orister and the Orister logo are trademarks of Orister Corporation. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders.