B300D44A102XXG

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Audio Processor for Portable Communication Devices Introduction BelaSigna® 300 is a DSP −based mixed −signal audio processing system that delivers superior audio clarity without compromising size or battery life. The processor is specifically designed for monaural portable communication devices requiring high performance audio processing capabilities and programming flexibility when form−factor and power consumption are key design constraints. The efficient dual−MAC 24−bit CFX DSP core, together with the HEAR configurable accelerator signal processing engine, high speed debugging interface, advanced algorithm security system, state −of− the−art analog front end, Class D output stage and much more, constitute an entire system on a single chip, which enables manufacturers to create a range of advanced and unique products. The system features a high level of instructional parallelism, providing highly efficient computing capability. It can simultaneously execute multiple advanced adaptive noise reduction and echo cancellation algorithms, and uses an asymmetric dual−core patented architecture to allow for more processing in fewer clock cycles, resulting in reduced power consumption. BelaSigna 300 is supported by a comprehensive suite of development tools, hands −on training, full technical support and a network of solution partners offering software and engineering services to help speed product design and shorten time to market. Key Features

Flexible DSP−based System: a complete DSP−based, mixed−signal audio system consisting of the CFX core, a fully programmable, highly cycle−efficient, dual−Harvard architecture 24−bit DSP utilizing explicit parallelism; the HEAR configurable accelerator for optimized signal processing; and an efficient input/output controller (IOC) along with a full complement of peripherals and interfaces, which optimize the architecture for audio processing at extremely low power consumption
Ultra−low−power: typically 1−5 mA
Excellent Audio Fidelity: up to 110 dB input dynamic range, exceptionally low system noise and low group delay
Miniature Form Factor: available in a miniature 3.63 mm x 2.68 mm x 0.92 mm (including solder balls) WLCSP package. In addition, BelaSigna 300 is also available in a bigger DFN package allowing easier assembly and PCB routing
Multiple Audio Input Sources: four input channels from five input sources (depends on package selection) can be used simultaneously for multiple microphones or direct analog audio inputs
Full Range of Configurable Interfaces: including a fast I2C−based interface for download, debug and general communication, a highly configurable PCM interface to stream data into and out of the device, a high−speed UART, an SPI port and 5 GPIOs http://onsemi.com DFN−44 D SUFFIX CASE 506BU MARKING DIAGRAM WLCSP−35 W SUFFIX CASE 567AG BELASIGNA300 35−02−G XXXXYZZ BELASIGNA300 = Device Code 35 = Number of Balls 02 = Revision of Die G = Pb −Free XXXX = Date Code Y = Assembly Plant Identifier = (May be Two Characters) ZZ = Traceability Code Device Package

ORDERING INFORMATION

(Pb−Free) B300D44A102XXG DFN (Pb−Free) Shipping

2500 Units /

http://onsemi.com

Integrated A/D Converters and Powered Output: minimize need for external components
Flexible Clocking Architecture: supports speeds up to

40 MHz

“Smart” Power Management: including low current standby mode requiring only 0.06 mA
Diverse Memory Architecture: 4864x48−bit words of shared memory between the CFX core and the HEAR accelerator plus 8−Kword DSP core data memory, 12−Kwords of 32−bit DSP core program memory as well as other memory banks
Data Security: sensitive program data can be encrypted for storage in external NVRAM to prevent unauthorized parties from gaining access to proprietary software intellectual property, 128−bit AES encryption
Development Tools: interface hardware with USB support as well as a full IDE that can be used for every step of program development including testing and debugging
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

The tests were performed at 20°C with a clean 1.8 V supply voltage. BelaSigna 300 was running in low voltage mode (VDDC = 1.2 V). The system clock (SYS_CLK) was set to 5.12 MHz and the sampling frequency is 16 kHz unless otherwise noted. Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part. Table 2. ELECTRICAL SPECIFICATIONS

1.8 V if it relies on an external

5.12 MHz, 16 kHz

DFN Package option can have higher input −referred noise up to 2 /C0109V worse than the WLCSP. WLCSP specifications listed.
CDM only applies to the DFN package.

Table 2. ELECTRICAL SPECIFICATIONS (continued)

100 Hz to 10 kHz BW

DFN Package option can have higher input −referred noise up to 2 /C0109V worse than the WLCSP. WLCSP specifications listed.
CDM only applies to the DFN package.

DFN Package option can have higher input −referred noise up to 2 /C0109V worse than the WLCSP. WLCSP specifications listed.
CDM only applies to the DFN package.

DFN Package option can have higher input −referred noise up to 2 /C0109V worse than the WLCSP. WLCSP specifications listed.
CDM only applies to the DFN package.

All BelaSigna 300 packages are Pb−free, RoHS−compliant and Green. BelaSigna 300 parts are qualified against standards outlined in the following sections. All BelaSigna 300 package options are Green (RoHS−compliant). Contact ON Semiconductor for supporting documentation. Table 3. WLCSP PACKAGE−LEVEL QUALIFICATION Table 4. WLCSP BOARD−LEVEL QUALIFICATION The DFN package has been qualified against AEC−Q100. Contact ON Semiconductor for full details. Table 5. DFN PACKAGE−LEVEL QUALIFICATION Table 6. DFN BOARD−LEVEL QUALIFICATION

A 2.68 x 3.63 mm ultra−miniature wafer−level chip scale package (WLCSP)

description of these pins is given in Table 7. Table 7. WLCSP PAD DESCRIPTIONS

If no pre −screening of solder paste is used,
the solder mask opening should be >0.3 mm in
the copper pad will have 0.25 mm diameter, and
soldermask thickness should be less than 1 mil

thick above the copper surface. BelaSigna 300 WLCSP (B300W35A102XYG) has an average weight of 0.095 grams. A total of 44 active pins are present on the BelaSigna 300 DFN package. A description of these pins is given in Table 8. Table 8. DFN PAD DESCRIPTIONS

20 RCVR_HP+ Extra output driver pad for high power mode O A

19 RCVR+ Output from output driver O A

18 RCVR− Output from output driver O A

17 RCVR_HP− Extra output driver pad for high power mode O A

13 CAP0 Charge pump capacitor pin 0 N/A A

14 CAP1 Charge pump capacitor pin 1 N/A A

12 VDBL Doubled voltage O A

11 VBAT Power supply I A

10 VREG Regulated supply voltage O A

9 AGND0 Analog ground 0 N/A A

8 AGND1 Analog ground 1 N/A A

2 AIR01 Input stage reference for channels 0 and 1 N/A A

5 AIR23 Input stage reference for channels 2 and 3 N/A A

7 AI4 Audio signal input 4 I A

6 AI3/LOUT3 Audio signal input 3/output signal from preamp 3 I/O A

4 AI2/LOUT2 Audio signal input 2/output signal from preamp 2 I/O A

3 AI1/LOUT1 Audio signal input 1/output signal from preamp 1 I/O A

1 AI0/LOUT0 Audio signal input 0/output signal from preamp 0 I/O A

44 GPIO[4]/LSAD[4] General−purpose I/O 4/low speed AD input 4 I/O A/D

43 GPIO[3]/LSAD[3] General−purpose I/O 3/low speed AD input 3 I/O A/D

42 GPIO[2]/LSAD[2] General−purpose I/O 2/low speed AD input 2 I/O A/D

41 GPIO[1]/LSAD[1]/UART−RX General−purpose I/O 1/low speed AD input 1/and UART RX I/O A/D

40 GPIO[0]/UART−TX General−purpose I/O 0/UART TX I/O A/D

34 GNDC Core logic ground N/A A

33 VDDC Core logic power O A

39 GNDO Digital ground N/A A

38 VDDO Digital power I A

Table 8. DFN PAD DESCRIPTIONS (continued)

28 VDDO_SPI Supply for SPI interface I/O I A

32 SPI_CLK Serial peripheral interface clock O D

31 SPI_SERI Serial peripheral interface input I D

30 SPI_CS Serial peripheral interface chip select O D

29 SPI_SERO Serial peripheral interface output O D

37 SDA (I2C) I2C data I/O D

36 SCL (I2C) I2C clock I/O D

35 EXT_CLK External clock input/internal clock output I/O D

27 PCM_FR PCM interface frame I/O D

26 PCM_SERI PCM interface input I D

25 PCM_SERO PCM interface output O D

24 PCM_CLK PCM interface clock I/O D

23 Reserved Reserved

yield with the fine pitch on the DFN pads. the input traces from the output traces. of the power regulator as illustrated in Figure 1. Figure 1. Schematic of Ground Scheme

consideration, see Table 9 and Table 10. connect to the star point with separate traces. Supply V oltage section for more details on VDDC. Table 9. Non−critical signals are outlined in Table 10. Table 9. CRITICAL SIGNALS VBAT Power supply Place 1 /C0109F (min) decoupling capacitor close to pin. Connect negative terminal of capacitor to DGND plane. Place separate 1 /C0109F decoupling capacitors close to each pin. Connect negative capacitor terminal to AGND. Keep away from digital traces and output traces. VREG may be used to generate microphone bias. VDBL shall not be used to supply external circuitry. AGND Analog ground return Connect to AGND plane. VDDC Internal regulator for digital core Place 10 /C0109F decoupling capacitor close to pin. Connect negative terminal of capacitor to DGND. GNDC Digital ground return Connect to digital ground. GNDO Digital ground return Connect to digital ground. Audio inputs Keep as short as possible. Keep away from all digital traces and audio outputs. Avoid routing in parallel with other traces. Connect unused inputs to AGND. Direct digital audio output Keep away from analog traces, particularly audio inputs. Corresponding traces should be of approximately the same length. Ideally, route lines parallel to each other. GNDRCVR Output stage ground return Connect to star point. Keep away from all analog audio inputs.

Table 10. NON−CRITICAL SIGNALS omitted for transparent bass response. might also be provided by the VDBL power supply. microphone inputs to avoid cross−coupling. approximately the same to provide matched impedances. Table 11. RECOMMENDATIONS FOR UNUSED PADS

Table 11. RECOMMENDATIONS FOR UNUSED PADS (continued) The architecture of BelaSigna 300 is shown in Figure 2. Figure 2. BelaSigna 300 Architecture: A Complete Audio Processing System

Dual−MAC 24−bit load−store DSP core
Four 56−bit accumulators
Four 24−bit input registers
Support for hardware loops nested up to 4 deep
Combined XY memory space (48−bits wide)
Dual address generator units
Wide range of addressing modes: ♦ Direct ♦ Indirect with post−modification ♦ Modulo addressing ♦ Bit reverse CFX DSP Architecture The CFX architecture encompasses various memory types and sizes, peripherals, interrupt controllers, and interfaces. Figure 3 illustrates the basic architecture of the CFX. The control lines shown exiting the PCU indicate that control signals go from the PCU to essentially all other parts of the CFX. The CFX employs a parallel instruction set for simultaneous control of multiple computation units. The DSP can execute up to four computation operations in parallel with two data transfers (including rounding and/or saturation as well as complex address updates), while simultaneously changing control flow. SR LR ILSR ILPC PC PCU CTRL Pre−adder X Multiplier X ALU and Shifter A Accumulators Y Multiplier DCU Y ALU Immediate Interrupts CTRL X Round/ Saturate Y Round/ Saturate X Sign/Zero Extend Y Sign/Zero Extend DMU X Data Y Data SP Offset Direct Addr CTRL PMEM XMEM YMEM Internal Routing Instruction Bus P Bus X Bus Y BusY Bus X Bus P Bus Internal Routing X AGU Y AGU Data registers Address and Control registers Hardware Loop Stack B Accumulators

Figure 3. CFX DSP Core Architecture

shown in the table. Please refer to the CFX DSP Architecture Manual for more details. Table 12. CFX SUMMARY INSTRUCTION SET

Table 12. CFX SUMMARY INSTRUCTION SET (continued) Accelerator Reference Manual. accordingly. It is an advanced audio DMA unit. Table 13. RAM AND ROM STRUCTURE

pointers when a new block has been read or written. The structure of the XMEM and YMEM address spaces are shown in Figure 5. Figure 5. XMEM and YMEM Memory Maps

The structure of the PMEM address space is shown in Figure 6. Figure 6. PMEM Memory Map

detecting input from a push button. acknowledged as a check that an application is still running. acknowledgement, a system reset will occur. generated by the CFX DSP core and the HEAR accelerator. which are interrupts in the CFX. Reference Manual for BelaSigna 300. Figure 7. Interrupt Flow unlocked, both memory and EEPROM are accessible. from external access by the regular access restrictions.

steps). The input stage is shown in Figure 8. Figure 8. Input Stage modulator is pre−scaled from the system clock.

signal to all components using the reference voltage. it is internally connected to VBAT. as it is internally connected to VBAT. the regulated voltages within the system. internal charge pump. It is a reference to the analog circuitry. filtering of the regulated voltages within the system. and VDDO_SPI power sources determine these voltage levels. to ensure proper device operation under all battery conditions. voltages are shown in Table 15. Table 15. POWER MANAGEMENT THRESHOLDS

The internal regulators are enabled and allowed to
The internal charge pump is enabled and allowed
SYSCLK is connected to all of the system
The system switches to external clocking mode

http://onsemi.com Power Management Strategy BelaSigna 300 has a built−in power management unit that guarantees valid system operation under any voltage supply condition to prevent any unexpected audio output as the result of any supply irregularity. The unit constantly monitors the power supply and shuts down all functional units (including all units in the audio path) when the power supply voltage goes below a level at which point valid operation can no longer be guaranteed. Once the supply voltage rises above the startup voltage of the internal regulator that supplies the digital subsystems (VDDC STARTUP) and remains there for the length of time TPOR, a POR will occur. If the supply is consistent, the internal system voltage will then remain at a fixed nominal voltage (VDDC NOMINAL). If a spike occurs that causes the voltage to drop below the shutdown internal system voltage (VDDCSHUTDOWN), the system will shut down. If the voltage rises again above the startup voltage and remains there for the length of time T POR, a POR will occur. If operating directly off a battery, the system will not power down until the voltage drops below the VDDC SHUTDOWN voltage as the battery dies. This prevents unwanted resets when the voltage is just on the edge of being too low for the system to operate properly because the difference between VDDC STARTUP and VDDCSHUTDOWN prevents oscillation around the VDDCSHUTDOWN point. Other Analog Support Blocks and Functions Low−Speed A/D Converters (LSAD) The BelaSigna 300 chip has four LSAD channels that connect to external analog inputs for purposes such as for reading the value of a potentiometer or an analog sensor (LSAD[1..4]). The native data format for the LSAD is 10−bit two’s −complement. However, a total of eight operation modes are provided that allow a configurable input dynamic range in cases where certain minimum and maximum values for the converted inputs are desired, such as in the case of a volume control where only input values up to a certain magnitude are allowed. Each LSAD channel is sampled at a nominal frequency of 1.6 kHz when using the default settings. Each LSAD pin is multiplexed with a GPIO function (see the General −Purpose Input Output Ports section) as such the functionality of the pin can be either a GPIO or an LSAD depending on the configuration. Battery Monitor A programmable on−chip battery monitor is available for overall system power management. The battery monitor works by incrementing a counter value every time the battery voltage goes below a desired, configurable threshold value. This counter value can be used in an application − specific power −management algorithm running on the CFX. The CFX can initiate any desired actions once the battery hits a predetermined value. Digital Interfaces General−Purpose Input Output (GPIO) Ports BelaSigna 300 has five GPIO ports that can connect to external digital inputs such as push buttons, or digital outputs such as the control or trigger of an external companion chip (GPIO[0..4]). The direction of these ports (input or output) is configurable and each pin has an internal pull −up resistor when configured as a GPIO. A read from an unconnected pin will give a value of logic 1. Four of the five GPIO pins are multiplexed with an LSAD (see the Low −Speed A.D Converters section) and as such the functionality of the pin can be either a GPIO or an LSAD depending on the configuration. Note that GPIO0 cannot be used as an LSAD. Inter−IC Communication (I2C) Interfaces The I2C interface is an industry −standard interface that can be used for high −speed transmission of data between BelaSigna 300 and an external device. The interface operates at speeds up to 400 Kbit/sec for system clocks (EXT_CLK) higher than 1.6 MHz. In product development mode, the I 2C interface is used for application debugging purposes, communicating with the BelaSigna 300 development tools. The interface can be configured to operate in either master mode or slave mode. Serial Peripheral Interface (SPI) Port An SPI port is available on BelaSigna 300 for applications such as communication with a non −volatile memory (EEPROM). The I/O levels on this port are defined by the voltage on the VDDO_SPI pin on the DFN package option, whereas it is defined by VBAT on the WLCSP package option. The SPI port operates in master mode only, which supports communications with slave SPI devices. The SPI port on BelaSigna 300 only supports master mode, so it will only communicate with SPI slave devices. When connecting to an SPI slave device other than a boot EEPROM, the SPI_CS pin should be left unconnected and the slave device CS line should be driven from a GPIO to avoid BelaSigna 300 boot malfunction. When connecting to an SPI EEPROM for boot, the designer can choose to connect the SPI_CS pin to the EEPROM or use a GPIO (high at boot) for a design with several daisy-chained SPI devices. PCM Interface BelaSigna 300 includes a highly configurable pulse code modulation (PCM) interface that can be used to stream signal, control and configuration data into and out of the device. The I/O levels on this port are defined by the voltage on the VDDO pin (VBAT on the WLCSP package option). UART Interface A general−purpose two−pin UART interface is available for RS −232 compatible communications. The baud rate (bits/second) of this interface is typically configurable within a range of 0.4 to 320 kbps, depending on the application’s system clock. The I/O levels on this port are defined by the voltage on the VDDO pin (VBAT on the WLCSP option).

The application diagram of BelaSigna 300 (WLCSP Option) is shown in Figure 14. Figure 14. BelaSigna 300 WLCSP Application Diagram

The application diagram of BelaSigna 300 (DFN Option) is shown in Figure 15. Figure 15. BelaSigna 300 DFN Application Diagram

http://onsemi.com Sample Shipping Label Figure 20. Sample Shipping Label for the re−flow and the assembly that is being re −flowed. J−STD−020D.01 can be used as a guideline. To order BelaSigna 300 WLCSP, please contact your account manager and ask for part number B300W35A102XYG. To order BelaSigna 300 DFN, please contact your account manager and ask for part number B300D44A102XXG. Chip Identification Chip identification information can be retrieved by using the Communications Accelerator Adaptor (CAA) tool along with the protocol software provided by ON Semiconductor (see CAA instruction manual). For BelaSigna 300, the key identifier components and values are as follows for the different package options: Package Option Chip Family Chip Version Chip Revision WLCSP 0x03 0x02 0x0100 DFN 0x03 0x01 0x0200 Support Software A full suite of comprehensive tools is available to assist software developers from the initial concept and technology assessment through to prototyping and product launch. Simulation, application development and communication tools as well as an Evaluation and Development Kit (EDK) facilitate the development of advanced algorithms on BelaSigna 300. Training To facilitate development on the BelaSigna 300 platform, training is available upon request. Contact your account manager for more information. Company or Product Inquiries For more information about ON Semiconductor products or services visit our Web site at http://onsemi.com.

http://onsemi.com PACKAGE DIMENSIONS WLCSP35, 3.63x2.68 CASE 567AG−01 ISSUE B SEATING PLANE 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A MIN MAX 0.84 MILLIMETERS D 3.63 BSC E b 0.24 0.29 eD 0.25 BSC 1.00 È È D E AB PIN A1 REFERENCE eD A0.05 BC 0.03 C 0.05 C 35X b 456 C B A 0.10 C A C 0.17 0.23

2.68 BSC

eE 0.433 BSC 0.25 35X DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.250

0.10 C2X TOP VIEW

A2 0.72 REF RECOMMENDED PACKAGE OUTLINE 123789 PITCH C 0.125 BSC E D 1011121314 C 0.433 PITCH 0.125

http://onsemi.com PACKAGE DIMENSIONS ÉÉÉ ÉÉÉ ÉÉÉ DFN44 8.9x5, 0.4P CASE 506BU−01 ISSUE O SEATING K 0.15 C (A3) A b 44X L44X BOTTOM VIEW DETAIL A TOP VIEW SIDE VIEW D A B E 0.15 C PIN ONE LOCATION 0.10 C 0.08 C C e/2 A0.07 B C 0.05 C NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. PLANE DIM MIN MAX MILLIMETERS A 0.80 0.90 A1 0.00 0.05 A3 0.20 REF b 0.15 0.25 D 8.90 BSC D2 8.20 8.40 E 5.00 BSC e 0.40 BSC K 0.20 −−− L 0.30 0.50 3.50 3.70 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.63 0.40 3.70 44X 0.2644X 5.30 8.40 DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÉÉ ÉÉÉÉ ÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONS NOTE 4 DETAIL B NOTE 3 L1 0.00 0.15 DIMENSIONS: MILLIMETERS e AM0.10 B C M M AM0.10 B C PITCH PACKAGE OUTLINE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. B300/D BelaSigna is a registered trademark of Semiconductor Components Industries, LLC. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative

Product Information

B300D44A102XXG specifications and overview.

Summary

Audio Processor for Portable Communication Devices DFN??4 D SUFFIX March, 2011 ??Rev. 7

Description