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© Semiconductor Components Industries, LLC, 2012 July, 2012 − Rev. 9

1 Publication Order Number:

BELASIGNA® 250 is a complete programmable audio processing system, designed specifically for ultra −low−power embedded and portable digital audio systems. This high−performance chip builds on the architecture and design of BELASIGNA 200 to deliver exceptional sound quality along with unmatched flexibility. BELASIGNA 250 incorporates a full audio signal chain, from stereo 16−bit A/D converters or digital interfaces to accept the signal, through the fully flexible digital processing architecture, to stereo analog line −level or direct digital power outputs that can connect directly to speakers. BELASIGNA 250 features flexible clocking options and smart power management features including a soft power−down mode. Two DSP subsystems operate concurrently: the RCore, which is a fully software programmable DSP core, and the weighted overlap −add (WOLA) filterbank coprocessor, which is a dedicated, configurable processor that executes time−frequency domain transforms and other vector− based computations. A full range of other hardware −assisted features, such as audio−targeted DMA complete the system. A comprehensive and easy −to−use suite of development tools, hands−on training and full technical support are available to enable rapid development and introduction of highly differentiated products in record time. Key Features

  • Unique Parallel−processing Architecture: A Complete DSP−based, Mixed−signal Audio System Consisting of a 16−bit Fully Programmable Dual−Harvard 16−bit DSP Core, a Patented, High−resolution Block Floating−point WOLA Filterbank Coprocessor, and an Input/Output Processor (IOP) along with Several Peripherals and Interfaces which Optimize the Architecture for Audio Processing
  • Integrated Converters and Powered Output: Minimize Need for External Components
  • Ultra−low Power Consumption: Under 5 mA at 20 MHz to Support Advanced Operations; 1.8 V Supply V oltage
  • “Smart” Power Management: Including Low Current Standby Mode Requiring Only 0.05 mA
  • Flexible Clocking Architecture: Supports Speeds up to 50 MHz
  • Full Range of Configurable Interfaces: Including: I2S, PCM, UART, SPI, I2C, TWSS, GPIO
  • Excellent Fidelity: 88 dB System Dynamic Range, Exceptionally Low System Noise and Low Group Delay
  • Support for IP Protection: to Prevent Unauthorized Access to Algorithms and Data
  • Available in CABGA and LFBGA Package Options
  • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com LFBGA−64 PLASTIC CASE 504 MARKING DIAGRAMS CABGA−57 PLASTIC CASE 566AA See detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet.

ORDERING INFORMATION

0W888−002 = 64 LFBGA Option 0W633 = 57 CABGA Option XXXX = Date Code Y = Assembly Plant Identifier ZZ = Traceability Code AAAA = Country of Assembly XXXXYZZ BELASIGNA 250 0W888−002 AAAA XXXXYZZ B−250 0W633 AAAA

Table 1. ABSOLUTE MAXIMUM RATINGS

  1. Below 1.05 V audio performance will be degraded.
  2. Parameters may exceed listed tolerances when out of the temperature range 0 to 50 °C.

was set to 5.12 MHz and a sampling frequency of 16 kHz was used with MCLK was set to 1.28 MHz. Parameters marked as screened are tested on each chip. Other parameters are qualified but not tested on every part. Table 2. ELECTRICAL SPECIFICATIONS

5.12 MHz, 16 kHz − 1 − mA

19.2 MHz, 16 kHz − 5 − mA

49.152 MHz, 16 kHz − 10 − mA

49.152 MHz, 48 kHz − 13 − mA

  1. Audio performance will be degraded below 1.05 V.
  2. Measured with a = 12 dB input signal.
  3. Input stage delay is inversely proportional to sampling frequency.
  4. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.

Table 2. ELECTRICAL SPECIFICATIONS (continued)

20 Hz to 8 kHz BW

  1. Audio performance will be degraded below 1.05 V.
  2. Measured with a = 12 dB input signal.
  3. Input stage delay is inversely proportional to sampling frequency.
  4. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
  1. Audio performance will be degraded below 1.05 V.
  2. Measured with a = 12 dB input signal.
  3. Input stage delay is inversely proportional to sampling frequency.
  4. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
  1. Audio performance will be degraded below 1.05 V.
  2. Measured with a = 12 dB input signal.
  3. Input stage delay is inversely proportional to sampling frequency.
  4. Max voltage should be limited to 2.2 V peak regardless of VDDC. Protection diodes will be enabled above this voltage.
  • A 7 x 7 mm LFBGA package where all the device I/Os are available at the BGA level
  • A 5 x 5 mm CABGA package BELASIGNA 250 also exists in a PLCC package, but it is only used on the evaluation and development board. The PLCC package is not available in production quantities. A separate data sheet is available for this part (part number 0W548−001−XTD). Contact ON Semiconductor for more information on this package option. All BELASIGNA 250 package options are Green (RoHS− compliant). Contact ON Semiconductor for supporting documentation. A total of 51 active pins are present on the BELASIGNA 250 7 x 7 mm LFBGA package option. This package contains a total of 64 balls, organized in an 8−by−8 array. A description of these pins is given in Table 3.

Table 3. LFBGA PIN DESCRIPTIONS

Table 3. LFBGA PIN DESCRIPTIONS (continued) NOTE: Unlisted pads must be left unconnected. BELASIGNA 250 LFBGA (0W888−002−XTP) has an average weight of 0.1275 grams. Table 4. CABGA PIN DESCRIPTIONS

Table 4. CABGA PIN DESCRIPTIONS (continued)

http://onsemi.com Recommended Design Guidelines BELASIGNA 250 is designed to allow both digital and analog processing in a single system. Due to the mixed−signal nature of this system, the careful design of the printed circuit board (PCB) layout is critical to maintain the high audio fidelity of BELASIGNA 250. To avoid coupling noise into the audio signal path, keep the digital traces away from the analog traces. To avoid electrical feedback coupling, isolate the input traces from the output traces. Recommended Ground Design Strategy The ground plane should be partitioned into two: the analog ground plane (AGND) and the digital ground plane (DGND). These two planes should be connected together at a single point, known as the star point. The star point should be located at the ground terminal of a capacitor on the output of the power regulator as illustrated in Figure 1. The DGND plane is used as the ground return for digital circuits and should be placed under digital circuits. The AGND plane should be kept as noise−free as possible. It is used as the ground return for analog circuits and it should surround analog components and pins. It should not be connected to or placed under any noisy circuits such as RF chips, switching supplies or digital pads of BELASIGNA 250 itself. Analog ground returns associated with the audio output stage should connect back to the star point on separate individual traces. For more information on the recommended ground design strategy, see Table 5 and Table 6. In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be used. Each analog ground return should connect to the star point with separate traces.

Figure 1. Schematic of Ground Scheme

should be placed as close as possible to the power pads. Further details on these critical signals are provided in Table 5. Non−critical signals are outlined in Table 6. Table 5. CRITICAL SIGNALS negative terminal of capacitor to DGND plane. phone bias. VDBL shall not be used to supply external circuitry. AGND Analog ground return Connect to AGND plane. terminal of capacitor to DGND. GNDO / GNDC Digital ground return (pads and core) Connect to digital ground. with microphone grounds to star point. AO0, AO1 Analog audio output Keep away from microphone inputs. Direct digital audio output Keep away from analog traces, particularly microphone inputs. other and approximately the same length. AOR Output stage reference voltage Connect to star point. Share trace with power amplifier (if present). RCVRGND Output stage ground return Connect to star point. Keep away from analog inputs. surround with digital ground. AI_RC Infrared receiver input If used, minimize trace length to photodiode. Table 6. NON−CRITICAL SIGNALS operation, should be connected to DGND. Pulse code modulation port Not critical − Keep away from analog signals.

Figure 3. RCore DSP Architecture three−stage pipeline (FETCH, DECODE, EXECUTE). X data memory (XRAM) and Y data memory (YRAM).

  1. Arithmetic and Logic Instructions

can be utilized by applying appropriate shifts to the data. to the previous product (a MAC operation) are available. of specific bits, limiting, and other functions.

  1. Data Movement Instructions

(accumulator, PH, PL, etc.).

  1. Program Flow Control Instructions

unconditional branches are also provided. The full instruction set may be seen in Table 7.

Table 7. INSTRUCTION SET

Table 8. NOTATION

Figure 4. WOLA Filterbank Coprocessor Architecture time−frequency processing and alias−free gain adjustments. coprocessor during execution. application, synthesis) through dedicated control registers. data to the audio output stage from the output FIFO. interface is especially useful for time−domain filters. an IOP end−of−battery−life auto−mute feature is available. four different audio modes that are shown in Figure 8.

  • Mono mode: Input samples are stored sequentially in the input FIFO. Output samples are stored sequentially in the output FIFO.
  • Simple stereo mode: Input samples from the two channels are interleaved in the input FIFO. Output samples for the single output channel are stored in the lower part of the output FIFO.
  • Digital mixed mode: Input samples from the two channels are stored in each half of the input FIFO. Output samples for the single output channel are stored in the lower half of the output FIFO.
  • Full stereo mode: Input samples from the two channels are interleaved in the input FIFO. Output samples for the two output channels are also interleaved in the output FIFO.

Figure 5. Audio Modes

Complete memory maps for BELASIGNA 250 are shown in Figure 6. Figure 6. Memory Maps voltage or reading the value of a volume control. acknowledged as a check that an application is still running. acknowledgement, BELASIGNA 250 will fully reset itself. the priority scheme of the interrupt sources can be modified. Refer to Table 9 for a description of all interrupts.

Table 9. INTERRUPT DESCRIPTIONS bypass or gain values of 12 to 30 dB (3 dB steps). for optimal gain matching between the two input channels. versa). This is useful in beam−forming applications. Figure 7. Input Stage

/C0083/C0068 D/A converter and the direct digital outputs. configurable at 10 or 20 kHz. interval 12 to 30 dB (3 dB steps) or it can be bypassed. the chip and the supply for the output driver. The output stage is shown in Figure 8. Figure 8. Output Stage

BELASIGNA 250 chip is the system clock (SYS_CLK). Table 10. CLOCK DOMAINS

1.92 MHz sampling frequencies up to 30 kHz can be

current draw, which can affect the audio signal.

  • High voltage (HV) power supply mode: BELASIGNA 250 operates from a nominal supply of

1.8 V on VBAT, but this can scale depending on

necessary for higher than 5.12 MHz system clocks.

  • Low voltage (LV) power supply mode: BELASIGNA 250 operates from a nominal supply of 1.25 V . The WOLA, the RCore and all digital I/O pads run from a 1 V regulated supply. The low voltage operation of the processing cores is very power−efficient, but the system clock should be kept under 5.12 MHz to ensure proper operation.
  • Double voltage (DV) power supply mode: BELASIGNA 250 operates from a nominal supply of 1.25 V . The WOLA, the RCore and all digital I/O pads run from the on−chip charge pump which regulates internal voltage up to 2 V . This allows BELASIGNA 250 to communicate with higher voltage systems like a 1.8 V EEPROM when running on a lower supply voltage. However, a specific level translation mechanism has been designed to allow BELASIGNA 250 to communicate with an SPI EEPROM in low voltage mode as well. This voltage mode is not suitable for normal operation, processing in this mode may result in audible audio artifacts. Most BELASIGNA 250 applications run in high voltage mode. Power−on−Reset (POR) and Booting Sequence At POR, all control registers and RCore registers are put into known default states. During the power−on procedure, all audio outputs are muted; all RCore registers and all control registers (analog and digital) are set to default values. (Please contact ON Semiconductor for more

BELASIGNA 250 boots in a two −stage boot sequence. external EEPROM 200 ms after power is applied to the chip. approximately every second and attempts to reboot. sequence can be seen in Figure 9. Figure 9. Booting Sequence operation can no longer be guaranteed. The power supply operation can be seen in Figure 10. around the VDDCSHUTDOWN point.

Figure 10. Power Management at the same instant in time. Six LSAD inputs are available on BELASIGNA 250. multiplexed with other functionality. internal LSAD tied directly to the power supply. scheme. Data are received at 1200 bps by a dedicated UART. through memory mapped control registers and interrupts.

  • 16−pin general−purpose I/O (GPIO) interface.
  • Serial peripheral interface (SPI) communications port with interface speeds up to 640 kbps at 1.28 MHz system clock. The SPI port on BELASIGNA 250 only supports master mode, so it will only communicate with SPI slave devices. When connecting to an SPI slave device other than a boot EEPROM, the SPI_CS pin should be left unconnected and the slave device CS line should be driven from a GPIO to avoid BELASIGNA 250 boot malfunction. When connecting

http://onsemi.com to an SPI EEPROM for boot, the designer can choose to connect the SPI_CS pin to the EEPROM or use a GPIO (high at boot) for a design with several daisy−chained SPI devices.

  • PCM interface for high−bandwidth digital audio I/O. This interface comes with configurable input and output buffers for reduced interrupt handling overhead when BELASIGNA 250 is used in an audio streaming application.
  • Configurable high−speed RS−232 universal asynchronous receiver/transmitter (UART).
  • RS−232−based communications port for debugging and in−circuit emulation. This interface can also be used to send analog audio data to the input stage.
  • Two−wire synchronous serial (TWSS) interface compatible with the I2C protocol and with speeds up to 100 kbps at 1.28 MHz MCLK and up to 400 kbps at MCLKs higher than 1.92 MHz. Supports master and slave operation. Assembly Information Carrier Details 7 x 7 mm LFBGA ON Semiconductor offers tape and reel packing for BELASIGNA 250 LFBGA packages. The packing consists of a pocketed carrier tape, a cover tape, and a molded anti−static polystyrene reel. The carrier and cover tape create an ESD safe environment, protecting the components from physical and electrostatic damage during shipping and handling.

Figure 15. Sample Label BELASIGNA 250 are MSL JEDEC Level 3. for the re−flow and the assembly that is being re −flowed. assessment through to prototyping and product launch. account manager for more information. or services visit our Web site at http://onsemi.com. Table 11. ORDERING INFORMATION Specifications Brochure, BRD8011/D.

http://onsemi.com PACKAGE DIMENSIONS DIM MIN NOM MILLIMETERS A --- --- A1 0.27 --- A2 0.32 REF b 0.35 0.4 D 7.0 BSC E 7.0 BSC e 0.8 BSC D1 5.6 BSC NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M-1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.1 X0.15 YZ 0.08 A PIN 1 CORNER X Y 876 321 A B C D E F G H b64 X Z 0.1 Z 0.1 ZZ VIEW M−M DETAIL K ROTATED 90 CLOCKWISE/C0095 NOTE 5 PIN 1 CORNER M M DETAIL KD E Z e/2 e7 X e/2 e

7 X NOTE 3

(SEATING PLANE) MAX 1.5 0.37 0.45 A3 0.8 REF E1 5.6 BSC LFBGA 64 BALLS, 7x7 CASE 504−01 ISSUE O

http://onsemi.com PACKAGE DIMENSIONS LFBGA 57, 5x5 CASE 566AA ISSUE B ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a numb er of patents, trademarks, reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 B250/D BELASIGNA is a registered trademark of Semiconductor Components Industries, LLC. LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative