STB130NH02L STMICROELECTRONICS | Alldatasheet

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N-CHANNEL 24V - 0.0034 Ω - 120A D²PAK/TO-220 STripFET™ III POWER MOSFET FOR DC-DC CONVERSION Rev. 2.0 Figure 1:PackageTable 1: General Features ■ TYPICAL R DS (on) = 0.0034 Ω @ 10 V ■ TYPICAL R DS (on) = 0.005 Ω @ 5 V ■ R DS(ON) * Qg INDUSTRY’s BENCHMARK ■ CONDUCTION LOSSES REDUCED ■ SWITCHING LOSSES REDUCED ■ LOW THRESHOLD DEVICE ■ SURFACE-MOUNTING D 2PAK (TO-263) POWER PACKAGE IN TUBE (NO SUFFIX) OR IN TAPE & REEL (SUFFIX “T4”)

DESCRIPTION

The STB_P130NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. It is ideal in high performance DC-DC converter applications where efficiency is to be achieved at very high output currents.

APPLICATIONS

■ SYNCHRONOUS RECTIFICATIONS FOR TELECOM AND COMPUTER ■ OR-ING DIODE Table 2: Ordering Information TYPE VDSS R DS(on) ID STB130NH02L STP130NH02L 24 V 24 V < 0.0044 Ω < 0.0044 Ω

90 A(2)

SALES TYPE MARKING PACKAGE PACKAGING STB130NH02LT4 B130NH02L TO-263 TAPE & REEL STP130NH02L P130NH02L TO-220 TUBE ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vspike(1) Drain-source Voltage Rating 30 V VDS Drain-source Voltage (VGS = 0) 24 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 24 V VGS Gate- source Voltage ± 20 V ID (2) Drain Current (continuous) at TC = 25°C 90 A ID (2) Drain Current (continuous) at TC = 100°C 90 A IDM (3) Drain Current (pulsed) 360 A Ptot Total Dissipation at TC = 25°C 150 W Derating Factor 1 W/°C EAS (4) Single Pulse Avalanche Energy 900 mJ Tstg Storage Temperature -55 to 175 °CTj Max. Operating Junction Temperature TO-220 D 2PAK TO-263 (Suffix “T4”) Figure 2: Internal Schematic Diagram

Table 4: THERMAL DATA ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) Table 5: OFF Table 6: ON (*) Table 7: DYNAMIC Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 1.0 62.5 300 °C/W °C/W Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 25 mA, VGS = 0 24 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = 20 V VDS = 20 V TC = 125°C µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20 V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS I D = 250 µA 1V R DS(on) Static Drain-source On Resistance VGS = 10 V I D = 45 A VGS = 5 V I D = 22.5 A 0.0034 0.005 0.0044 0.008 Ω Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (5) Forward Transconductance VDS = 10 V I D =4 5 A 55 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 15V f = 1 MHz VGS = 0 4450 1126 141 pF pF pF R G Gate Input Resistance f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain 1.6 Ω

Table 8: SWITCHING ON Table 9: SWITCHING OFF Table 10: SOURCE DRAIN DIODE (1) Garanted when external Rg=4.7 Ω and tf < tfmax. (5) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Value limited by wire bonding (6) Qoss = C oss*∆ Vin , C oss = C gd + C ds . See Appendix A (3) Pulse width limited by safe operating area. (7) Gate charge for synchronous operation (4) Starting Tj = 25 oC, ID = 45A, VDD = 10V . Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 10 V I D = 45 A R G =4 . 7 Ω V GS = 10 V (Resistive Load, Figure ) 224 ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD =10 V ID =90 A VGS =10 V 69 93 nC nC nC Q oss(6) Output Charge VDS = 16 V VGS = 0 V 27 nC Q gls(7) Third-quadrant Gate ChargeVDS < 0 V VGS = 10 V 64 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time VDD = 10 V I D = 45 A R G =4 . 7Ω, V GS = 10 V (Resistive Load, Figure 3) 40 54 ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM Source-drain Current Source-drain Current (pulsed) 360 A A VSD (5) Forward On Voltage ISD = 45 A VGS = 0 1.3 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 90 A di/dt = 100A/µs VDD = 15 V T j = 150°C (see test circuit, Figure 5) 2.5 ns nC A ELECTRICAL CHARACTERISTICS (continued) Figure 3: Safe Operating Area Figure 4: Thermal Impedance

DIM. mm. inch. A 4.4 4.6 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.40 2.70 0.094 0.106 H2 10 10.40 0.393 0.409 L2 16.40 0.645 L3 28.90 1.137 L4 13 14 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.20 6.60 0.244 0.260 L9 3.50 3.93 0.137 0.154 DIA 3.75 3.85 0.147 0.151 TO-220 MECHANICAL DATA

DIM. mm. inch. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.028 0.037 B2 1.14 1.7 0.045 0.067 C 0.45 0.6 0.018 0.024 C2 1.21 1.36 0.048 0.054 D 8.95 9.35 0.352 0.368 D1 8 0.315 E 10 10.4 0.394 0.409 E1 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.591 0.624 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.069 M 2.4 3.2 0.094 0.126 R 0.4 0.015 V2 0° 8° 0° 8° D 2PAK MECHANICAL DATA

DIM. mm inch MIN. MAX. MIN. MAX. A0 10.5 10.7 0.413 0.421 B0 15.7 15.9 0.618 0.626 D 1.5 1.6 0.059 0.063 D1 1.59 1.61 0.062 0.063 E 1.65 1.85 0.065 0.073 F 11.4 11.6 0.449 0.456 K0 4.8 5.0 0.189 0.197 P0 3.9 4.1 0.153 0.161 P1 11.9 12.1 0.468 0.476 P2 1.9 2.1 0075 0.082 R 50 1.574 W 23.7 24.3 0.933 0.956 DIM. mm inch MIN. MAX. MIN. MAX. A 330 12.992 B 1.5 0.059 C 12.8 13.2 0.504 0.520 D 20.2 0.795 G 24.4 26.4 0.960 1.039 N 100 3.937 T 30.4 1.197 BASE QTY BULK QTY 1000 1000 REEL MECHANICAL DATA * on sales type TUBE SHIPMENT (no suffix)* TAPE AND REEL SHIPMENT (suffix ”T4”)* D 2PAK FOOTPRINT TAPE MECHANICAL DATA

Buck Converter: Power Losses Estimation The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires:

  • Very low RDS(on) to reduce conduction losses
  • Small Qgls to reduce the gate charge losses
  • Small Coss to reduce losses due to output capacitance
  • Small Qrr to reduce losses on SW1 during its turn-on
  • The C gd/Cgs ratio lower than V th/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires:
  • Small R g and L s to allow higher gate current peak and to limit the voltage feedback on the gate
  • Small Qg to have a faster commutation and to reduce gate charge losses
  • Low RDS(on) to reduce the conduction losses.

High Side Switch (SW1) Low Side Switch (SW2) conductionP δ*I*R 2 LDS(on)SW1 )1(*I*R 2 LDS(on)SW2 δ− switchingP g L I I*f*)Q(Q*V gd(SW1)gsth(SW1)in + Zero Voltage Switching Recovery Not Applicable 1 f*Q*V rr(SW2)indiodeP Conduction Not Applicable f*t*I*V deadtimeLf(SW2) )gate(QGP f*V*Q ggg(SW1) f*V*Q gggls(SW2) QossP f*Q*V oss(SW1)in f*Q*V oss(SW2)in Parameter Meaning d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction On state losses Pswitching On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses QossP Output capacitance losses

1 Dissipated by SW1 during turn-on

Table 11:Revision History Date Revision Description of Changes April 2005 2.0 ADDED PACKAGE TO-220

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