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Technical content
Features
mWSaver™ Technology Achieve Low No-Load Power Consumption Less than 40 mW at 230 VAC (EMI Filter Loss Included) Meets 2013 ErP Standby Power Regulation (Less than 0.5 W Consumption with 0.25 W Load) for ATX Power and LCD TV Power Eliminate X-Cap Discharge Resistor Loss with AX-CAP™ Technology Linearly Decreased Switching Frequency at Light- Load Condition and Advanced Burst Mode Operation at No-Load Condition 700 V High-Voltage JFET Startup Circuit to Eliminate the Startup Resistor Loss Highly Integrated with Rich Features Internal Avalanche-Rugged 700 V SenseFET Built-in 5 ms Soft-Start Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking (LEB) Synchronized Slope Compensation Proprietary Asynchronous Jitter to Reduce EMI Advanced Protection Internal Overload / Open-Loop Protection (OLP) VDD Under-Voltage Lockout (UVLO) VDD Over-Voltage Protection (OVP) Constant Power Limit (Full AC Input Range) Internal Auto Restart Circuit (OLP, VDD OVP, OTP) Internal OTP Sensor with Hysteresis Adjustable Peak Current Limit Related Resources Evaluation Board: FEBFSB127H_T001 Fairchild Power Supply WebDesigner — Flyback Design & Simulation - In Minutes at No Expense
Description
The FSB-series is a next-generation, green-mode Fairchild Power Switch (FPS™) incorporating Fairchild’s innovative mWSaver™ technology, which dramatically reduces standby and no-load power consumption, enabling conformance to all worldwide Standby Mode efficiency guidelines. It integrates an advanced current- mode pulse width modulator (PWM) and an avalanche- rugged 700 V SenseFET in a single package, allowing auxiliary power designs with higher standby energy efficiency, reduced size, improved reliability, and lower system cost than previous solutions. Fairchild Semiconductor’ s mWSaver™ technology offers best-in-class mini mum no-load and light-load power consumption. An innovative AX-CAP™ method, one of the five proprietary mWSaver™ technologies, minimizes losses in the EMI filter stage by eliminating the X-cap discharge resist ors while still meeting IEC61010-1 safety requirement. mWSaver™ Green Mode gradually decreases switching frequency as load decreases to minimize switching losses. A new proprietary asynchronous jitter decreases EMI emission and built-in synchronized slope compensation allows stable peak-current-mode control over a wide range of input voltage. The proprietary internal line compensation ensures const ant output power limit over entire universal line voltage range. Requiring a minimum number of external components, the FSB-series provides a basic platform that is well suited for the cost-effectiv e flyback converter design with low standby power consumption.
Applications
General-purpose switched-mode power supplies and flyback power converters, including: Auxiliary Power Supply for PC, Server, LCD TV, and Game Console SMPS for VCR, SVR, STB, DVD, and DVCD Player, Printer, Facsimile, and Scanner General Adapter LCD Monitor Power / Open-Frame SMPS
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 2 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Ordering Information
Part Number SenseFET Operating Temperature Range Package Packing Method FSB117HNY 1 A, 700 V -40°C to +105°C 8-Pin, Dual In-Line Package (DIP) Tube FSB127HNY 2 A, 700 V FSB147HNY 4 A, 700 V Application Diagram Figure 1. Typical Flyback Application Table 1. Output Power Table (1)
230 VAC ±15%(2) 85-265 V AC
- The maximum output power can be li mited by junction temperature.
- 230 V AC or 100/115 VAC with voltage doubler.
- Typical continuous power in a non- ventilated enclosed adapter with sufficient drain pattern of printed circuit
board (PCB) as a heat sink, at 50C ambient.
- Maximum practical continuous power in an open-frame des ign with sufficient drain pattern of printed circuit board
(PCB) as a heat sink, at 50C ambient.
Figure 2. Block Diagram
Figure 3. Pin Configuration
2 VDD
Supply voltage of the IC. Typically the holdup capacitor connects from this pin to ground. cycle is determined by comparing the signal on this pin and the internal current-sense signal.
4 IPK
resistor, which determines the current limit level of pulse-by-pulse current limit. line disconnection detection.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 5 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™) Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may dam age the device. The device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDRAIN Drain Pin Voltage (5,6) 700 V IDM Drain Current Pulsed (7) FSB117H 4.0 A FSB127H 8.0 FSB147H(9) 9.6 EAS Single Pulsed Avalanche Energy (8) FSB117H 50 mJ FSB127H 140 FSB147H 120 VDD DC Supply Voltage 30 V VFB FB Pin Input Voltage -0.3 7.0 V VIPK IPK Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 700 V PD Power Dissipation (TA＜50°C) 1.5 W TJ Operating Junction Temperature -40 Internally Limited(10) C TSTG Storage Temperature Range -55 +150 C TL Lead Soldering Temperature (Wave Soldering or IR, 10 Seconds) +260 C ESD Electrostatic Discharge Capability, All Pins Except HV Pin Human Body Model: JESD22-A114 5.50 kV Charged Device Model: JESD22-C101 2.00 Electrostatic Discharge Capability, All Pins Including HV Pin Human Body Model: JESD22-A114 3.00 Charged Device Model: JESD22-C101 1.25 Notes: 5. All voltage values, except differential voltages, ar e given with respect to the network ground terminal. 6. Stresses beyond those listed under Absolute Maximu m Ratings may cause permanent damage to the device. 7. Non-repetitive rating: pulse width is limited by maximum junction temperature. 8. L=51 mH, starting T J=25°C. 9. L=14 mH, starting T J=25°C. 10. Internally limited by Over-Temper ature Protection (OTP). Refer to TOTP. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit RHV Resistor Connect to HV Pin for Full Range Input Detection 150 250 k Ω Thermal Resistance Table Symbol Parameter Typ. Unit θJA Junction-to-Air Thermal Resistance 86 C/W ψJT Junction-to-Package Thermal Resistance (11) 20 C/W Note: 11. Measured on the package top surface.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 6 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)
Electrical Characteristics
VDD=15 V, TA=25C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit SenseFET Section(12) BVDSS Drain-Source Breakdown Voltage I D=250µA, VGS=0 V 700 V IDSS Zero-Gate-Voltage Drain Current VDS=700 V, VGS=0 V 50 μA VDS=560 V, VGS=0 V, TC=125C 200 RDS(ON) Drain-Source On-State Resistance(13) FSB117H VGS=10 V, ID=0.5 A 8.8 11.0 Ω FSB127H 6.0 7.2 FSB147H V GS=10 V, ID=2.5 A 2.3 2.7 CISS Input Capacitance FSB117H VGS=0 V, VDS=25 V, f=1 MHz 250 325 pF FSB127H 550 715 FSB147H 450 500 COSS Output Capacitance FSB117H VGS=0 V, VDS=25 V, f=1 MHz 25 33 pF FSB127H 38 50 FSB147H 60 72 CRSS Reverse Transfer Capacitance FSB117H VGS=0 V, VDS=25 V, f=1 MHz 10 15 pF FSB127H 17 26 FSB147H 7 21 td(on) Turn-On Delay FSB117H VDS=350 V, ID=1.0 A 12 34 ns FSB127H 20 50 FSB147H 12 35 tr Rise Time FSB117H VDS=350 V, ID=1.0 A 4 18 ns FSB127H 15 40 FSB147H 20 50 td(off) Turn-Off Delay FSB117H VDS=350 V, ID=1.0 A 30 70 ns FSB127H 55 120 FSB147H 30 70 tf Fall Time FSB117H VDS=350 V, ID=1.0 A 10 30 ns FSB127H 25 60 FSB147H 16 42 Continued on the following page…
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 7 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) VDD=15 V, TA=25C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Control Section VDD Section VDD-ON UVLO Start Threshold Voltage 11 12 13 V VDD-OFF1 UVLO Stop Threshold Voltage 5 6 7 V VDD-OFF2 I DD-OLP Enable Threshold Voltage 8 9 10 V VDD-OLP VDD Voltage Threshold for HV Startup Turn- On at Protection Mode 5 6 7 V IDD-ST Startup Supply Current V DD-ON – 0.16 V 30 µA IDD-OP1 Operating Supply Current with Normal Switching Operation VDD=15 V, VFB=3 V 3.8 mA IDD-OP2 Operating Supply Current without Switching Operation VDD=15 V, VFB=1 V 1.8 mA IDD-OLP Internal Sinking Current VDD-OLP + 0.1 V 30 60 90 µA VDD-OVP V DD Over-Voltage Protection 27 28 29 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 70 140 210 µs HV Section IHV Supply Current Drawn from HV Pin HV=120 VDC, VDD=0 V with 10 µF 1.5 5.0 mA IHV-LC Leakage Current after Startup HV=700 V, VDD=VDD-OFF1+1 V 10 µA VAC-ON Brown-in Threshold Level (V DC) DC Voltage Applied to HV Pin through 200 kΩ Resistor 105 110 115 V VAC-OFF Brownout Threshold Level (VDC) V AC-ON-10 V tUVP Brownout Protection Time 0.8 1.2 1.6 s Oscillator Section fOSC Frequency in Nominal Mode Center Frequency 94 100 106 kHz Hopping Range ±4.0 ±6.0 ±8.0 tHOP Hopping Period(12) 20 ms fOSC-G Green-Mode Frequency 20 23 26 kHz fDV Frequency Variation vs. VDD Deviation V DD=11 V to 22 V 5 % fDT Frequency Variation vs. Temperature Deviation(12) TA=-40 to 105°C 5 % Continued on the following page…
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 8 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) VDD=15 V, TA=25C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Feedback Input Section AV Internal Voltage Dividing Factor of FB Pin(12) 1/4.5 1/4.0 1/3.5 V/V ZFB Pull-Up Impedance of FB Pin 15 21 27 k Ω VFB-OPEN FB Pin Pull-Up Voltage FB Pin Open 5.2 5.4 5.6 V VFB-OLP FB Voltage Threshold to Trigger Open-Loop Protection 4.3 4.6 4.9 V tD-OLP Delay of FB Pin Open-Loop Protection 46 56 66 ms VFB-N FB Voltage Threshold to Exit Green Mode VFB is Rising 2.4 2.6 2.8 V VFB-G FB Voltage Threshold to enter Green Mode V FB is Falling V FB-N-0.2 V VFB-ZDC FB Voltage Threshold to Enter Zero-Duty State VFB is Falling 1.95 2.05 2.15 V VFB-ZDCR FB Voltage Threshold to Exit Zero-Duty State VFB is Rising VFB-ZDC +0.1 V IPK Pin Section VIPK-OPEN IPK Pin Open Voltage 3.0 3.5 4.0 V VIPK-H Internal Upper Clamping Voltage of IPK Pin 3 (12) V VIPK-L Internal Lower Clamping Voltage of IPK Pin 1.5(12) V IPK Internal Current Source of IPK Pin TA=-40 to 105°C, VIPK=2.25 V 45 50 55 µA ILMT-FL-H Current Limit Plateau when I PK Pin Voltage is Internally Clamped to Upper Limit FSB117H V IPK=3 V, Duty>40% 0.72 0.80 0.88 A FSB127H 0.90 1.00 1.10 FSB147H 1.35 1.50 1.65 ILMT-VA-H Initial Current Limit when I PK Pin Voltage is Internally Clamped to Upper Limit FSB117H VIPK=3 V, Duty=0% ILMT-FL-H -0.20 A FSB127H ILMT-FL-H -0.25 FSB147H ILMT-FL-H - 0.37 ILMT-FL-L Current Limit Plateau when I PK Pin Voltage is Internally Clamped to Lower Limit FSB117H V IPK=1.5 V, Duty>40% 0.36 0.40 0.44 A FSB127H 0.45 0.50 0.55 FSB147H 0.67 0.75 0.83 ILMT-VA-L Initial Current Limit when I PK Pin Voltage is Internally Clamped to Lower Limit FSB117H VIPK=1.5 V, Duty=0% ILMT-FL-L -0.10 A FSB127H ILMT-FL-L -0.12 FSB147H ILMT-FL-L - 0.18 Continued on the following page…
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 9 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™) Electrical Characteristics (Continued) VDD=15 V, TA=25°C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Current-Sense Section(14) tPD Current Limit Turn-Off Delay 100 200 ns tLEB Leading-Edge Blanking Time 230 280 330 ns tSS Soft-Start Time (12) 5 ms GATE Section(14) DCYMAX Maximum Duty Cycle 70 % Over-Temperature Protection Section (OTP) TOTP Junction Temperature to trigger OTP(12) 135 142 150 °C ∆TOTP Hysteresis of OTP (12) 25 °C Notes: 12. Guaranteed by design; not 100% tested in production. 13. Pulse test: pulse width ≤ 300 µs, duty ≤ 2%. 14. These parameters, although guarante ed, are tested in wafer-sort process.
Figure 26. Burst-Mode Operation
6 V, the protection is re set and HV startup circuit
charges VDD up to 12 V, allowing re-startup. feedback loop is open due to a soldering defect. Figure 27. OLP Operation applied to prevent false triggering by switching noise. temperature, the FSB-series resumes normal operation. and V DD is charged up by the HV startup circuit. VDD reaches 12 V, the IC resumes switching operation. Figure 28. Two-Level UVLO
Figure 29. Schematic of Typical Application Circuit
Figure 30. Transformer Specification
MOLD FLASH, AND TIE BAR EXTRUSIONS. E) DRAWING FILENAME AND REVSION: MKT-N08MREV1. Figure 31. 8-Pin, Dual In-Line Package (DIP) warranty therein, which covers Fairchild products. http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FSB117H / FSB127H / FSB147H • Rev. 1.0.7 18 FSB117H / FSB127H / FSB147H — mWSaver™ Fairchild Power Switch (FPS™)