AVC8T245PWR-D

SN74AVC8T245_17 TI1 | Alldatasheet

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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AVC8T245 SCES517J – DECEMBER 2003– REVISED MARCH 2017 SN74AVC8T2458-BitDual-SupplyBusTransceiverWithConfigurableVoltageTranslation and3-StateOutputs

1 Features

1• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

ESD Protection Exceeds JESD 22 – 8000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
VCC Isolation Feature – If Either VCC Input Is at GND, All I/O Ports Are in the High-Impedance State
Ioff Supports Partial Power-Down Mode Operation
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.4-V to 3.6-V Power-Supply Range
I/Os Are 4.6-V Tolerant
Maximum Data Rates – 170 Mbps (VCCA < 1.8 V or VCCB < 1.8 V) – 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)

2 Applications

Personal Electronic
Industrial
Enterprise
Telecom Logic Diagram (Positive Logic)

3 Description

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC8T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. The device is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of nodes. The SN74AVC8T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated. The SN74AVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA. The SN74AVC8T245 solution is compatible with a single-supply system and can be replaced later with a '245 function, with minimal printed circuit board redesign. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, thus preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74AVC8T245 VQFN (24) 3.50 mm x 5.50 mm TSSOP (24) 4.40 mm x 7.80 mm TVSOP (24) 4.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.

12.2 Receiving Notification of Documentation Updates 20

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (December 2014) to Revision J Page

Added Documentation Support section, Receiving Notification of Documentation Updates, and Community Changes from Revision H (February 2007) to Revision I Page
Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device

V GND CCBVCCA 1 1 VCCA DIR GND GND VCCB VCCB OE GND SN74AVC8T245 www.ti.com SCES517J – DECEMBER 2003– REVISED MARCH 2017 Product Folder Links: SN74AVC8T245 Submit Documentation FeedbackCopyright © 2003–2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME NO. A1 3 I/O Input/output A1. Referenced to VCCA. A2 4 I/O Input/output A2. Referenced to VCCA. A3 5 I/O Input/output A3. Referenced to VCCA. A4 6 I/O Input/output A4. Referenced to VCCA. A5 7 I/O Input/output A5. Referenced to VCCA. A6 8 I/O Input/output A6. Referenced to VCCA. A7 9 I/O Input/output A7. Referenced to VCCA. A8 10 I/O Input/output A8. Referenced to VCCA. B1 21 I/O Input/output B1. Referenced to VCCB. B2 20 I/O Input/output B2. Referenced to VCCB. B3 19 I/O Input/output B3. Referenced to VCCB. B4 18 I/O Input/output B4. Referenced to VCCB. B5 17 I/O Input/output B5. Referenced to VCCB. B6 16 I/O Input/output B6. Referenced to VCCB. B7 15 I/O Input/output B7. Referenced to VCCB. B8 14 I/O Input/output B8. Referenced to VCCB. DIR 2 I Direction-control signal GND 11, 12, 13 — Ground OE 22 I 3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to VCCA. VCCA 1 — A-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V VCCB 23, 24 — B-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V

SCES517J – DECEMBER 2003– REVISED MARCH 2017 www.ti.com Product Folder Links: SN74AVC8T245 Submit Documentation Feedback Copyright © 2003–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCCA, VCCB Supply voltage –0.5 4.6 V VI Input voltage(2) I/O ports (A port) –0.5 4.6 VI/O ports (B port) –0.5 4.6 Control inputs –0.5 4.6 VO Voltage range applied to any output in the high-impedance or power-off state(2) A port –0.5 4.6 V B port –0.5 4.6 VO Voltage range applied to any output in the high or low state(2) (3) A port –0.5 VCCA + 0.5 V B port –0.5 VCCB + 0.5 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±8000 VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 Machine model (MM) ±200

www.ti.com SCES517J – DECEMBER 2003– REVISED MARCH 2017 Product Folder Links: SN74AVC8T245 Submit Documentation FeedbackCopyright © 2003–2017, Texas Instruments Incorporated (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs, SCBA004.

6.3 Recommended Operating Conditions

See (1)(2)(3) VCCI VCCO MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB Supply voltage 1.2 3.6 V VIH High-level input voltage Data inputs 1.2 V to 1.95 V VCCI × 0.65 V1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 VIL Low-level input voltage Data inputs 1.2 V to 1.95 V VCCI × 0.35 V1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 VIH High-level input voltage DIR (referenced to VCCA) 1.2 V to 1.95 V VCCA × 0.65 V1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 VIL Low-level input voltage DIR (referenced to VCCA) 1.2 V to 1.95 V VCCA × 0.35 V1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 VI Input voltage 0 3.6 V VO Output voltage Active state 0 VCCO V 3-state 0 3.6 IOH High-level output current

1.2 V –3

1.4 V to 1.6 V –6 1.65 V to 1.95 V –8 2.3 V to 2.7 V –9 3 V to 3.6 V –12 IOL Low-level output current

1.2 V 3

1.4 V to 1.6 V 6 1.65 V to 1.95 V 8 2.3 V to 2.7 V 9 3 V to 3.6 V 12 Δt/Δv Input transition rise or fall rate 5 ns/V TA Operating free-air temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) SN74AVC8T245 UNITDGV PW RHL

24 PINS 24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 95.5 92 35 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27 29.3 39.9 °C/W RθJB Junction-to-board thermal resistance 48.9 46.7 13.8 °C/W ψJT Junction-to-top characterization parameter 0.7 1.5 0.3 °C/W ψJB Junction-to-board characterization parameter 48.5 46.2 13.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 1.4 °C/W

SCES517J – DECEMBER 2003– REVISED MARCH 2017 www.ti.com Product Folder Links: SN74AVC8T245 Submit Documentation Feedback Copyright © 2003–2017, Texas Instruments Incorporated (1) VCCO is the VCC associated with the output port. (2) VCCI is the VCC associated with the input port. (3) For I/O ports, the parameter IOZ includes the input leakage current.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)(1)(2) PARAMETER TEST CONDITIONS VCCA VCCB TA = 25°C –40°C to +85°C –40°C to +125°C UNIT MIN TYP MAX MIN MAX MIN MAX VOH IOH = –100 μA VI = VIH 0.2 V IOH = –3 mA 1.2 V 1.2 V 0.95 IOH = –6 mA 1.4 V 1.4 V 1.05 1 IOH = –8 mA 1.65 V 1.65 V 1.2 1.2 IOH = –9 mA 2.3 V 2.3 V 1.75 1.75 IOH = –12 mA 3 V 3 V 2.3 2.3 VOL IOL = 100 μA VI = VIL V IOL = 3 mA 1.2 V 1.2 V 0.15 IOL = 6 mA 1.4 V 1.4 V 0.35 0.35 IOL = 8 mA 1.65 V 1.65 V 0.45 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 0.55 IOL = 12 mA 3 V 3 V 0.7 0.7 II Control Ioff A or B port VI or VO = 0 to 3.6 V 0 V 0 V to 3.6 V –1 ±0.1 1 –5 5 ±5 μA 0 V to 3.6 V 0 V –1 ±0.1 1 –5 5 ±5 IOZ(3) A or B port VO = VCCO or GND, VI = VCCI or GND, OE = VIH ICCA VI = VCCI or GND, IO = 0 1.2 V to 3.6 V 1.2 V to 3.6 V 15 15 μA0 V 3.6 V –2 –2

3.6 V 0 V 15 15

VI = VCCI or GND, IO = 0 1.2 V to 3.6 V 1.2 V to 3.6 V 15 15 μA0 V 3.6 V 15 15

3.6 V 0 V –2 –2

VI = VCCI or GND, IO = 0 1.2 V to 3.6 V 1.2 V to 3.6 V 25 25 μA Ci Control Cio A or B port VO = 3.3 V or GND 3.3 V 3.3 V 6 7 pF

www.ti.com SCES517J – DECEMBER 2003– REVISED MARCH 2017 Product Folder Links: SN74AVC8T245 Submit Documentation FeedbackCopyright © 2003–2017, Texas Instruments Incorporated 6.6 Switching Characteristics, VCCA = 1.2 V over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT TYP TYP tPLH, tPHL A B VCCB = 1.2 V 3.1 3.1 ns VCCB = 1.5 V 2.6 2.6 VCCB = 1.8 V 2.5 2.5 VCCB = 2.5 V 3 3 VCCB = 3.3 V 3.5 3.5 tPLH, tPHL B A VCCB = 1.2 V 3.1 3.1 ns VCCB = 1.5 V 2.7 2.7 VCCB = 1.8 V 2.5 2.5 VCCB = 2.5 V 2.4 2.4 VCCB = 3.3 V 2.3 2.3 tPZH, tPZL OE A VCCB = 1.2 V 5.3 5.3 ns VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V tPZH, tPZL OE B VCCB = 1.2 V 5.1 5.1 ns VCCB = 1.5 V 4 4 VCCB = 1.8 V 3.5 3.5 VCCB = 2.5 V 3.2 3.2 VCCB = 3.3 V 3.1 3.1 tPHZ, tPLZ OE A VCCB = 1.2 V 4.8 4.8 ns VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V tPHZ, tPLZ OE B VCCB = 1.2 V 4.7 4.7 ns VCCB = 1.5 V 4 4 VCCB = 1.8 V 4.1 4.1 VCCB = 2.5 V 4.3 4.3 VCCB = 3.3 V 5.1 5.1 6.7 Switching Characteristics, VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPLH, tPHL A B VCCB = 1.2 V 2.7 3.1 ns tPLH, tPHL B A VCCB = 1.2 V 2.6 3.1 ns

SCES517J – DECEMBER 2003– REVISED MARCH 2017 www.ti.com Product Folder Links: SN74AVC8T245 Submit Documentation Feedback Copyright © 2003–2017, Texas Instruments Incorporated Switching Characteristics, VCCA = 1.5 V ± 0.1 V (continued) over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPZH, tPZL OE A VCCB = 1.2 V 3.7 5.3 ns tPZH, tPZL OE B VCCB = 1.2 V 4.8 5.1 ns tPHZ, tPLZ OE A VCCB = 1.2 V 3.1 4.8 ns tPHZ, tPLZ OE B VCCB = 1.2 V 4.1 4.7 ns 6.8 Switching Characteristics, VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPLH, tPHL A B VCCB = 1.2 V 2.5 2.5 ns tPLH, tPHL B A VCCB = 1.2 V 2.5 2.5 ns tPZH, tPZL OE A VCCB = 1.2 V 3 3 ns

www.ti.com SCES517J – DECEMBER 2003– REVISED MARCH 2017 Product Folder Links: SN74AVC8T245 Submit Documentation FeedbackCopyright © 2003–2017, Texas Instruments Incorporated Switching Characteristics, VCCA = 1.8 V ± 0.15 V (continued) over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPZH, tPZL OE B VCCB = 1.2 V 4.6 4.6 ns VCCB = 1.8 V ± 0.15 V 1 6.7 0.5 17 tPHZ, tPLZ OE A VCCB = 1.2 V 2.8 2.8 ns tPHZ, tPLZ OE B VCCB = 1.2 V 3.9 3.9 ns 6.9 Switching Characteristics, VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPLH, tPHL A B VCCB = 1.2 V 2.4 2.4 ns tPLH, tPHL B A VCCB = 1.2 V 3 3 ns tPZH, tPZL OE A VCCB = 1.2 V 2.2 2.2 ns tPZH, tPZL OE B VCCB = 1.2 V 4.5 4.5 ns

SCES517J – DECEMBER 2003– REVISED MARCH 2017 www.ti.com Product Folder Links: SN74AVC8T245 Submit Documentation Feedback Copyright © 2003–2017, Texas Instruments Incorporated Switching Characteristics, VCCA = 2.5 V ± 0.2 V (continued) over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPHZ, tPLZ OE A VCCB = 1.2 V 1.8 1.8 ns tPHZ, tPLZ OE B VCCB = 1.2 V 3.6 3.6 ns 6.10 Switching Characteristics, VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 10) PARAMETER FROM (INPUT) TO (OUTPUT) VCCB TA = –40°C to +85°C TA = –40°C to +125°C UNIT MIN TYP MAX MIN TYP MAX tPLH, tPHL A B VCCB = 1.2 V 2.3 2.3 ns VCCB = 1.8 V ± 0.15 V tPLH 0.5 3.7 0.5 11.1 tPHL 0.5 3.3 0.5 11.1 tPLH, tPHL B A VCCB = 1.2 V 3.5 3.5 ns tPZH, tPZL OE A VCCB = 1.2 V 2 2 ns tPZH, tPZL OE B VCCB = 1.2 V 4.5 4.5 ns tPHZ, tPLZ OE A VCCB = 1.2 V 1.7 1.7 ns

6.11 Operating Characteristics

Table 1. Typical Total Static Power Consumption (ICCA + ICCB)

6.12 Typical Characteristics

Figure 1. Typical Propagation Delay (A to B) vs Load Figure 2. Typical Propagation Delay (A to B) vs Load Figure 3. Typical Propagation Delay (A to B) vs Load Figure 4. Typical Propagation Delay (A to B) vs Load Figure 5. Typical Propagation Delay (A to B) vs Load Figure 6. Typical Propagation Delay (A to B) vs Load

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 W , dv/dt≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. t PLH and tPHL are the same as tpd. H. V CCI is the VCC associated with the input port. I. V CCO is the VCC associated with the output port.

7 Parameter Measurement Information

Figure 10. Load Circuit and Voltage Waveforms

8 Detailed Description

8.1 Overview

The SN74AVC8T245 is an 8-bit, dual-supply noninverting transceiver with bidirectional voltage level translation. A when OE is set to low. When OE is set to high, both A and B are in the high-impedance state.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.2 Support High-Speed Translation

when the device power supply is more than 1.8 V.

8.3.3 Ioff Supports Partial-Power-Down Mode Operation

Ioff prevents backflow current by disabling I/O output circuits when device is in partial power-down mode.

8.4 Device Functional Modes

(VCCB). The signal translation between 1.2 V and 3.6 V requires direction control and output enable control. transmission is from B to A. When OE is high, both output ports will be high-impedance. Table 2. Function Table (Each

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

device voltage power supply is more than 1.8 V.

9.2 Typical Application

Figure 11. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 3. Table 3. Design Parameters

9.2.2 Detailed Design Procedure

Input voltage range – Use the supply voltage of the device that is driving the SN74AVC8T245 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
Output voltage range – Use the supply voltage of the device that the SN74AVC8T245 device is driving to determine the output voltage range.

9.2.3 Application Curve

Figure 12. Translation Up (1.2 V to 3.3 V) at 2.5 MHz

10 Power Supply Recommendations

The SN74AVC8T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation The output-enable OE input circuit is designed so that it is supplied by VCCA and when the OE input is high, all outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by the current-sinking capability of the driver.

11 GND B8 10

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.

Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements.

11.2 Layout Example

Figure 13. SN74AVC8T245 Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following: Implications of Slow or Floating CMOS Inputs, SCBA004

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples 74AVC8T245DGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 74AVC8T245DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 74AVC8T245RHLRG4 ACTIVE VQFN RHL 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 WE245 AVC8T245PWR-D ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 HPA00720RHLR ACTIVE VQFN RHL 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 WE245 SN74AVC8T245DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 WE245 SN74AVC8T245RHLR ACTIVE VQFN RHL 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 WE245 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 15-Apr-2017 Addendum-Page 2 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AVC8T245 :

Automotive: SN74AVC8T245-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC8T245DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74AVC8T245PWR TSSOP PW 24 2000 367.0 367.0 38.0 SN74AVC8T245RHLR VQFN RHL 24 1000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2017 Pack Materials-Page 2

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

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Summary

8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs

Description