AV775C

AD775 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 8-Bit 20 MSPS, 60 mW Sampling A/D Converter AD775 Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

CMOS 8-Bit 20 MSPS Sampling A/D Converter Low Power Dissipation: 60 mW +5 V Single Supply Operation Differential Nonlinearity: 0.3 LSB Differential Gain: 1% Differential Phase: 0.5 Degrees Three-State Outputs On-Chip Reference Bias Resistors Adjustable Reference Input Video Industry Standard Pinout Small Packages: 24-Pin 300 Mil SOIC Surface Mount 24-Pin 400 Mil Plastic DIP PRODUCT DESCRIPTION The AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling analog-to-digital converter (ADC). The AD775 features a built- in sampling function and on-chip reference bias resistors to pro- vide a complete 8-bit ADC solution. The AD775 utilizes a pipelined/ping pong two-step flash architecture to provide high sampling rates (up to 35 MHz) while maintaining very low power consumption (60 mW). Its combination of excellent DNL, fast sampling rate, low dif- ferential gain and phase errors, extremely low power dissipation, and single +5 V supply operation make it ideally suited for a variety of video and image acquisition applications, including portable equipment. The AD775’s reference ladder may be con- nected in a variety of configurations to accommodate different input ranges. The low input capacitance (11 pF typical) provides an easy-to-drive input load compared to conventional flash converters. The AD775 is offered in both 300 mil SOIC and 400 mil DIP plastic packages, and is designed to operate over an extended commercial temperature range (–20 °C to +75°C). PRODUCT HIGHLIGHTS Low Power: The AD775 has a typical supply current of 12 mA, for a power consumption of 60 mW. Reference ladder current is also low: 6.6 mA typical, minimizing the reference power consumption. Complete Solution: The AD775’s switched capacitor design features an inherent sample/hold function: no external SHA is required. On-chip reference bias resistors are included to allow a supply-based reference to be generated without any external resistors. Excellent Differential Nonlinearity: The AD775 features a typical DNL of 0.3 LSBs, with a maximum limit of 0.5 LSBs. No missing codes is guaranteed. Single +5 V Supply Operation: The AD775 is designed to oper- ate on a single +5 V supply, and the reference ladder may be configured to accommodate analog inputs inclusive of ground. Low Input Capacitance: The 11 pF input capacitance of the AD775 can significantly decrease the cost and complexity of input driving circuitry, compared with conventional 8-bit flash ADCs. 14 13 1119 21 24 CLOCK LOGIC FINE COMPARATORS BANK B FINE COMPARATORS BANK A COARSE COMPARATORS CORRECTION LOGIC AV DD AV SS 3-STATE OUTPUT LATCHES D7 (MSB) D0 (LSB) RREF SWITCH MATRIX VRTS V RT V RB V RBS OE AV SS CLK DV SS AV DD V IN DV DD AD775 255 LSB MULTIPLEXOR

REV. 0–2– AD775–SPECIFICATIONS AD775J Parameter Min Typ Max Units RESOLUTION 8 Bits DC ACCURACY Integral Nonlinearity (INL) +0.5 1.3 LSB Differential Nonlinearity (DNL) ± 0.3 ± 0.5 LSB No Missing Codes GUARANTEED Offset To Top of Ladder V RT –10 –35 –60 mV To Bottom of Ladder V RB 0 +15 +45 mV VIDEO ACCURACY1 Differential Gain Error 1.0 % Differential Phase Error 0.5 Degrees ANALOG INPUT Input Range (VRT–VRB) 2.0 V p-p Input Capacitance 11 pF AC SPECIFICATIONS2 Signal-to-Noise and Distortion (S/(N + D)) fIN = 1 MHz 47 dB fIN = 5 MHz 41 dB Total Harmonic Distortion (THD) fIN = 1 MHz –51 dB fIN = 5 MHz –42 dB REFERENCE INPUT Reference Input Resistance (R REF) 230 300 450 Ω Case 1: VRT = VRTS, VRB = VRBS Reference Bottom Voltage (V RB) 0.60 0.64 0.68 V Reference Span (VRT–VRB) 1.96 2.09 2.21 V Reference Ladder Current (I REF) 4.4 7.0 9.6 mA Case 2: VRT = VRTS, VRB = AVSS Reference Span (VRT–VRB) 2.25 2.39 2.53 V Reference Ladder Current (I REF) 581 1 m A POWER SUPPLIES Operating Voltages AVDD +4.75 +5.25 Volts DVDD +4.75 +5.25 Volts Operating Current IAVDD 9.5 mA IDVDD 2.5 mA IAVDD + IDVDD 12 17 mA POWER CONSUMPTION 60 85 mW TEMPERATURE RANGE Operating –20 +75 °C NOTES 1NSTC 40 IRE modulation ramp, CLOCK = 14.3 MSPS. 2fIN amplitude = 0.3 dB full scale. Specifications subject to change without notice. See Definition of Specifications for additional information. (TA = +258C with AVDD, DVDD = +5 V, AVSS, DVSS = 0 V, VRT = 2.6 V, VRB = +0.6 V, CLOCK = 20 MHz unless otherwise noted)

Specifications subject to change without notice. Figure 1. AD775 Timing Diagram

REV. 0–4– WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD775 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN DESCRIPTION Pin No. Symbol Type Name and Function

1 OE DI OE = Low OE = High

Normal Operating Mode. High Impedance Outputs. 2, 24 DV SS P Digital Ground. Note: DV SS and AVSS pins should share a common ground plane on the circuit board. 3 D0 (LSB) DO Least Significant Bit, Data Bit 0. 4–9 D1–D6 DO Data Bits 1 Through 6. 10 D7 (MSB) DO Most Significant Bit, Data Bit 7. 11, 13 DV DD P +5 V Digital Supply. Note: DV DD and AVDD pins should share a common supply on the circuit board. 12 CLK DI Clock Input. 16 V RTS AI Reference Top Bias. Short to V RT for Self-Bias. 17 V RT AI Reference Ladder Top. 23 V RB AI Reference Ladder Bottom. 22 V RBS AI Reference Bottom Bias. Short to V RB for Self-Bias. 14, 15, 18 AV DD P +5 V Analog Supply. Note: DV DD and AVDD pins should share a common supply within 0.5 inches of the AD775. 19 V IN AI Analog Input. Input Span = V RT–VRB. 20, 21 AV SS P Analog Ground. Note: DV SS and AVSS pins should share a common ground within 0.5 inches of the AD775. NOTE Type: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power. PIN CONFIGURATION (DIP and SOIC) MAXIMUM RATINGS* *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option AD775JN –20 °C to +75°C 24-Pin 400 Mil Plastic DIP N-24B AD775JR –20 °C to +75°C 24-Pin 300 Mil SOIC R-24A

of each particular code to the true straight line. defined as the deviation from this ideal. quency signal on which it is superimposed. data is provided every clock cycle. pressed as a percentage or in decibels. pling and the corresponding converted output is 2.5 clock cycles. ladder to be conveniently biased by the supply voltage. der and is typically +0.5 LSB. Figure 8. Reference Configuration: 0.64 V to 2.73 V configurations for these resistors are shown in Figures 8 and 9.

REV. 0 –9– POWER SUPPLY CONNECTIONS AND DECOUPLING The analog and digital supplies of the AD775 have been sepa- rate to prevent the typically large transients associated with the on-chip digital circuitry from coupling into the analog supplies (AV DD, AVSS). However, in order to avoid possible latch-up conditions, AVDD and DVDD must share a common supply external to the part, preferably a common source somewhere on the PC board. Each supply should be decoupled by a 0.1 µF capacitor located as close to the device pin as possible. Surface-mount capacitors, by virtue of their low parasitic inductance, are preferable to through-hole types. A larger capacitor (10 µF electrolytic) should be located somewhere on the board to help decouple large, low frequency supply noise. For specific layout informa- tion, refer to the AD775 Evaluation Board section of the data sheet. C15 D C13 A TP4 VRT C12 +5V D C18 +5VA C14 TP3 VRB 1AD822 390pF R10 1/2 U2 10k 8 C9 A+5VA AD822 7 390pF 201/2 U2 10k 5 4 A A 10k A A GND 74ALS541 D D C22 +5V VCC TP13 ENABLE J10 D D D D P2-40 PIN IDC A 10k D 3 2 VIN VOUT GND AD680 A +5VA A 499 A R2 500 500 R11 75R12 4.99k 6AD817 A 22mF R13 20 Q1 2N3904 TP2 49.9 A TP1 ANALOG INPUT VEE VCC VEE A VCC R14 500 +5VA R15

499 CR1

+5VA A 10pF TP5 VIN TP10 R16 49.9 D TP9 CLOCK ( ) DV SS DV DD CLK OE VRB AV SS VIN AV DD AV SS VRT VRTS AV DD AV DD DV DD DV SS VRBS AD775 = 47mF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE NOTED = 0.1mF CERAMIC CAPACITOR UNLESS OTHERWISE NOTED NOTES VIN VOUT GND 78M05 C11 D C21 TP12 TP6 +5V +5VA A VCC C16 C20C19 TP7 TP8 TP11 VCC VEE 1 2 5 6 VEE Figure 17. AD775 Evaluation Board Schematic

APPLICATIONS

Figures 17 through 22 show the schematic and printed circuit board (PCB) layout for the AD775 evaluation board. Referring to Figure 17, the input signal is buffered by U3, an AD817 op amp configured as a unity-gain follower. The signal is then ac- coupled and dc-biased by adjusting potentiometer R14. Video and imaging applications would typically use a dc-restoration circuit instead of the manual potentiometer adjustment. Q1, an emitter-follower, buffers the input signal and provides ample current to drive a simple low-pass filter. The filtering is included to limit wideband noise and highlight the fact that the AD775 can be driven from a nonzero source impedance. The reference circuit is similar to the one shown in Figure 11 with the exception that R1 and R2 allow precise adjustment of

REV. 0–10– Table I. Components List Reference Designator Description Quantity R1, R2, R14 Potentiometer 3 R3, R15 Resistor, 1%, 499 Ω 2 R4, R13, R16 Resistor, 1%, 49.9 Ω 3 R5, R10 Resistor, 1%, 20 Ω 2 R6–R9 Resistor, 1%, 10 k Ω 4 R11 Resistor, 1%, 75 Ω 1 R12 Resistor, 1%, 4.99 k Ω 1 CR1 Diode, 1N4148 1 C1, C2, C5, C6, C9, C12–C15, C18 C20, C22, C23 Ceramic Cap, Z5U, 0.1 µF1 3 C3, C4 Capacitor, Mica, 390 pF 2 C7 Capacitor, Mica, 10 pF 1 C8 Capacitor, Tantalum, 22 µF, 16 V 1 C11, C16, C19, C21 Capacitor, Alum. Electrolytic, 47 µF, 16 V 4 Q1 Transistor, 2N3904 1 U1 AD680JT 1 U2 AD822AN 1 U3 AD817AN 1 U4 78M05 1 U5 AD775 1 U6 74ALS541N 1 U7 74HC04N 1 J1, J8 BNC Jack 2 VRT and VRB. Note that the VRT and VRB traces (see Figures 19 and 20) are run in parallel and in the same proximity. Any noise coupling is likely to be common mode to both signals and would result in an offset error but not a gain error. The entire reference circuit is powered by a single +5 V supply. The minimum volt- age for V RB is determined by the impedance of the AD822 out- put stage and the amount of current flowing through the internal resistor ladder of the AD775. The sampling clock is buffered by U7, a 74HC04 inverter. It is recommended that the output loading of the inverter is mini- mized in order to maintain fast transition times on the clock. An additional inverter is used to provide a buffered clock signal whose rising edges indicate that data is valid. A 74ALS541 buffers the eight digital data outputs of the AD775 to improve the load driving capability. The multilayer PCB board layout shows some of the important design guidelines recommended for the AD775. The most im- portant aspect is the power and ground distribution. While the AD775 has separate analog and digital power and ground pins, the AD775 should be treated as an entirely analog component. The ground plane is joined close to the ADC in order to main- tain a low potential difference across the analog and digital ground pins. Because the power and grounds are derived from a common point, a slit in the ground plane is used to minimize any interaction between the analog and digital return currents. The power for the AD775, AV DD and DVDD, are derived from the same supply. Separate traces are run to AV DD and DVDD and joined together at the source. While not used on the evalua- tion board, a ferrite bead or inductor can effectively isolate noise generated by digital circuitry such as the output buffers. In cases where only a single supply is available, the inductor should not be placed between AV DD and DVDD. Instead, both supplies of the AD775 should be connected together and isolated from entirely digital components.

Figure 22. Power Plane PCB Layout (Not to Scale) Dimensions shown in inches and (mm).