74ALVT16899 PHILIPS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 20

Technical content

/C0109 /C0110 /C0114 74ALVT16899 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Product specification IC23 Data Handbook

1998 Jun 30

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

21998 Jun 30 853-2090-19651

FEATURES

  • Symmetrical (A and B bus functions are identical)
  • Selectable generate parity or ”feed-through” parity for A-to-B and B-to-A directions
  • Independent transparent latches for A-to-B and B-to-A directions
  • Selectable ODD/EVEN parity
  • Continuously checks parity of both A bus and B bus latches as ERRA and ERRB
  • Open-collector ERR output
  • Ability to simultaneously generate and check parity
  • Can simultaneously read/latch A and B bus data
  • Output capability: +64 mA/–32mA
  • Latch-up protection exceeds 500mA per Jedec Std 17
  • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
  • Power up 3-State
  • Power-up reset
  • No bus current loading when output is tied to 5 V bus
  • Live insertion/extraction permitted
  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

DESCRIPTION

The 74ALVT16899 is a high-performance BiCMOS product designed for VCC operation at 2.5V or 3.3V with I/O compatibility up to 5V. The 74ALVT16899 is a 16-bit to 16-bit parity transceiver with separate transparent latches for the A bus and B bus. Either bus can generate or check parity. The parity bit can be fed-through with no change or the generated parity can be substituted with the SEL input. The 74ALVT16899 features independent latch enables for the A and B bus latches, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. FUNCTIONAL DESCRIPTION: The 74ALVT16899 has three principal modes of operation which are outlined below. All modes apply to both the A-to-B and B-to-A directions. Transparent latch, Generate parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are High and the Mode Select (SEL ) is Low, the parity generated from A0-A7 and B0-B7 can be checked and monitored by ERRA and ERRB . (Fault detection on both input and output buses.) Transparent latch, Feed-through parity, Check A and B bus parity: Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is High. Parity is still generated and checked as ERRA and ERRB and can be used as an interrupt to signal a data/parity bit error to the CPU. Latched input, Generate/Feed-through parity, Check A (and B) bus parity: Independent latch enables (LEA and LEB) allow other permutations of:

  • Transparent latch / 1 bus latched / both buses latched
  • Feed-through parity / generate parity
  • Check in bus parity / check out bus parity / check in and out bus parity QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS TYPICAL UNITSYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V 2.5 V 3.3 V UNIT tPLH tPHL Propagation delay An to Bn or Bn to An C L = 50pF 2.0 2.2 1.5 1.7 ns tPLH tPHL Propagation delay An to ERRA C L = 50pF 9.8 7.0 7.8 5.1 ns C IN Input capacitance VI = 0V or VCC 3 3 pF C I/O Output capacitance Outputs disabled; VO = 0V or VCC 9 9 pF ICCZ Quiescent supply current Outputs disabled 40 70 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT16899 AV16899 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT16899 DGG AV16899 DGG SOT364-1

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 3

27, 25, 24, 23, 22, 20, 19, 18 Latched A bus 3-State inputs/outputs 1B0 - 1B7 2B0 - 2B7 54, 52, 51, 50, 49, 47, 46, 45 30, 32, 33, 34, 35, 37, 38, 39 Latched B bus 3-State inputs/outputs 1APAR 2APAR 13, 17 A bus parity 3-State input/output 1BPAR 2BPAR 44, 40 B bus parity 3-State input/output ODD/EVEN 1 Parity select input (Low for EVEN parity) OEA , OEB 2, 29 Output enable inputs (gate A to B, B to A) SEL 56 Mode select input (Low for generate) LEA, LEB 55, 28 Latch enable inputs (transparent High) 1ERRA , 1ERRB 2ERRA , 2ERRB 14, 43, 16, 41 Error signal outputs (active-Low) GND 4, 15, 26, 31, 42, 53 Ground (0V) VCC 9, 21, 36, 48 Positive supply voltage

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 4

1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 54 52 51 50 49 47 46 45 LEA SEL LEB ODD/EVEN 1ERRA 1ERRB 1APAR 1BPAR

29 OEB

2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 30 32 33 34 35 37 38 39 LEA SEL LEB ODD/EVEN 2ERRA 2ERRB 2APAR 2BPAR PARITY AND ERROR FUNCTION TABLE INPUTS OUTPUTS SEL ODD/EVEN xPAR (A or B) Σ of High Inputs xPAR (B or A) ERRt ERRr * PARITY MODES H H H Even Odd H H H L H L Odd H H L Even Odd L L L H L H Mode Feed-through/check parity H L H Even Odd H H L H L H Even H L L Even Odd L L H L H L Mode L H H Even Odd H L H L H H Odd L H L Even Odd H L L H H H Mode Generate parity L L H Even Odd L H L H H H Even L L L Even Odd L H H L H H Mode H = High voltage level L = Low voltage level t = Transmit–if the data path is from A→ B then ERRt is ERRA r = Receive–if the data path is from A→ B then ERRr is ERRB * Blocked if latch is not transparent

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 5

9–bit Output Buffer OE 9–bit Output Buffer 9–bit Transparent Latch LE Parity Generator Parity Generator mux OE 9–bit Transparent Latch LE OEB LEA APAR OEA SEL ODD/ EVEN LEB BPAR ERRA ERRB SH00084 (1 of 2 parity blocks) FUNCTION TABLE INPUTS OPERATING MODE OEB OEA SEL LEA LEB H H X X X 3-State A bus and B bus (input A & B simultaneously) H L L L H B → A, transparent B latch, generate parity from B0 - B7, check B bus parity H L L H H B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity H L L X L B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity H L H X H B → A, transparent B latch, parity feed-through, check B bus parity H L H H H B → A, transparent A & B latch, parity feed-through, check A & B bus parity L H L H X A → B, transparent A latch, generate parity from A0 - A7, check A bus parity L H L H H A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity L H L L X A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity L H H H L A → B, transparent A latch, parity feed-through, check A bus parity L H H H H A → B, transparent A & B latch, parity feed-through, check A & B bus parity L L X X X Output to A bus and B bus (NOT ALLOWED) H = High voltage level L = Low voltage level X = Don’t care

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 6

ABSOLUTE MAXIMUM RATINGS 1, 2 SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage -0.5 to +4.6 V IIK DC input diode current VI < 0 -50 mA VI DC input voltage3 -0.5 to +7.0 V IOK DC output diode current VO < 0 -50 mA VOUT DC output voltage3 Output in Off or High state -0.5 to +7.0 V IOUT DC output current Output in Low state 128 mAIOUT DC out ut current Output in High state -64 mA Tstg Storage temperature range -65 to +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER 2.5V RANGE LIMITS 3.3V RANGE LIMITS UNITSYMBOL PARAMETER MIN MAX MIN MAX UNIT VCC DC supply voltage 2.3 2.7 3.0 3.6 V VI Input voltage 0 5.5 0 5.5 V VIH High-level input voltage 1.7 2.0 V VIL Input voltage 0.7 0.8 V IOH High-level output current –8 –32 mA IOL Low-level output current 8 32 mAIOL Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 24 64 mA Δt/Δv Input transition rise or fall rate; Outputs enabled 10 10 ns/V Tamb Operating free-air temperature range –40 +85 –40 +85 °C

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 7

DC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT MIN TYP 1 MAX VIK Input clamp voltage VCC = 3.0V; IIK = –18mA –0.85 –1.2 V VCC = 3.0V; IOL = 100µA 0.07 0.2 VCC = 3.0V; IOL = 64mA 0.4 0.55 VRST Power-up output low voltage6 VCC = 3.6V; IO = 1mA; VI = VCC or GND 0.55 V VCC = 3.6V; VI = VCC or GND Controlpins 0.1 ±1 VCC = 0 or 3.6V; VI = 5.5V Control ins 0.1 10 II Input leakage current VCC = 3.6V; VI = 5.5V 0.1 20 µA VCC = 3.6V; VI = VCC Data pins4 0.5 1 VCC = 3.6V; VI = 0V 0.1 -5 IOFF Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 ±100 µA Bus Hold current VCC = 3V; VI = 0.8V 75 130 IHOLD Bus Hold current Data inputs VCC = 3V; VI = 2.0V –75 –140 µA Data inputs VI = 0V to 3.6V; VCC = 3.6V7 ±500 IEX Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 3.0V 10 125 µA IPU/PD Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC ; VI = GND or VCC OE/OE = Don’t care 33 ±100 µA IOZH 3-State output High currentVCC = 3.6V; VO = 3.0V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 3.6V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA ICCH VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.05 0.1 ICCL Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 4.6 7.0 mA ICCZ VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 0.06 0.1 ΔICC Additional supply current per input pin2 VCC = 3V to 3.6V; One input at VCC –0.6V, Other inputs at VCC or GND 0.04 0.4 mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 8

AC CHARACTERISTICS (3.3V 0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω ; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V UNIT MIN TYP 1 MAX tPLH tPHL Propagation delay An to Bn or Bn to An 1 0.5 0.5 1.5 1.7 2.7 2.8 ns tPLH tPHL Propagation delay An to BPAR or Bn to APAR 4 2.5 2.0 5.0 4.6 8.0 7.3 ns tPLH tPHL Propagation delay An to ERRA or Bn to ERRB 5 2.5 2.5 7.8 5.1 11.5 8.5 ns tPLH tPHL Propagation delay APAR to BPAR or BPAR to APAR 3 1.0 1.0 2.9 3.0 6.9 6.4 ns tPLH tPHL Propagation delay APAR to ERRA or BPAR to ERRB 8 2.5 1.0 5.1 2.5 8.0 3.6 ns tPLH tPHL Propagation delay ODD/EVEN to APAR or BPAR 7 1.5 1.5 3.8 3.4 6.5 5.4 ns tPLH tPHL Propagation delay ODD/EVEN to ERRA or ERRB 6 2.5 1.5 6.6 4.0 10.0 6.6 ns tPLH tPHL Propagation delay SEL to APAR or BPAR 10 1.0 1.0 2.6 2.4 4.0 3.4 ns tPLH tPHL Propagation delay SEL to ERRA or ERRB 5 2.5 1.5 7.8 4.8 10.8 7.1 ns tPLH tPHL Propagation delay LEA to Bn or LEB to An 11 1.0 1.0 2.2 2.2 3.8 3.8 ns tPLH tPHL Propagation delay LEA to BPAR or LEB to APAR 11 2.5 2.0 5.3 4.9 8.5 7.6 ns tPLH tPHL Propagation delay LEA to ERRA or LEB to ERRB 9 2.5 2.5 7.4 5.6 11.0 9.2 ns tPZH tPZL Output enable time OEA to An, APAR or OEB to Bn, BPAR 13, 14 1.0 0.5 2.4 1.8 5.8 3.3 ns tPHZ tPLZ Output disable time OEA to An, APAR or OEB to Bn, BPAR 13, 14 2.5 1.0 5.2 2.4 8.0 3.5 ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC SETUP REQUIREMENTS (3.3V 0.3V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V UNIT MIN TYP ts(H) ts(L) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB 12 1.0 1.0 0.1 0.1 ns th(H) th(L) Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB 12 1.0 1.0 –0.1 0.1 ns tw (H) Pulse width, High LEA or LEB 12 1.0 – ns

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 9

DC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT MIN TYP 1 MAX VIK Input clamp voltage VCC = 2.3V; IIK = –18mA –0.85 –1.2 V VCC = 2.3V; IOL = 100µA 0.07 0.2 VOL Low-level output voltage VCC = 2.3V; IOL = 24mA 0.3 0.5 V VCC = 2.3V; IOL = 8mA 0.4 VRST Power-up output low voltage7 VCC = 2.7V; IO = 1mA; VI = VCC or GND 0.55 V VCC = 2.7V; VI = VCC or GND Controlpins 0.1 ±1 VCC = 0 or 2.7V; VI = 5.5V Control ins 0.1 10 II Input leakage current VCC = 2.7V; VI = 5.5V 0.1 20 µA VCC = 2.7V; VI = VCC Data pins4 0.1 10 VCC = 2.7V; VI = 0 0.1 -5 IOFF Off current VCC = 0V; VI or VO = 0 to 4.5V 0.1 ±100 µA IHOLD 6 Bus Hold current VCC = 2.3V; VI = 0.7V 115 µAIHOLD 6 Data inputs VCC = 2.3V; VI = 1.7V 10 µA IEX Current into an output in the High state when VO > VCC VO = 5.5V; VCC = 2.3V 10 125 µA IPU/PD Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC ; VI = GND or VCC ; OE/OE = Don’t care 33 ±100 µA IOZH 3-State output High currentVCC = 2.7V; VO = 2.3V; VI = VIL or VIH 0.5 5 µA IOZL 3-State output Low current VCC = 2.7V; VO = 0.5V; VI = VIL or VIH 0.5 –5 µA ICCH VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 0.04 0.1 ICCL Quiescent supply current VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 3.5 4.5 mA ICCZ VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05 0.04 0.1 ΔICC Additional supply current per input pin2 VCC = 2.3V to 2.7V; One input at VCC –0.6V, Other inputs at VCC or GND 0.04 0.4 mA NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 10

AC CHARACTERISTICS (2.5V 0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω ; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.5V ± 0.2V UNIT MIN TYP 1 MAX tPLH tPHL Propagation delay An to Bn or Bn to An 1 1.0 1.0 2.0 2.2 3.5 3.9 ns tPLH tPHL Propagation delay An to BPAR or Bn to APAR 4 3.0 3.0 7.0 6.5 10.5 10.2 ns tPLH tPHL Propagation delay An to ERRA or Bn to ERRB 5 4.5 3.5 9.8 7.0 14.5 11.5 ns tPLH tPHL Propagation delay APAR to BPAR or BPAR to APAR 3 1.0 1.0 3.0 3.5 4.3 5.5 ns tPLH tPHL Propagation delay APAR to ERRA or BPAR to ERRB 8 3.0 1.5 6.7 3.6 10.0 5.4 ns tPLH tPHL Propagation delay ODD/EVEN to APAR or BPAR 7 2.5 2.5 5.2 5.0 7.8 7.8 ns tPLH tPHL Propagation delay ODD/EVEN to ERRA or ERRB 6 4.0 4.0 8.6 8.1 12.0 10.6 ns tPLH tPHL Propagation delay SEL to APAR or BPAR 10 1.5 1.5 3.7 3.2 5.5 5.3 ns tPLH tPHL Propagation delay SEL to ERRA or ERRB 5 4.5 3.0 9.4 7.6 14.0 11.5 ns tPLH tPHL Propagation delay LEA to Bn or LEB to An 11 1.0 1.0 3.0 3.0 4.8 4.6 ns tPLH tPHL Propagation delay LEA to BPAR or LEB to APAR 11 2.5 2.5 7.5 7.4 12.2 11.2 ns tPLH tPHL Propagation delay LEA to ERRA or LEB to ERRB 9 4.5 3.5 9.7 8.5 15.0 13.4 ns tPZH tPZL Output enable time OEA to An, APAR or OEB to Bn, BPAR 13, 14 1.5 1.0 4.0 2.6 6.0 4.6 ns tPHZ tPLZ Output disable time OEA to An, APAR or OEB to Bn, BPAR 13, 14 1.5 1.0 4.5 3.7 6.5 5.0 ns NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. AC SETUP REQUIREMENTS (2.5V 0.2V RANGE) GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω ; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.5V ±0.2V UNIT MIN TYP ts(H) ts(L) Setup time, High or Low An, APAR to LEA or Bn, BPAR to LEB 12 –1.0 1.2 –0.4 0.4 ns th(H) th(L) Hold time, High or Low An, APAR to LEA or Bn, BPAR to LEB 12 –1.0 1.2 –0.4 0.5 ns tw (H) Pulse width, High LEA or LEB 12 1.0 – ns

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 11

VM = 1.5V or VCC /2 whichever is less; VIN = GND to 3.0V SW00160 nAx INPUT VM nYx OUTPUT tPHL tPLH VM VM VM 3.0V or VCC , whichever is less VOH VOL Waveform 1. Input (nAx) to Output (nYx) Propagation Delays nOE INPUT VM VM tPZH tPHZ nYx OUTPUT VOH VM VMnYx OUTPUT V OL tPZL tPLZ VX VY 3.0V or VCC whichever is less SW00204 Waveform 2. 3-State Output Enable and Disable Times An, APAR (Bn, BPAR) VM tPLH tPHL VM VM VM Bn, BPAR (An, APAR) SEL INPUT OUTPUT SA00293 Waveform 3. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR An (Bn) tPLH VM VM VM BPAR (APAR) LEA (LEB) INPUT OUTPUT ODD/EVEN SEL tPHL VMODD PARITY EVEN PARITY ODD PARITY NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00294 Waveform 4. Propagation Delay, An to BPAR or Bn to APAR

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 12

(Bn) tPHL VM VM VM ERRA (ERRB ) LEA (LEB) INPUT OUTPUT APAR (BPAR) ODD/EVEN tPLH VMODD PARITY EVEN PARITY ODD PARITY NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1 SA00295 SEL Waveform 5. Propagation Delay, An to ERRA or Bn to ERRB APAR (BPAR) VM tPLH tPHL VM VM VM ERRA (ERRB ) INPUT OUTPUT An (Bn) EVEN PARITY ODD/EVEN INPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output SA00296 Waveform 6. Propagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 13

(APAR) INPUT OUTPUT APAR (BPAR) SEL tPLH VM EVEN PARITY ODD/EVEN INPUT NOTE: Only even parity mode is shown, odd parity mode would cause inverted output An (Bn) SA00297 Waveform 7. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR APAR (BPAR) tPHL VM VM VM ERRA (ERRB ) INPUT OUTPUT tPLH VM EVEN PARITY ODD/EVEN INPUT An (Bn) NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00298 Waveform 8. Propagation Delay, APAR to ERRA or BPAR to ERRB

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 14

(Bn) INPUT APAR (BPAR) ODD/EVEN EVEN PARITY ODD PARITY EVEN PARITY LEA (LEB) tPHL VM ERRA (ERRB ) INPUT OUTPUT tPLH VM VM VM NOTE: Only odd parity mode is shown. Even parity mode would be with ODD/EVEN = o SA00299 Waveform 9. Propagation Delay, LEA to ERRA or LEB to ERRB An (Bn) tPHL VM VM VM BPAR (APAR) INPUT OUTPUT APAR (BPAR) ODD/EVEN tPLH VM EVEN PARITY SEL INPUT NOTE: Only even parity mode is shown with even parity. Odd parity mode would cause inverted output and odd parity mode would be with ODD/EVEN = 1 SA00300 Waveform 10. Propagation Delay, SEL to BPAR or SEL to APAR

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 15

APAR, An] (BPAR, Bn) INPUT SEL LEA (LEB) tPHL VM Bn, BPAR (An, APAR) INPUT OUTPUT tPLH VM VM SA00301 Waveform 11. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ VM APAR, BPAR, An, Bn VM VM VM VM VM LEA, LEB ts(H) th(H) ts(L) th(L) tw (H) VM SA00302 The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 12. Data Setup and Hold Times, Pulse Width High OEA , OEB VM tPZH tPHZ VOH –0.3V VM VM An, APAR, Bn, BPAR SA00303 Waveform 13. 3-State Output Enable Time to High Level and Output Disable Time from High Level OEA , OEB tPZL tPLZ VOL +0.3V An, APAR, Bn, BPAR VM VM VM SA00304 Waveform 14. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)

1998 Jun 30 16

tW 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tW AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS Rep. Rate tw tR tF ≤ 10MHz 500ns ≤ 2.5ns≤ 2.5ns Input Pulse Definition VCC FAMILY 74ALVT16 D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for Open Collector Outputs tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) Amplitude 3.0V or VCC , which ever is less R X SV01732 tPLZ/tPZL 6 V or VCC × 2 tPLH/tPHL open tPHZ /tPZH GND SWITCH POSITION R L = Load resistor; see AC CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. DEFINITIONS: VX OUTPUT RX VX ERROR 100 VCC All other 500 switch LOAD VALUES TEST SWITCH

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Philips Semiconductors Product specification 74ALVT16899

1998 Jun 30 17

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Philips Semiconductors Product specification 74ALVT16899

1998 Jun 30 18

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) Philips Semiconductors Product specification 74ALVT16899

1998 Jun 30 19

Philips Semiconductors Product specification 74ALVT168992.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State) yyyy mmm dd 20 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 05-96 Document order number: 9397-750-04066 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.