ATT3020-100T68I

ATT3000 ETC1 | Alldatasheet

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Technical content

Features

n High performance: — Up to 270 MHz toggle rates — 4-input LUT delays <2.7 ns n User-programmable gate arrays — Unlimited reprogrammability — Easy design iteration through in-system logic changes n Flexible array architecture: — Compatible arrays ranging from 1500 to 6000 gate logic complexity — Extensive register, combinatorial, and I/O capabilities — Low-skew clock nets — High fan-out signal distribution — Internal 3-state bus capabilities — TTL or CMOS input thresholds — On-chip oscillator amplifier n Standard product availability: — Low-power 0.55 µm CMOS, static memory technology — Pin-for-pin compatible with Xilinx* XC3000* and XC3100* families — Cost-effective for volume production — 100% factory pretested — Selectable configuration modes n ORCA ™ Foundry for ATT3000 Development System support n All FPGAs processed on a QML-certified line n Extensive packaging options

Description

The CMOS ATT3000 Series Field-Programmable Gate Array (FPGA) family provides a group of high- density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O blocks, a core array of logic blocks, and resources for interconnection. The general struc- ture of an FPGA is shown in Figure 1. The ORCA Foundry for ATT3000 Development Sys- tem provides automatic place and route of netlists. Logic and timing simulation are available as design verification alternatives. The design editor is used for interactive design optimization and to compile the data pattern that represents the configuration pro- gram. The FPGA’s user-logic functions and interconnec- tions are determined by the configuration program data stored in internal static memory cells. The pro- gram can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM, or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of pro- gram data at powerup. A serial configuration PROM can provide a very simple serial configuration pro- gram storage. * Xilinx, XC3000, and XC3100 are registered trademarks of Xilinx, Inc. Table 1. ATT3000 Series FPGAs

ATT3000 Series Field-Programmable Gate Arrays February 1997 2 Lucent Technologies Inc. Contents Page Contents Page Table of Contents

board traces connecting MSI/SSI packages. implemented by program-controlled multiplexers. Figure 1. Field-Programmable Gate Array Structure

are frequently read and rewritten. Figure 2. Static Configuration Memory Cell

ATT3000 Series Field-Programmable Gate Arrays February 1997 6 Lucent Technologies Inc. I/O Block (continued) For reliable operation, inputs should have transition times of less than 100 ns and should not be left float- ing. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 300 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor which is selected by the program to provide a constant high for otherwise undriven package pins. Normal CMOS handling precautions should be observed. Flip-flop loop delays for the IOB and logic block flip- flops are approximately 3 ns. This short delay provides good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition which can result from asser- tion of the clock during data transitions. Because of the short loop delay characteristic in the FPGA, the IOB flip-flops can be used to synchronize external signals applied to the device. When synchronized in the IOB, the signals can be used internally without further con- sideration of their clock relative timing, except as it applies to the internal logic and routing path delays. Output buffers of the IOBs provide CMOS-compatible 4 mA source-or-sink drive for high fan-out CMOS or TTL compatible signal levels. The network driving IOB pin .o becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB pin .t) can control output activity. An open-drain type output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer out- put is enabled only for a LOW. Configuration program bits for each IOB control features such as optional output register, logical signal inversion, and 3-state and slew rate control of the out- put. The program-controlled memory cells in Figure 3 control the following options: n Logical inversion of the output is controlled by one configuration program bit per IOB. n Logical 3-state control of each IOB output buffer is determined by the states of configuration program bits which turn the buffer on or off or select the output buffer 3-state control interconnection (IOB pin .t). When this IOB output control signal is high, a logic 1, the buffer is disabled and the package pin is high impedance. When this IOB output control signal is low, a logic 0, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control logic sense (output enable) is controlled by an addi- tional configuration program bit. n Direct or registered output is selectable for each IOB. The register uses a positive-edge, clocked flip-flop. The clock source may be supplied (IOB pin .ok) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer. n Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive load peak currents of noncritical outputs and minimize system noise. n A high-impedance pull-up resistor may be used to prevent unused inputs from floating. Summary of I/O Options n Inputs —Direct —Flip-flop/latch —CMOS/TTL threshold (chip inputs) —Pull-up resistor/open circuit n Outputs —Direct/registered —Inverted/not —3-state/on/off —Full speed/slew limited —3-state/output enable (inverse)

B, C, Qx, and Qy. The fourth variable can be either D or E. variables: A, D, E, and two choices among B, C, Qx, Qy. some functions of six or seven variables. Figure 5. Combinatorial Logic Diagram seven variables, the F and G outputs are identical. Figure 6. C8BCP Macro

4 VARIABLES

ately to its right and to the .c input of the CLB to its left. with CLBs are shown in Figure 12. Figure 11. Direct Interconnect

Figure 12. ATT3020 Die Edge I/O Blocks with Direct Access to Adjacent CLB

where only the outer long lines serve that function. Figure 13. Horizontal and Vertical Long Lines in the FPGA

Figure 16. Lower-Right Corner of ATT3020

3 VERTICAL LONG LINES

complete in order to allow the oscillator to stabilize.

1 MHz may require individual characterization with

20 MHz generally require a crystal which operates in a

package pins are available for general user I/O. Figure 17. Crystal Oscillator Inverter

the input levels of three mode pins: M0, M1, and M2. ing each configuration program cycle. Table 2. Configuration Modes

Figure 18. State Diagram of Configuration Process for Powerup and Reprogram to be shared with user logic signals. and the direct clock inputs are fixed at a CMOS level.

be used (see Table 2). The data may be either bit-serial or byte-parallel, depending on the configuration mode.

• The FPGA devices require four dummy bits minimum.

Figure 19. Internal Configuration Data Structure

197 CONFIGURATION DATA FRAMES

roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached. separated by 4-bit postambles. An additional final postamble bit is added for each slave device, and the result rounded up to byte boundary. each be programmed to occur one cycle before or after the I/O outputs become active. Figure 20. FPGA Configuration and Start-Up Table 3. ATT3000 Device Configuration Data

Lucent Technologies Inc. 21 Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Configuration (continued) The specific data format for each device is produced by the bit stream generation program, and one or more of these files can then be combined and appended to a length count preamble and be transformed into a PROM format file by the PROM generation program of the ORCA Foundry Development System. The tie option of the bit stream generation program defines output levels of unused blocks of a design and con- nects these to unused routing resources. This prevents indeterminate levels which might produce parasitic supply currents. This tie option can be omitted for quick breadboard iterations where a few additional mA of ICC are acceptable. The configuration bit stream begins with high preamble bits, a 4-bit preamble code, and a 24-bit length count. When configuration is initiated, a counter in the FPGA is set to 0 and begins to count the total number of con- figuration clock cycles applied to the device. As each configuration data frame is supplied to the FPGA, it is internally assembled into a data word. As each data word is completely assembled, it is loaded in parallel into one word of the internal configuration memory array. The configuration loading process is complete when the current length count equals the loaded length count and the required configuration program data frames have been written. Internal user flip-flops are held reset during configuration. Two user-programmable pins are defined in the uncon- figured FPGA: high during configuration (HDC) and low during configuration (LDC ), and DONE/PR OG may be used as external control signals during configuration. In master mode configurations, it is convenient to use LDC as an active-low EPROM chip enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options in the bit stream generation program allow timing choices of one clock earlier or later for the timing of the end of the internal logic reset and the assertion of the DONE signal. The open-drain DONE/PR OG output can be AND-tied with multiple FPGAs and used as an active- high READY, an active-low PROM enable, or a RESET to other portions of the system. The state diagram of Figure 18 illustrates the configuration process.

which begin execution from opposite ends of memory. from DOUT to DIN, DOUT to DIN, etc. cascaded to support additional FPGAs. An early DONE inhibits the data output one CCLK cycle before the FPGA I/O becomes active. Figure 21. Master Serial Mode

Figure 22. Master Parallel Mode

CS2). If all of these signals are not available, the unused inputs should be driven to their respective active levels. The FPGA will accept 1 byte of configuration data on the D[7:0] inputs for each selected processor write cycle. Figure 23. Peripheral Mode

device in master or peripheral mode. Data may also be supplied by a processor or other special circuits. Figure 24. Slave Mode

Figure 25. Master Mode with Daisy-Chained Slave Mode Devices

Lucent Technologies Inc. 27 Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Special Configuration Functions The configuration data includes control over several special functions in addition to the normal user logic functions and interconnects: n Input thresholds n Readback enable n DONE pull-up resistor n DONE timing n RESET timing n Oscillator frequency divided by two Each of these functions is controlled by configuration data bits which are selected as part of the normal development system bit stream generation process. Input Thresholds Prior to the completion of configuration, all FPGA input thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS compatible as programmed. The use of the TTL threshold option requires some additional supply current for threshold shifting. The exception is the threshold of the PWRD WN input and direct clocks which always have a CMOS input. Prior to the completion of configuration, the user I/O pins each have a high- impedance pull-up. The configuration program can be used to enable the IOB pull-up resistors in the opera- tional mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of an FPGA may be read back if it has been programmed with a bit stream in which the read- back option has been enabled. Readback may be used for verification of configuration and as a method for determining the state of internal logic nodes. There are three options in generating the configuration bit stream: n Never will inhibit the readback capability. n One-time will inhibit readback after one readback has been executed to verify the configuration. n On-command will allow unrestricted use of read- back. Readback is accomplished without the use of any of the user I/O pins; only M0, M1, and CCLK are used. The initiation of readback is produced by a low-to-high transition of the M0/RTRIG (read trigger) pin. Once the readback command has been given, the input CCLK is driven by external logic to read back each data bit in a format similar to loading. After two dummy bits, the first data frame is shifted out on the M1/RDATA (read data) pin. The logic polarity of the readback data is always inverted, such that a zero in configuration becomes a one in readback and vice versa. Each readback frame has one start bit and one stop bit per frame (configura- tion writes at least 3 stop bits per frame). All data frames must be read back to complete the process and return the mode select and CCLK pins to their normal functions. The readback data includes the current state of each internal logic block storage element, and the state of the input (.i and .ri) connection pins on each IOB. The data is imbedded into unused configuration bit posi- tions during readback. This state information is used by the FPGA development system in-circuit verifier to pro- vide visibility into the internal operation of the logic while the system is operating. To read back a uniform time sample of all storage elements, it may be neces- sary to inhibit the system clock.

ATT3000 Series Field-Programmable Gate Arrays February 1997 28 Lucent Technologies Inc. Special Configuration Functions (continued) Reprogram The FPGA configuration memory can be rewritten while the device is operating in the user’s system. To initiate a reprogramming cycle, the dual-function pack- age pin DONE/PR OG must be given a high-to-low tran- sition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the FPGA’s internal timing gen- erator. When reprogram begins, the user-programma- ble I/O output buffers are disabled and high-impedance pull-ups are provided for the package pins. The device returns to the clear state and clears the configuration memory before it prompts INITIALIZED. Since this clear operation uses chip-individual internal timing, the master might complete the clear operation and then start configuration before the slave has completed the clear operation. To avoid this, wire-AND the slave INIT pins and use them to force a RESET on the master (see Figure 25). Reprogram control is often implemented by using an external open-collector driver which pulls DONE/ PR OG low. Once it recognizes a stable request, the FPGA will hold a low until the new configuration has been completed. Even if the reprogram request is externally held low beyond the configuration period, the FPGA will begin operation upon completion of configu- ration. DONE Pull-Up DONE/ PR OG is an open-drain I/O pin that indicates the FPGA is in the operational state. An optional internal pull-up resistor can be enabled by the user of the devel- opment system when the bit stream generation pro- gram is executed. The DONE/PR OG pins of multiple FPGAs in a daisy chain may be connected together to indicate that all are DONE or to direct them all to repro- gram. DONE Timing The timing of the DONE status signal can be controlled by a selection in the bit stream generation program to occur a CCLK cycle before, or after, the timing of out- puts being activated (see Figure 20). This facilitates control of external functions, such as a PROM enable or holding a system in a wait-state. RESET Timing As with DONE timing, the timing of the release of the internal RESET can be controlled by a selection in the bit stream generation program to occur a CCLK cycle before, or after, the timing of outputs being enabled (see Figure 20). This reset maintains all user-program- mable flip-flops and latches in a zero state during con- figuration. Crystal Oscillator Division A selection in the bit stream generation program allows the user to incorporate a dedicated divide-by-two flip- flop in the crystal oscillator function. This provides higher assurance of a symmetrical timing signal. Although the frequency stability of crystal oscillators is high, the symmetry of the waveform can be affected by bias or feedback drive.

ATT3000 Series Field-Programmable Gate Arrays February 1997 30 Lucent Technologies Inc. Performance (continued) Logic Block Performance Logic block performance is expressed as the propaga- tion time from the interconnect point at the input of the combinatorial logic to the output of the block in the interconnect area. Combinatorial performance is inde- pendent of the specific logic function because of the table look-up based implementation. Timing is different when the combinatorial logic is used in conjunction with the storage element. For the combinatorial logic func- tion driving the data input of the storage element, the critical timing is data setup relative to the clock edge provided to the flip-flop element. The delay from the clock source to the output of the logic block is critical in the timing of signals produced by storage elements. Loading of a logic block output is limited only by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a function of supply voltage and temperature (see Figures 28 and 29). Interconnect Performance Interconnect performance depends on the routing resource used to implement the signal path. As dis- cussed earlier, direct interconnect from block to block provides a fast path for a signal. The single metal segment used for long lines exhibits low resistance from end to end, but relatively high capacitance. Signals driven through a programmable switch will have the additional impedance of the switch added to their normal drive impedance. General-purpose interconnect performance depends on the number of switches and segments used, the presence of the bidirectional repowering buffers, and the overall loading on the signal path at all points along the path. In calculating the worst-case timing for a general interconnect path, the timing calculator portion of the ORCA Foundry Development System accounts for all of these elements. As an approximation, interconnect timing is propor- tional to the summation of totals of local metal seg- ments beyond each programmable switch. In effect, the time is a sum of R-C time each approximated by an R times the total C it drives. The R of the switch and the C of the interconnect are functions of the particular device performance grade. For a string of three local interconnects, the approxi- mate time at the first segment after the first switch resistance would be three units—an additional two units after the next switch plus an additional unit after the last switch in the chain. The interconnect R-C chain terminates at each repowering buffer. The capacitance of the actual block inputs is not significant; the capaci- tance is in the interconnect metal and switches. Figure 30 illustrates this.

heavily loaded output buffers near the ground pads. ing in the same direction simultaneously. Figure 31. FPGA Power Distribution

Lucent Technologies Inc. 33 Data Sheet February 1997 ATT3000 Series Field-Programmable Gate Arrays Power (continued) Power Dissipation The FPGA exhibits the low power consumption charac- teristic of CMOS ICs. The configuration option of TTL chip input threshold requires power for the threshold reference. The power required by the static memory cells that hold the configuration data is very low and may be maintained in a powerdown mode. Typically, most of the power dissipation is produced by external capacitive loads on the output buffers. This load and frequency dependent power is 25 µW/pF/MHz per output. Another component of I/O power is the dc loading on each output pin by devices driven by the FPGA. Internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. In an FPGA, the fraction of nodes changing on a given clock is typically low (10% to 20%). For example, in a large binary counter, the average clock cycle produces changes equal to one CLB output at the clock frequency. Typical global clock buffer power is between 1.7 mW/MHz for the ATT3020 and 3.5 mW/ MHz for the ATT3090. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each configurable logic block output requires about 0.22 mW/MHz of its output frequency: Total Power =VCC + ICCO + External (dc + Capacitive) + Internal (CLB + IOB + Long Line + Pull-up) Because the control storage of the FPGA is CMOS static memory, its cells require a very low standby cur- rent for data retention. In some systems, this low data retention current characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA has built-in powerdown logic which, when activated, will disable normal opera- tion of the device and retain only the configuration data. All internal operation is suspended and output buffers are placed in their high-impedance state with no pull- ups. Powerdown data retention is possible with a sim- ple battery backup circuit, because the power require- ment is extremely low. For retention at 2.4 V, the required current is typically on the order of 50 nA. To force the FPGA into the powerdown state, the user must pull the PWRD WN pin low and continue to supply a retention voltage to the VCC pins of the package. When normal power is restored, VCC is elevated to its normal operating voltage and PWRD WN is returned to a high. The FPGA resumes operation with the same internal sequence that occurs at the conclusion of configuration. Internal I/O and logic block storage ele- ments will be reset, the outputs will become enabled, and the DONE/PR OG pin will be released. No configu- ration programming is involved. When the power supply is removed from a CMOS device, it is possible to supply some power from an input signal. The conventional electrostatic input pro- tection is implemented with diodes to the supply and ground. A positive voltage applied to an I/O will cause the positive protection diode to conduct and drive the power pin. This condition can produce invalid power conditions and should be avoided. A large series resis- tor might be used to limit the current or a bipolar buffer may be used to isolate the input signal.

Table 4. Permanently Dedicated Pins GND Two to eight (depending on package type) connections to ground. All must be connected. not used, PWRD WN must be tied to VCC . n Prior to the start of configuration, a low input will delay the start of the configuration process. figuration at the termination of RESET . IOB and CLB storage elements of the FPGA. a clock input for the configuration data being filtered out. read trigger to initiate a readback of configuration and storage-element data clocked by CCLK.

Table 5. I/O Pins with Special Functions configuration, this pin becomes a user-programmable I/O pin. configuration, this pin is a user I/O pin. configuration. It is available as a control output indicating that configuration is not yet completed. mode device. After configuration, this pin becomes a user-programmable I/O pin. configuration, the pins are user-programmable I/O pins.

memory device (normally not used). peripheral modes. After configuration is complete, they are user-programmed I/O pins. mode. After configuration is complete, they are user-programmed I/O pins. is data zero input in master or peripheral configuration mode. TCLKIN This is a direct CMOS level input to the global clock buffer. perform other functions before configuration is complete (see above). Table 5. I/O Pins with Special Functions (continued)

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 37 Pin Information (continued) Table 6A. ATT3000 Family Configuration (44, 68, and 84 PLCC; 100 QFP; and 100 TQFP) Configuration Mode (M2:M1:M0) PLCC * PLCC PLCC † 100 QFP 100 TQFP User OperationSlave (1:1:1) Master-Serial (0:0:0) Peripheral (1:0:1) Master-High (1:1:0) Master-Low (1:0:0) PWRDWN PWRDWN PWRDWN PWRDWN PWRDWN 7 10 12 29 26 PWRDWN VCC VCC VCC VCC VCC 12 18 22 41 38 VCC M1 (High) M1 (Low) M1 (Low) M1 (High) M1 (Low) 16 25 31 52 49 RDATA M0 (High) M0 (Low) M0 (Low) M0 (High) M0 (Low) 17 26 32 54 51 RTRIG M2 (High) M2 (Low) M2 (High) M2 (High) M2 (Low) 18 27 33 56 53 I/O HDC (High) HDC (High) HDC (High) HDC (High) HDC (High) 19 28 34 57 54 I/O LDC (Low) LDC (Low) LDC (Low) LDC (Low) LDC (Low) 20 30 36 59 56 I/O INIT‡ INIT‡ INIT‡ INIT‡ INIT‡ 22 34 42 65 62 I/O GND GND GND GND GND 23 35 43 66 63 GND 26 43 53 76 73 XTL2–I/O RESET RESET RESET RESET RESET 27 44 54 78 75 RESET DONE DONE DONE DONE DONE 28 45 55 80 77 PROG D7 D7 D7 — 46 56 81 78 I/O 30 47 57 82 79 XTL1–I/O D6 D6 D6 — 48 58 83 80 I/O D5 D5 D5 — 49 60 87 84 I/O CS0 — — — 50 61 88 85 I/O D4 D4 D4 — 51 62 89 86 I/O VCC VCC VCC VCC VCC 34 52 64 91 88 VCC D3 D3 D3 — 53 65 92 89 I/O CS1 — — — 54 66 93 90 I/O D2 D2 D2 — 55 67 94 91 I/O D1 D1 D1 — 56 70 98 95 I/O RDY/BUSY RCLK RCLK — 57 71 99 96 I/O DIN DIN D0 D0 D0 38 58 72 100 97 I/O DOUT DOUT DOUT DOUT DOUT 39 59 73 1 98 I/O CCLK CCLK CCLK CCLK CCLK 40 60 74 2 99 CCLK WS A0 A0 — 61 75 5 2 I/O CS2 A1 A1 — 62 76 6 3 I/O A2 A2 — 63 77 8 5 I/O A3 A3 — 64 78 9 6 I/O A15 A15 — 65 81 12 9 I/O A4 A4 — 66 82 13 10 I/O A14 A14 — 67 83 14 11 I/O A5 A5 — 68 84 15 12 I/O GND GND GND GND GND 1 1 1 16 13 GND A13 A13 — 2 2 17 14 I/O A6 A6 — 3 3 18 15 I/O A12 A12 — 4 4 19 16 I/O A7 A7 — 5 5 20 17 I/O A11 A11 — 6 8 23 20 I/O A8 A8 — 7 9 24 21 I/O A10 A10 — 8 10 25 22 I/O A9 A9 — 9 11 26 23 I/O Represents a 50 kΩ to 100 kΩ pull-up. * Peripheral mode and master parallel mode are not supported in the 44-pin PLCC package; see Table 7. † Pin assignments for the ATT3064/ATT3090 differ from those shown; see page 42. ‡ INIT is an open-drain output during configuration.

ATT3000 Series Field-Programmable Gate Arrays February 1997 38 Lucent Technologies Inc. Pin Information (continued) Table 6B. ATT3000 Family Configuration (132 PPGA, 144 TQFP, 160 QFP, 175 PPGA, 208 SQFP) Configuration Mode (M2:M1:M0) 132 PPGA 144 TQFP 160 QFP 175 PPGA 208 SQFP User OperationSlave (1:1:1) Master-Serial (0:0:0) Peripheral (1:0:1) Master-High (1:1:0) Master-Low (1:0:0) PWRDWN PWRDWN PWRDWN PWRDWN PWRDWN A1 1 159 B2 3 PWRDWN VCC VCC VCC VCC VCC C8 19 20 D9 26 VCC M1 (High) M1 (Low) M1 (Low) M1 (High) M1 (Low) B13 36 40 B14 48 RDATA M0 (High) M0 (Low) M0 (Low) M0 (High) M0 (Low) A14 38 42 B15 50 RTRIG M2 (High) M2 (Low) M2 (High) M2 (High) M2 (Low) C13 40 44 C15 56 I/O HDC (High) HDC (High) HDC (High) HDC (High) HDC (High) B14 41 45 E14 57 I/O LDC (Low) LDC (Low) LDC (Low) LDC (Low) LDC (Low) D14 45 49 D16 61 I/O INIT* INIT* INIT* INIT* INIT* G14 53 59 H15 77 I/O GND GND GND GND GND H12 55 19 J14 25 GND M13 69 76 P15 100 XTL2–I/O RESET RESET RESET RESET RESET P14 71 78 R15 102 RESET DONE DONE DONE DONE DONE N13 73 80 R14 107 PROG D7 D7 D7 M12 74 81 N13 109 I/O P13 75 82 T14 110 XTL1–I/O D6 D6 D6 N11 78 86 P12 115 I/O D5 D5 D5 M9 84 92 T11 122 I/O CS0 — — N9 85 93 R10 123 I/O D4 D4 D4 N8 88 98 R9 128 I/O VCC VCC VCC VCC VCC M8 90 100 N9 130 VCC D3 D3 D3 N7 92 102 P8 132 I/O CS1 — — P6 93 103 R8 133 I/O D2 D2 D2 M6 96 108 R7 138 I/O D1 D1 D1 M5 102 114 R5 145 I/O RDY/BUSY RCLK RCLK N4 103 115 P5 146 I/O DIN DIN D0 D0 D0 N2 106 119 R3 151 I/O DOUT DOUT DOUT DOUT DOUT M3 107 120 N4 152 I/O CCLK CCLK CCLK CCLK CCLK P1 108 121 R2 153 CCLK WS A0 A0 M2 111 124 P2 161 I/O CS2 A1 A1 N1 112 125 M3 162 I/O A2 A2 L2 115 128 P1 165 I/O A3 A3 L1 116 129 N1 166 I/O A15 A15 K1 119 132 M1 172 I/O A4 A4 J2 120 133 L2 173 I/O A14 A14 H1 123 136 K2 178 I/O A5 A5 H2 124 137 K1 179 I/O GND GND GND GND GND H3 126 139 J3 182 GND A13 A13 G2 128 141 H2 184 I/O A6 A6 G1 129 142 H1 185 I/O A12 A12 F2 133 147 F2 192 I/O A7 A7 E1 134 148 E1 193 I/O A11 A11 D1 137 151 D1 199 I/O A8 A8 D2 138 152 C1 200 I/O A10 A10 B1 141 155 E3 203 I/O A9 A9 C2 142 156 C2 204 I/O Represents a 50 kΩ to 100 kΩ pull-up. * INIT is an open-drain output during configuration.

Peripheral mode and master parallel mode are not supported in the M44 package. Parallel address and data pins are not assigned. Table 7. ATT3030 44-Pin PLCC Pinout

1 GND 23 GND

2 I/O 24 I/O

3 I/O 25 I/O

4 I/O 26 XTL2–I/O

5 I/O 27 RESET

6 I/O 28 DONE– PR OG

7 PWRD WN 29 I/O

8 TCLKIN–I/O 30 XTL1–BCLKIN–I/O

9 I/O 31 I/O

10 I/O 32 I/O

11 I/O 33 I/O

12 VCC 34 VCC

13 I/O 35 I/O

14 I/O 36 I/O

15 I/O 37 I/O

16 M1– RD ATA 38 DIN–I/O

17 M0–RTRIG 39 DOUT–I/O

18 M2–I/O 40 CCLK

19 HDC–I/O 41 I/O

20 LDC –I/O 42 I/O

21 I/O 43 I/O

22 INIT–I/O 44 I/O

Table 8. ATT3020, ATT3030, and ATT3042; 68-Pin PLCC and 84-Pin PLCC Pinout*

68 PLCC 84 PLCC 68 PLCC 84 PLCC

† Indicates unconnected package pins for the ATT3020.

74 pads; therefore, the corresponding pins on the 84-pin packages have no connections to an ATT3020. **Table 8. ATT3020, ATT3030, and ATT3042; 68-Pin PLCC and 84-Pin PLCC Pinout* (continued)** † Indicates unconnected package pins for the ATT3020.

• Different pin definition than ATT3020/ATT3030/ATT3042 PC84 package.

outputs are default slew-limited. Table 9. ATT3064 and ATT3090 84-Pin PLCC Pinout

12 PWRD WN 40 I/O 68 D2–I/O*

13 TCLKIN–I/O 41 INIT–I/O* 69 I/O

14 I/O 42 VCC * 70 D1–I/O

15 I/O 43 GND 71 RDY/BUSY –RCLK –I/O

16 I/O 44 I/O 72 D0–DIN–I/O

17 I/O 45 I/O 73 DOUT–I/O

18 I/O 46 I/O 74 CCLK

19 I/O 47 I/O 75 A0– WS –I/O

20 I/O 48 I/O 76 A1–CS2–I/O

21 GND* 49 I/O 77 A2–I/O

22 VCC 50 I/O 78 A3–I/O

23 I/O 51 I/O 79 I/O*

24 I/O 52 I/O 80 I/O*

25 I/O 53 XTL2–I/O 81 A15–I/O

26 I/O 54 RESET 82 A4–I/O

27 I/O 55 DONE– PR OG 83 A14–I/O

28 I/O 56 D7–I/O 84 A5–I/O

29 I/O 57 XTL1–BCLKIN–I/O 1 GND

30 I/O 58 D6–I/O 2 VCC *

31 M1– RD ATA 59 I/O 3 A13–I/O*

32 M0–RTRIG 60 D5–I/O 4 A6–I/O*

33 M2–I/O 61 CS0 –I/O 5 A12–I/O*

34 HDC–I/O 62 D4–I/O 6 A7–I/O*

35 I/O 63 I/O 7 I/O

36 LDC –I/O 64 VCC 8 A11–I/O

37 I/O 65 GND* 9 A8–I/O

38 I/O 66 D3–I/O* 10 A10–I/O

39 I/O 67 CS1 –I/O* 11 A9–I/O

asterisks, do not exist on the ATT3020, which has 74 pads; therefore, the corresponding pins have no connections. Table 10. ATT3020, ATT3030, and ATT3042 100-Pin QFP Pinout

16 GND 50 I/O* 84 I/O*

17 A13–I/O 51 I/O* 85 I/O*

18 A6–I/O 52 M1– RD ATA 86 I/O

19 A12–I/O 53 GND* 87 D5–I/O

20 A7–I/O 54 M0–RTRIG 88 CS0 –I/O

21 I/O* 55 VCC * 89 D4–I/O

22 I/O* 56 M2–I/O 90 I/O

23 A11–I/O 57 HDC–I/O 91 VCC

24 A8–I/O 58 I/O 92 D3–I/O

25 A10–I/O 59 LDC –I/O 93 CS1 –I/O

26 A9–I/O 60 I/O* 94 D2–I/O

29 PWRD WN 63 I/O 97 I/O*

30 TCLKIN–I/O 64 I/O 98 D1–I/O

31 I/O** 65 INIT–I/O 99 RCLK –RDY/B USY –I/O

32 I/O* 66 GND 100 D0–DIN–I/O

33 I/O* 67 I/O 1 DOUT–I/O

34 I/O 68 I/O 2 CCLK

35 I/O 69 I/O 3 VCC *

36 I/O 70 I/O 4 GND*

37 I/O 71 I/O 5 A0– WS –I/O

38 I/O 72 I/O 6 A1–CS2–I/O

39 I/O 73 I/O 7 I/O**

40 I/O 74 I/O* 8 A2–I/O

41 VCC 75 I/O* 9 A3–I/O

42 I/O 76 XTL2–I/O 10 I/O*

43 I/O 77* GND 11 I/O*

44 I/O 78 RESET 12 A15–I/O

45 I/O 79 VCC * 13 A4–I/O

46 I/O 80 DONE– PR OG 14 A14–I/O

47 I/O 81 D7–I/O 15 A5–I/O

48 I/O 82 XTL1–BCLKIN–I/O — —

49 I/O 83 D6–I/O — —

• Indicates unconnected package pins for the ATT3030.

Table 11. ATT3030, ATT3042, and ATT3064 100-Pin TQFP Pinout

13 GND 47 I/O 81 I/O

14 A13–I/O 48 I/O 82 I/O

15 A6–I/O 49 M1– RD ATA 83 I/O

16 A12–I/O 50 GND 84 D5–I/O

17 A7–I/O 51 M0–RTRIG 85 CS0 –I/O

18 I/O 52 VCC 86 D4–I/O

19 I/O 53 M2–I/O 87 I/O

20 A11–I/O 54 HDC–I/O 88 VCC

21 A8–I/O 55 I/O 89 D3–I/O

22 A10–I/O 56 LDC –I/O 90 CS1 –I/O

23 A9–I/O 57 I/O 91 D2–I/O

24 VCC 58 I/O 92 I/O

25 GND 59 I/O 93 I/O

26 PWRD WN 60 I/O 94 I/O

27 TCLKIN–I/O 61 I/O 95 D1–I/O

28 I/O* 62 INIT–I/O 96 RCLK –RDY/BUSY –I/O

29 I/O 63 GND 97 D0–DIN–I/O

30 I/O 64 I/O 98 DOUT–I/O

31 I/O 65 I/O 99 CCLK

32 I/O 66 I/O 100 VCC

33 I/O 67 I/O 1 GND

34 I/O 68 I/O 2 A0– WS –I/O

35 I/O 69 I/O 3 A1–CS2–I/O

36 I/O 70 I/O 4 I/O*

37 I/O 71 I/O 5 A2–I/O

38 VCC 72 I/O 6 A3–I/O

39 I/O 73 XTL2–I/O 7 I/O

40 I/O 74 GND 8 I/O

41 I/O 75 RESET 9 A15–I/O

42 I/O 76 VCC 10 A4–I/O

43 I/O 77 DONE– PR OG 11 A14–I/O

44 I/O 78 D7–I/O 12 A5–I/O

45 I/O 79 XTL1–BCLKIN–I/O — —

46 I/O 80 D6–I/O — —

• Indicates unconnected package pins for the ATT3030.

Table 12. ATT3042 and ATT3064 132-Pin PPGA Pinout

• Indicates unconnected package pins for the ATT3042.

Table 13. ATT3042 and ATT3064 144-Pin TQFP Pinout

1 PWRD WN 37 GND 73 DONE— PR OG 109 VCC

2 TCLKIN—I/O 38 M0–RTRIG 74 D7–I/O 110 GND

3 I/O* 39 VCC 75 XTL1–BCLKIN–I/O 111 A0– WS –I/O

4 I/O 40 M2–I/O 76 I/O 112 A1–CS2–I/O

5 I/O 41 HDC–I/O 77 I/O 113 I/O

6 I/O* 42 I/O 78 D6–I/O 114 I/O

7 I/O 43 I/O 79 I/O 115 A2–I/O

8 I/O 44 I/O 80 I/O* 116 A3–I/O

9 I/O* 45 LDC —I/O 81 I/O 117 I/O

10 I/O 46 I/O* 82 I/O 118 I/O

11 I/O 47 I/O 83 I/O* 119 A15–I/O

12 I/O 48 I/O 84 D5–I/O 120 A4–I/O

13 I/O 49 I/O 85 CS0 –I/O 121 I/O*

14 I/O 50 I/O* 86 I/O* 122 I/O*

15 I/O* 51 I/O 87 I/O* 123 A14 –I/O

16 I/O 52 I/O 88 D4–I/O 124 A5–I/O

17 I/O 53 INIT–I/O 89 I/O 125 —

18 GND 54 VCC 90 VCC 126 GND

19 VCC 55 GND 91 GND 127 VCC

20 I/O 56 I/O 92 D3—I/O 128 A13–I/O

21 I/O 57 I/O 93 CS1 —I/O 129 A6–I/O

22 I/O 58 I/O 94 I/O* 130 I/O*

23 I/O 59 I/O 95 I/O* 131 —

24 I/O 60 I/O 96 D2—I/O 132 I/O*

25 I/O 61 I/O 97 I/O 133 A12–I/O

26 I/O 62 I/O 98 I/O 134 A7–I/O

27 I/O 63 I/O* 99 I/O* 135 I/O

28 I/O* 64 I/O* 100 I/O 136 I/O

29 I/O 65 I/O 101 I/O* 137 A11–I/O

30 I/O 66 I/O 102 D1—I/O 138 A8–I/O

31 I/O* 67 I/O 103 RCLK —B USY /RDY—I/O 139 I/O

32 I/O* 68 I/O 104 I/O 140 I/O

33 I/O 69 XTL2—I/O 105 I/O 141 A10–I/O

34 I/O* 70 GND 106 D0—DIN—I/O 142 A9–I/O

35 I/O 71 RESET 107 DOUT–I/O 143 VCC

36 M1– RD ATA 72 VCC 108 CCLK 144 GND

• Indicates unconnected package pins for the ATT3064.

Table 14. ATT3064 and ATT3090 160-Pin QFP Pinout

1 I/O* 41 GND 81 D7–I/O 121 CCLK

2 I/O* 42 M0–RTRIG 82 XTL1–BCLKIN–I/O 122 VCC

3 I/O* 43 VCC 83 I/O* 123 GND

4 I/O 44 M2–I/O 84 I/O 124 A0– WS –I/O

5 I/O 45 HDC–I/O 85 I/O 125 A1–CS2–I/O

6 I/O 46 I/O 86 D6–I/O 126 I/O

7 I/O 47 I/O 87 I/O 127 I/O

8 I/O 48 I/O 88 I/O 128 A2–I/O

9 I/O 49 LDC –I/O 89 I/O 129 A3–I/O

10 I/O 50 I/O* 90 I/O 130 I/O

11 I/O 51 I/O* 91 I/O 131 I/O

12 I/O 52 I/O 92 D5–I/O 132 A15–I/O

13 I/O 53 I/O 93 CS0 – I/O 133 A4–I/O

14 I/O 54 I/O 94 I/O* 134 I/O

15 I/O 55 I/O 95 I/O* 135 I/O

16 I/O 56 I/O 96 I/O 136 A14 –I/O

17 I/O 57 I/O 97 I/O 137 A5–I/O

18 I/O 58 I/O 98 D4–I/O 138 I/O*

19 GND 59 INIT–I/O 99 I/O 139 GND

20 VCC 60 VCC 100 VCC 140 VCC

21 I/O* 61 GND 101 GND 141 A13–I/O

22 I/O 62 I/O 102 D3–I/O 142 A6–I/O

23 I/O 63 I/O 103 CS1 –I/O 143 I/O*

24 I/O 64 I/O 104 I/O 144 I/O*

25 I/O 65 I/O 105 I/O 145 I/O

26 I/O 66 I/O 106 I/O* 146 I/O

27 I/O 67 I/O 107 I/O* 147 A12–I/O

28 I/O 68 I/O 108 D2–I/O 148 A7–I/O

29 I/O 69 I/O 109 I/O 149 I/O

30 I/O 70 I/O 110 I/O 150 I/O

31 I/O 71 I/O 111 I/O 151 A11–I/O

32 I/O 72 I/O 112 I/O 152 A8–I/O

33 I/O 73 I/O 113 I/O 153 I/O

34 I/O 74 I/O 114 D1–I/O 154 I/O

35 I/O 75 I/O* 115 RCLK –RDY/B USY –I/O 155 A10–I/O

36 I/O 76 XTL2–I/O 116 I/O 156 A9–I/O

37 I/O 77 GND 117 I/O 157 VCC

38 I/O* 78 RESET 118 I/O* 158 GND

39 I/O* 79 VCC 119 D0–DIN–I/O 159 PWRD WN

40 M1– RD ATA 80 DONE– PR OG 120 DOUT–I/O 160 TCLKIN–I/O

Table 15. ATT3000 Family 175-Pin PPGA Pinout outputs are default slew-limited. Pins A2, A3, A15, A16, T1, T2, T3, T15, and T16 are not connected. Pin A1 does not exist.

Table 16. ATT3000 Family 208-Pin SQFP Pinout

2 GND 54 — 106 VCC 158 —

3 PWRD WN 55 VCC 107 DONE– PR OG 159 —

4 TCLKIN–I/O 56 M2–I/O 108 — 160 GND

5 I/O 57 HDC–I/O 109 D7–I/O 161 A0– WS –I/O

6 I/O 58 I/O 110 XTL1–BCLKIN–I/O 162 A1–CS2–I/O

7 I/O 59 I/O 111 I/O 163 I/O

8 I/O 60 I/O 112 I/O 164 I/O

9 I/O 61 LDC –I/O 113 I/O 165 A2–I/O

10 I/O 62 I/O 114 I/O 166 A3–I/O

11 I/O 63 I/O 115 D6–I/O 167 I/O

12 I/O 64 — 116 I/O 168 I/O

13 I/O 65 — 117 I/O 169 —

14 I/O 66 — 118 I/O 170 —

15 I/O 67 — 119 — 171 —

16 I/O 68 I/O 120 I/O 172 A15–I/O

17 I/O 69 I/O 121 I/O 173 A4–I/O

18 I/O 70 I/O 122 D5–I/O 174 I/O

19 I/O 71 I/O 123 CS0 –I/O 175 I/O

20 I/O 72 — 124 I/O 176 —

21 I/O 73 — 125 I/O 177 —

22 I/O 74 I/O 126 I/O 178 A14–I/O

23 I/O 75 I/O 127 I/O 179 A5–I/O

24 I/O 76 I/O 128 D4–I/O 180 I/O

25 GND 77 INIT–I/O 129 I/O 181 I/O

26 VCC 78 VCC 130 VCC 182 GND

27 I/O 79 GND 131 GND 183 VCC

28 I/O 80 I/O 132 D3–I/O 184 A13–I/O

29 I/O 81 I/O 133 CS1 –I/O 185 A6–I/O

30 I/O 82 I/O 134 I/O 186 I/O

31 I/O 83 — 135 I/O 187 I/O

32 I/O 84 — 136 I/O 188 —

33 I/O 85 I/O 137 I/O 189 —

34 I/O 86 I/O 138 D2–I/O 190 I/O

35 I/O 87 I/O 139 I/O 191 I/O

36 I/O 88 I/O 140 I/O 192 A12–I/O

38 I/O 90 — 142 — 194 —

39 I/O 91 — 143 I/O 195 —

40 I/O 92 — 144 I/O 196 —

41 I/O 93 I/O 145 D1–I/O 197 I/O

42 I/O 94 I/O 146 RDY/B USY –RCLK –I/O 198 I/O

43 I/O 95 I/O 147 I/O 199 A11–I/O

44 I/O 96 I/O 148 I/O 200 A8–I/O

45 I/O 97 I/O 149 I/O 201 I/O

46 I/O 98 I/O 150 I/O 202 I/O

47 I/O 99 I/O 151 D0–DIN–I/O 203 A10–I/O

48 M1– RD ATA 100 XTL2–I/O 152 DOUT–I/O 204 A9–I/O

49 GND 101 GND 153 CCLK 205 VCC

50 M0–RTRIG 102 RESET 154 VCC 206 —

ATT3000 Series Field-Programmable Gate Arrays February 1997 50 Lucent Technologies Inc. Package Thermal Characteristics When silicon die junction temperature is below the rec- ommended junction temperature of 125 °C, the temperature-activated failure mechanisms are mini- mized. There are four major factors that affect the ther- mal resistance value: silicon device size/paddle size, board-mounting configuration (board density, multilayer nature of board), package type and size, and system airflow over the package. The values in the table below reflect the capability of the various package types to dissipate heat at given airflow rates. The numbers rep- resent the delta °C/W between the ambient tempera- ture and the device junction temperature. To test package thermal characteristics, a single pack- age containing a 0.269 in. sq. test IC of each configura- tion is mounted at the center of a printed-circuit board (PCB) measuring 8 in. x 13 in. x 0.062 in. The assem- bled PCB is mounted vertically in the center of the rect- angular test section of a wind tunnel. The walls of the wind tunnel simulate adjacent boards in the electronic rack and can be adjusted to study the effects of PCB spacing. Forced air at room temperature is supplied by a pair of push-pull blowers which can be regulated to supply the desired air velocities. The air velocity is measured with a hot-wire anemometer at the center of the channel, 3 in. upstream from the package. A typical test consists of regulating the wind tunnel blowers to obtain the desired air velocity and applying power to the test IC. The power to the IC is adjusted until the maximum junction temperature (as measured by its diodes) reaches 115 °C to 120 °C. The thermal resistance Θ JA (°C/W) is computed by using the power supplied to the IC, junction temperature, ambient tem- perature, and air velocity: where: TJ = peak temperature on the active surface of the IC TA = ambient air temperature Q C = IC power The tests are repeated at several velocities from 0 fpm (feet per minute) to 1000 fpm. The definition of the junction to case thermal resistance Θ JC is: where: TC = temperature measured to the thermocouple at the top dead center of the package The actual Θ JC measurement performed at Lucent, Θ J – TDC, uses a different package mounting arrange- ment than the one defined for Θ JC in MIL-STD-883D and SEMI standards. Please contact Lucent for a dia- gram. The maximum power dissipation for a package is cal- culated from the maximum junction temperature, maxi- mum operating temperature, and the junction to ambient characteristic Θ JA. The maximum power dissi- pation for commercial grade ICs is calculated as fol- lows: max power (watts) = (125 °C – 70 °C) x (1/Θ JA), where 125 °C is the maximum junction temperature. Table 17 lists the ATT3000 plastic package thermal characteristics. Θ JA TJ TA– Θ JC TJ TC–

Table 17. ATT3000 Plastic Package Thermal Characteristics package routing, and the external leads. leads (all other leads are assumed to be grounded). should be added to each of the C1 and C2 capacitors.

• Leads designated as ground (power) can be connected to the ground plane, reducing the trace inductance to the minimum value listed.

Figure 32. Package Parasitics Table 18. Package Parasitics

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 53 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Supply Voltage Relative to GND VCC –0.5 7.0 V Input Voltage Relative to GND VIN –0.5 0.5 V Voltage Applied to 3-state Output VTS –0.5 0.5 V Storage Temperature (ambient) Tstg –65 150 °C Maximum Soldering Temperature (10 seconds at 1/16 in.) TSOL — 260 °C Junction Temperature TJ — 125 °C

ATT3000 Series Field-Programmable Gate Arrays February 1997 54 Lucent Technologies Inc.

Electrical Characteristics

• Sample tested. Note:With no output current loads, no active input or long-line pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a bit stream generation program tie option.

Table 19. dc Electrical Characteristics Over Operating Conditions

• These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.

hold time requirement (TCKDI—#5) of any CLB on the same die. Table 20. CLB Switching Characteristics (-50, -70, -100, and -125)

• These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.

hold time requirement (TCKDI—#5) of any CLB on the same die. Table 21. CLB Switching Characteristics (-3, -4, and -5)

Figure 33. CLB Switching Characteristics

• These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.

Timing is measured at pin threshold with 50 pF external capacitive loads (including test fixture). Typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pF of additional load. Typical slew-rate limited output rise/fall times are approximately 4 times longer. and <5 ns duration, which may cause problems when the FPGA drives clocks and other asynchronous signals. alternatively configured as a driven output or driven from an external source. Input pad setup time is specified with respect to the internal clock (ik). nal clock (ik) is negative. This means that pad levels changed immediately before the internal clock edge (ik) will not be recognized. Table 22. IOB Switching Characteristics (-50, -70, -100, and -125)

• These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%.

Timing is measured at pin threshold with 50 pF external capacitive loads (including test fixture). Typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pF of additional load. Typical slew-rate limited output rise/fall times are approximately 4 times longer. and <5 ns duration, which may cause problems when the FPGA drives clocks and other asynchronous signals. alternatively configured as a driven output or driven from an external source. Input pad setup time is specified with respect to the internal clock (ik). internal clock (ik) is negative. This means that pad levels changed immediately before the internal clock edge (ik) will not be recognized. Table 23. IOB Switching Characteristics (-3, -4, and -5)

Figure 34. IOB Switching Characteristics

15 TRPO65

• Timing is based on the ATT3042; for other devices, see timing calculator in ORCA Foundry.

Table 24. Buffer (Internal) Switching Characteristics

on RESET , followed by a >6 µs low level on RESET and DONE/PROG after VCC has reached 4 V. Figure 35. General FPGA Switching Characteristics functionally tested. Actual worst-case timing is provided by the timing calculator or simulation.

• RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration.

† PWRDWN transitions must occur while VCC > 4 V. Table 25. General FPGA Switching Characteristics

Figure 36. Master Serial Mode Switching Characteristics a >1 µs high level on RESET , followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V. Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high. Master serial mode timing is based on slave mode testing. Table 26. Master Serial Mode Switching Characteristics

output has no hold time requirements. Figure 37. Master Parallel Mode Switching Characteristics RESET , followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V. Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high. Table 27. Master Parallel Mode Switching Characteristics

within 60 ns after the end of WS . BUSY will stay active for several microseconds. WS may be asserted immediately after the end of BUSY . Figure 38. Peripheral Mode Switching Characteristics RESET , followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V. Configuration must be delayed until the INIT of all FPGAs is high. internal timing generator for CCLK. CCLK and DOUT timing is tested in slave mode. second-level buffer has started shifting out data. Table 28. Peripheral Mode Switching Characteristics

8 CCLKs

Figure 39. Slave Mode Switching Characteristics The maximum limit of CCLK LOW time is caused by dynamic circuitry inside the FPGA device. Configuration must be delayed until the INIT of all FPGAs is high. RESET , followed by >6 µs low level on RESET and D/P after VCC has reached 4.0 V. Table 29. Slave Mode Switching Characteristics

Figure 40. Program Readback Switching Characteristics During readback, CCLK frequency may not exceed 1 MHz. RTRIG (M0 positive transition) must not be done until after one clock following active I/O pins. Readback should not be initiated until after configuration is complete. Table 30. Program Readback Switching Characteristics

ATT3000 Series Field-Programmable Gate Arrays February 1997 68 Lucent Technologies Inc. Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, indicates the repeated design size if a tolerance is speci- fied or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension. 44-Pin PLCC Dimensions are in millimeters. 5-2506r7(C) 4.57 MAX 1.27 TYP 0.53 MAX 0.10 SEATING PLANE

0.51 MIN

PIN #1 IDENTIFIER ZONE

16.66 MAX

17.65 MAX

16.66 MAX 17.65 MAX

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 69 Outline Diagrams (continued) 68-Pin PLCC Dimensions are in millimeters. 5-2139r13(C) 27 43 PIN #1 IDENTIFIER ZONE 25.27 MAX 24.33 MAX

25.27 MAX

24.33 MAX

1.27 TYP 0.53 MAX 5.08 MAX

0.51 MIN,

0.10

ATT3000 Series Field-Programmable Gate Arrays February 1997 70 Lucent Technologies Inc. Outline Diagrams (continued) 84-Pin PLCC Dimensions are in millimeters. 5-2347r13(C)

5.08 MAX

1.27 TYP 0.53 MAX 0.10 SEATING PLANE PIN #1 IDENTIFIER ZONE 11 75 5333 32 54

29.16 MAX

30.35 MAX

30.35 MAX 29.16 MAX

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 71 Outline Diagrams (continued) 100-Pin QFP Dimensions are in millimeters. 5-2131r9(C) DETAIL A DETAIL B 3.30 MAX

0.65 TYP

0.10 2.80 ± 0.25

0.25 MAX

PIN #1 IDENTIFIER ZONE 17.20 ± 0.20 14.00 ± 0.20 20.00 ± 0.20 23.20 ± 0.20 5031 0.22/0.38 0.12 M 0.13/0.23 DETAIL B 0.25 0.73/1.03

1.60 REF

ATT3000 Series Field-Programmable Gate Arrays February 1997 72 Lucent Technologies Inc. Outline Diagrams (continued) 100-Pin TQFP Dimensions are in millimeters. 5-2146r14(C)

0.50 TYP

1.60 MAX

0.08 1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B 14.00 ± 0.20 16.00 ± 0.20 76100 26 50 14.00 ± 0.20 16.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL B 0.19/0.27 0.08 M 0.106/0.200 DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 73 Outline Diagrams (continued) 132-Pin PPGA Dimensions are in millimeters. 5-2115(C) TYPICAL THERMAL VIA PACKAGE ID 37.08 ± 0.38 37.08 ± 0.38 PIN A1 INDEX MARK A B C D E F G H J K L M N P 13 SPACES @ 2.54 = 33.02

13 SPACES @

2.54 = 33.02 PIN A1 CORNER 2.16 ± 0.23 1.19 ± 0.20 0.46 ± 0.05 1.78 ± 0.20 TYP 4 PLACES 5.21 ± 0.20

ATT3000 Series Field-Programmable Gate Arrays February 1997 74 Lucent Technologies Inc. Outline Diagrams (continued) 144-Pin TQFP Dimensions are in millimeters. 5-3815r5(C) 0.08 1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B PIN #1 IDENTIFIER ZONE 20.00 ± 0.20 22.00 ± 0.20 109144 37 72 108 20.00 ± 0.20 22.00 ± 0.20 DETAIL B 0.19/0.27 0.08 M 0.106/0.200 DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE 0.25

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 75 Outline Diagrams (continued) 160-Pin QFP Dimensions are in millimeters. 5-2132r12(C) 41 80 120 121 PIN #1 IDENTIFIER ZONE 31.20 ± 0.20 28.00 ± 0.20 28.00 ± 0.20 31.20 ± 0.20 0.10 SEATING PLANE 3.42 ± 0.25 0.25 MIN0.65 TYP 4.07 MAX DETAIL A DETAIL B 0.25 0.73/1.03 DETAIL A 0.22/0.38 0.12 M 0.13/0.23 DETAIL B

ATT3000 Series Field-Programmable Gate Arrays February 1997 76 Lucent Technologies Inc. Outline Diagrams (continued) 175-Pin PPGA Dimensions are in inches. 5-2116(C) 5.21 ± 0.20 2.16 ± 0.23 1.78 ± 0.20 TYP

4 PLACES

0.46 ± 0.05 1.19 ± 0.20 PIN A1 INDICATOR INDEX MARK 42.16 ± 0.40 TYPICAL THERMAL VIA PACKAGE ID 42.16 ± 0.40 15 SPACES @ 2.54 = 38.10 SRPNMLKJHGFECBA D PIN A1 CORNER

15 SPACES @

2.54 = 38.10

February 1997 ATT3000 Series Field-Programmable Gate Arrays Lucent Technologies Inc. 77 Outline Diagrams (continued) 208-Pin SQFP Dimensions are in millimeters. 156 105 30.60 ± 0.20 157208 53 104 28.00 ± 0.20 28.00 ± 0.20 30.60 ± 0.20 PIN #1 IDENTIFIER ZONE

4.10 MAX

0.10 3.40 ± 0.20 SEATING PLANE 0.25 MIN0.50 TYP DETAIL BDETAIL A 0.50/0.75 GAGE PLANE SEATING PLANE

1.30 REF

0.25 DETAIL A DETAIL B 0.17/0.27 0.10 M 0.090/0.200 5-2196(C)R12

ATT3000 Series Field-Programmable Gate Arrays February 1997 78 Lucent Technologies Inc.

Ordering Information

The ATT3000 Series includes standard and high- performance FPGAs. The part nomenclature uses two different suffixes for speed designation. The lower- speed ATT3000 Series devices use a flip-flop toggle rate (-50, -70, -100, -125), which corresponds to XC3000 Series nomenclature. The ATT3000 Series High-Performance FPGAs use a suffix which is an approximation of the look-up table delay (-5, -4, and -3), which corresponds to XC3100 nomenclature. For packaging options, burn-in diagrams, and/or pack- age assembly information, call 1-800-EASY-FPG(A) or 1-800-327-9374. Example: ATT3020, 100 MHz, 68-Lead PLCC, Industrial Temperature Table 31. FPGA Temperature Options Table 32. FPGA Package Options

Key: C = commercial, I = industrial. Table 33. ATT3000 Series Package Matrix

ATT3000 Series Field-Programmable Gate Arrays February 1997 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro/fpga U.S.A.:Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 1-610-712-4106 (In CANADA: 1-800-553-2448, FAX 1-610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Semiconductor Marketing Ltd., 2-7-18, Higashi-Gotanda, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1770, FAX (81) 3 5421 1785 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc. Copyright © 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. February 1997 DS97-048FPGA (Replaces DS94-177FPGA)