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Document overview
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Technical content
Features
- Consumable Authentication Device
- Superior SHA-256 Hash Algorithm with 256-bit Keys
- 248-byte EEPROM for Configuration, Keys and Data: – Data zone: 5 slots of 32 bytes each – Configuration zone: 88 bytes for counting, locks and serial number
- Data Zone Features: – ParentKey slot – DerivedKey slot – Three dedicated storage slots
- High-Speed, Single-Wire Interface with Parasitic Power
- On-Die Integrated Bypass Capacitor to Allow for Parasitic Power Operation
- 1,024 Maximum Uses (Device Can Be Configured for a Lesser Amount)
- 2.0V to 4.5V Supply Voltage Range
- <150 nA Sleep Current
- Packaging Solutions: – 2-Pad VSFN contact package for mechanical attachment without PCB – 8-Pad UDFN for prototyping and early development – 4-Ball WLCSP, 2 x 2 Grid with a 0.4 mm ball pitch (contact Microchip Sales for more information)
Applications
- Ecosystem Control
- Disposables Authentication
- Anti-cloning This is a summary document. A complete document is available under NDA. For more information, please contact your local Microchip sales office. © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 1
Table 1. Pin Descriptions
2 Pad VSFN Package
Note: The exposed backside paddle of the UDFN package should be connected to GND.
© 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 3
- Introduction The ATSHA206A device supports a standard challenge-response protocol to authenticate a component or an accessory attached to a system. In use, the host system sends a challenge (i.e. a 32-byte number) to the ATSHA206A device in the client subsystem via the Message Authentication Code (MAC) command. The device generates a SHA-256 hash by combining the challenge, the DerivedKey and some additional information and returns the result as the response to the host system. The use of a hash algorithm prevents an observer on the bus from deriving the value of the secret key while allowing the system to verify that the response is correct. The DeriveKey command implements a key derivation scheme. Each time the command is used, the current value of the ParentKey slot is cryptographically combined with certain fixed values and that result is then written into the DerivedKey slot. All security functions are implemented using the industry-standard SHA-256 secure hash algorithm, using full-sized 256-bit secret keys to prevent any kind of exhaustive attack. The ATSHA206A is designed to be compatible with the ATSHA204A for a subset of memory and commands as documented in this data sheet. For a comparison, see the Compatibility with ATSHA204A section.
1.1 EEPROM Organization
The EEPROM contains a total of 248 bytes (1984 bits) and is divided into the following zones: Configuration Zone An 88-byte (704-bit) zone contains a serial number, counter information, slot read/write and lock words. Within this document, the nomenclature SN[a:b] indicates a range of bytes within a field of the configuration section. The 88 bytes are accessible from within a three-block address space. Data Zone A 160-byte (1280-bit) zone splits into five general purpose, read-only, or read/write memory slots of 32 bytes (256 bits) each, that can be used to store keys or other information related to the item to which the ATSHA206A is attached. Data Sheet Nomenclature Within this document, the terms “slot” and “block” are used interchangeably to mean a single, 256-bit (32-byte) area of a particular memory zone. Industry SHA-256 documentation uses the term “block” to indicate a 512-bit section of the message input. In addition, the I/O section of this document uses the term “block” to indicate a variable-length aggregate element transferred between the system and the device.
- In this document, the nomenclature mode[b] indicates bit b of the parameter mode.
- Byte ranges are represented as [LSB:MSB]
- Slot indicators are represented by slot[#] ATSHA206A Introduction © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 4
- Electrical Characteristics
2.1 Absolute Maximum Ratings
Operating Temperature −40°C to +85°C Storage Temperature −65°C to + 150°C Maximum Applied Voltage 5.5V DC Output Current 5.0 mA ESD Ratings: Human Body Model (HBM) ESD > 8 kV Charge Device Model (CDM) ESD > 1 kV Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2.2 Reliability
The ATSHA206A is fabricated with the high reliability Microchip CMOS EEPROM manufacturing technology. Table 2-1. EEPROM Reliability Parameter Min. Typ. Max. Units Write Endurance (each byte at +25°C) 100,000 — — Write Cycles Data Retention (at +55°C) 10 — — Years Data Retention (at +35°C) 30 50 — Years Read Endurance Unlimited Read Cycles
2.3 AC Parameters
Figure 2-1. AC Timing Diagram tHIGNORE Wake tWLO tWHI Noise Suppresion Data Comm tLIGNORE ATSHA206A
Electrical Characteristics
© 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 5
Table 2-2. AC Parameters(3) Parameter Symbol Direction Min. Typ. Max. Unit Notes Wake Low Duration(4) tWLO To ATSHA206A 60 — — µs Minimum time to guarantee wake under all conditions. Wake High Delay to Data Comm. tWHI To ATSHA206A 2.5 — — ms SIO should be stable and > VSIO for this entire duration. High-Side Glitch Filter at Active(2) tHIGNORE_IO To ATSHA206A 45 — — ns Pulses shorter than this in width will be ignored by the device when in Active mode. Low-Side Glitch Filter at Active(2) tLIGNORE_IO To ATSHA206A 45 — — ns Pulses shorter than this in width will be ignored by the device when in Active mode. High-Side Glitch Filter at Sleep tHIGNORE_S To ATSHA206A 15 — — µs Pulses shorter than this in width will be ignored by the device when in Sleep mode. Low-Side Glitch Filter at Sleep tLIGNORE_S To ATSHA206A 15 — — µs Pulses shorter than this in width will be ignored by the device when in Sleep mode. Watchdog Reset(1) tWATCHDOG To ATSHA206A 0.7 1.3 1.7 s Maximum time from wake until the device is forced into Sleep mode. Notes: 1. These parameters are ensured through characterization but not tested in production. 2. “Active” refers to either I/O mode or Compute mode, as opposed to Sleep mode. 3. V SIO means the high level to which SIO is driven during the I/O mode. The driver could be either the totem pole driver on the MCU or the resistor when the ATSHA206A returns data. 4. When the device is in Sleep mode, pulses ≤t WLO but ≥ tLIGNORE_S may cause the device to wake up and transition to the I/O mode. When in the I/O mode, the device is designed to ensure that no legal tSTART or tZLO low pulse will cause the device to reset. ATSHA206A © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 6
Figure 2-2. AC Data Transfer Timing Diagram Logic 0 tSTART tZHI tZLO Logic 1 tSTART tBIT SIO tSTART tSTART tTURNAROUND Table 2-3. AC Data Transfer Parameters Applicable from TA = −5°C to +85°C, VSIO = +2.0V to +4.2V, CL = 100 pF(2) (unless otherwise noted). Parameter Symbol Direction Min. Typ. Max. Unit Notes Start Pulse Duration tSTART To ATSHA206A 4.10 4.34 4.56 µs Note 1 From ATSHA206A 4.60 6.00 8.60 µs Note 1 Zero Transmission High Pulse tZHI To ATSHA206A 4.10 4.34 4.56 µs Note 1 From ATSHA206A 4.60 6.00 8.60 µs Note 1 Zero Transmission Low Pulse tZLO To ATSHA206A 4.10 4.34 4.56 µs Note 1 From ATSHA206A 4.60 6.00 8.60 µs Note 1 Bit Time tBIT To ATSHA206A 37 39 — µs Note 1 From ATSHA206A 41 54 78 µs Note 1 Turnaround Delay tTURNAROUND From ATSHA206A 64 80 131 µs The ATSHA206A initiates the first low-going transition after this time interval following the start of the last bit (tBIT) of the Transmit flag. To ATSHA206A 93 — — µs After the ATSHA206A transmits the last bit of a block, the system must wait this interval before sending the first bit of a flag. ATSHA206A © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 7
Notes: 1. t START, tZLO, tZHI, and tBIT are designed to be compatible with a standard UART running at 230.4 Kbaud for both transmit and receive. The UART should be set to seven data bits, no parity, and one Stop bit. 2. All performance parameters assume C L ≤ 100 pF. Bus capacitance exceeding 100 pF will reduce performance, both of AC and DC parameters.
2.4 DC Parameters
Table 2-4. DC Parameters(1,) Parameter Symbol Min. Typ. Max. Unit Notes Ambient Operating Temperature TA -40 — +85 °C — Supply Voltage(2) VSIO 2.0 — 4.5 V Voltage on SIO pin during computation and when high during transmission to ATSHA206A Current Consumption during Computation ICOMPUTE — 500 2000 µA -40°C → +85°C, VSIO = 4.5V Current Consumption during I/O Mode IIO — 125 250 µA -40°C → +85°C, VSIO = 4.5V Sleep Current(3) ISLEEP — 50 200 nA When the device is in Sleep mode, VSIO(1) ≤ 4.5V, TA ≤ +85°C Output Low Voltage VOL — — 0.4 V When the device is in I/O mode, VSIO(1) = 3.0 to 4.5V Output Low Current IOL — — 4 mA When the device is in I/O mode, VSIO(1) = 3.0 to 4.5V, VOL = 0.4V Input Low Voltage VIL GND - 0.3 — VSIO x 0.3 V — Input High Voltage VIH VSIO x 0.7 — 4.5 V — Notes: 1. V SIO is the high level to which SIO is driven during I/O mode. The driver could be either (or both) the totem pole driver on the MCU or the resistor when the ATSHA206A returns data. This is also the value that should be connected to the pull-up resistor on the SIO signal. 2. During power-up from sleep, or from a prolonged low period on SIO, the ATSHA206A will self-configure and may consume up to 500 µA for tWHI. The VSIO high level must be maintained during this phase. 3. I SLEEP varies exponentially with temperature. The highest sleep current occurs at +85°C. ATSHA206A © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 8
- Compatibility with ATSHA204A The ATSHA206A is designed specifically to implement use cases associated with the authentication of disposable units, ecosystem control and anti-cloning. The commands of the ATSHA206A follow the same structure as other Microchip CryptoAuthentication products, but the number of commands and the flexibility of those commands have been significantly reduced from that of the ATSHA204A, due to the reduced application space. This simplifies the use of the ATSHA206A relative to that of the ATSHA204A.
3.1 ATSHA206A Configuration Zone
- 88-byte configuration zone, the same size as the SHA204A.
- Nothing in the configuration zone can be directly written by the customer using the Write command.
- The former I 2C Address byte Config[16] is not used and set to 0x00.
- All former slot configuration bytes Config[20:51] are set to 0x00 as default. These bytes do not affect the operation of the chip.
- The serial number is unique for each device. This is set at the time of the initial test, the same as the SHA204A.
- Config[4:8] is used to indicate whether DataStore Slots 1 and 2 are unlocked or locked. They are unique to ATSHA206A.
- Update Count and Use flags have been eliminated for Slots[0:6], Config[52:65]. Slot 7 (DerivedKey slot) Use flag and Update Count bytes remain, but have been renamed DeriveKeyFlag and DeriveKeyCount.
- ParentKey use operation remains the same and is associated with Slot 15.
- ConfigLock byte has been eliminated. DataLock is now 2 bytes, Config[87:88].
- The device is locked at time of the test. Devices are always shipped locked.
3.2 ATSHA206A Data and OTP Zones
- Slots 0-6, 11-14 have been eliminated.
- Slot 7 has been renamed DerivedKey and is configured for key storage. It is the target of the DeriveKey command.
- Slots 8-10 have been renamed DataStore. Slots 0, 1 and 2 are set for clear text writes and can be written after the Data zone is locked.
- Slots 9-10 (DataStore Slots 1 and 2) can be individually locked via the Write command when Write.Mode[5] = 1. This was not available for the SHA204A.
- Slot 15 is configured as the ParentKey slot to hold the Secret Key.
- The OTP zone has been eliminated.
3.3 ATSHA206A Command Differences
- CheckMac, GenDig, HMAC, Lock, Nonce, Pause, Random, SHA, and UpdateExtra commands have been removed.
- The DeriveKey command uses the key in Slot 15 (ParentKey slot) and various constants to derive a key and store it in Slot 7 (DerivedKey slot). Param1 and Param2 have no effect on the operation of the command. There is no flexibility in source and target locations.
- The MAC command computes a digest of Slot 7 and outputs the digest. Param1 and Param2 values have no effect on operation.
- The Nonce command is a null operation and does not generate an output.
- The Read command operates the same as the SHA204A but the slots in which it can be read are limited. All the configuration zones can be read.
- The Write command is limited to writing Slots 8-10 (DataStore Slots 0, 1 and 2), once the part has been locked and/or shipped. ATSHA206A Compatibility with ATSHA204A © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 9
- Package Marking Information As part of Microchip’s overall security features the part mark for all crypto devices is intentionally vague. The marking on the top of the package does not provide any information as to the actual device type or the manufacturer of the device. The alphanumeric code on the package provides manufacturing information and will vary with assembly lot. The packaging mark should not be used as part of any incoming inspection procedure. ATSHA206A Package Marking Information © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 10
- Package Drawings 5.1 2-Lead VSFN Package BA 0.10 C 0.10 C
0.10 C A B
C SEATING PLANE TOP VIEW END VIEW BOTTOM VIEW NOTE 1 0.10 C 0.08 C Microchip Technology Drawing C04-21315-LYB Rev D Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 2-Lead Very Thin Single Flat, No Lead Package (LYB) - 2x4 mm Body [VSFN] Atmel Legacy Global Package Code RWX © 2018 Microchip Technology Inc. D E A b e L NOTE 1 ATSHA206A Package Drawings © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 11
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2018 Microchip Technology Inc. REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Microchip Technology Drawing C04-21315-LYB Rev D Sheet 2 of 2 2-Lead Very Thin Single Flat, No Lead Package (LYB) - 2x4 mm Body [VSFN] Atmel Legacy Global Package Code RWX Number of Terminals Overall Height Terminal 1 Width Overall Width Terminal 2 Width Pitch Standoff Units Dimension Limits A b e E N
1.90 BSC
0.95 1.35 0.80 1.40 1.00 0.85
4.00 BSC
1.05 1.45 0.90 0.05 MAX L1 . 8 0 1.75 1.85Terminal Length Overall Length D 2.00 BSC Terminal 1 Center to Body Center e1 1.10 BSC ATSHA206A Package Drawings © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 12
E MAX Contact Pad Width X2 1.10 NOM BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M1. For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2019 Microchip Technology Inc. Microchip Technology Drawing C04-23315-LYB Rev D SILK SCREEN Contact Pad Length Y1 2.25 Contact Pad Length Y2 2.25 2-Lead Very Thin Single Flat, No Lead Package (LYB) - 2x4 mm Body [VSFN] Atmel Legacy Global Package Code RWX E Contact Pad Width X1 1.50 Contact Pitch E1 1.10 BSC Package Center to Contact Pad Edge Y3 0.85 Package Center to Contact Pad Edge Y4 0.85 ATSHA206A Package Drawings © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 13
5.2 8-pad UDFN BA 0.10C0.10C (DATUM B) (DATUM A) CSEATINGPLANE N 2XTOP VIEW SIDE VIEW NOTE 1 N 0.10CAB 0.10CAB 0.10C 0.08C Microchip Technology Drawing C04-21355-Q4B Rev B Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote:8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]Atmel Legacy Global Package Code YNZ © 2017 Microchip Technology Inc. D E E2K L 8X be 0.10CAB0.05C A(A3) BOTTOM VIEW ATSHA206A Package Drawings © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 14
For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: © 2017 Microchip Technology Inc. Number of TerminalsOverall Height Terminal WidthOverall WidthTerminal LengthExposed Pad Width Terminal ThicknessPitchStandoff UnitsDimension Limits A1A bE2 A3e LE N 0.50 BSC0.152 REF 1.200.350.18 0.500.00 0.250.401.30 0.550.02
3.00 BSC
1.400.450.30 0.600.05 MAX K -0.20 -Terminal-to-Exposed-Pad Overall LengthExposed Pad LengthDD21.402.00 BSC1.501.60 Microchip Technology Drawing C04-21355-Q4B Rev B Sheet 2 of 2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]Atmel Legacy Global Package Code YNZ ATSHA206A Package Drawings © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 15
RECOMMENDED LAND PATTERNDimension LimitsUnitsOptional Center Pad WidthOptional Center Pad LengthContact PitchY2X2 1.401.60MILLIMETERS0.50 BSCMINE MAX Contact Pad Length (X8)Contact Pad Width (X8)Y1X1 0.850.30 NOM CContact Pad Spacing2.90Contact Pad to Center Pad (X8)G10.33Thermal Via DiameterVThermal Via PitchEV 0.301.00 For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packagingNote: © 2017 Microchip Technology Inc.Microchip Technology Drawing C04-23355-Q4B Rev B 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]Atmel Legacy Global Package Code YNZ Y1SILK SCREENX1E C EVG2 ØV Contact Pad to Contact Pad (X6)G20.20 ATSHA206A Package Drawings © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 16
- Revision History Revision C (March 2021)
- Removed the TSB (MGH) package
- Updated the UDFN package option Revision B (April 2020)
- Removed WLCSP Packaging Outline Drawing
- Added ESD information to Absolute Maximum Ratings
- Updated VSFN Package Diagram Revision A (December 2019) Original release of this document ATSHA206A
Revision History
© 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 17
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- Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: www.microchip.com/support ATSHA206A © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 18
Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XXX XX -X Device Package Customer Code Tape and Reel Device: ATSHA206A: Cryptographic Co-Processor with Secure Hardware-Based Key Storage Package Options MBH 2RC-2, 2-Pad, 4.0 x 2.00 mm Body, 0.90 mm Maximum Thickness, Very Thin Single Flat No Lead Package (VSFN) MAH 8-Pad, 2.0 x 3.0 mm Body with Exposed Paddle UDFN — 4-Ball Wafer Level CSP(3) Customer Code <xx> Unique two digit alphanumeric code for each customer. This will be assigned by Microchip. Delivery Options B Bulk S Sample Devices in Tape and Reel Examples:
- ATSHA206A-MAH1X-S: 8-PAD 2.0 x 3.0 mm UDFN Package. Sample Devices Sold in Tape and Reel Format. NOT FOR PRODUCTION.
- ATSHA206A-MBH1X-B: 2-Pad 4.0 x 2.00 mm body VSFN Package. Sample Devices Sold in Bulk Only. NOT FOR PRODUCTION.
- ATSHA206A-MBH<xx>-B: 2-Pad 4.0 x 2.00 mm body VSFN Package. Customer Specific Ordering Code Format. Sold in Bulk. Notes: 1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip sales office for package availability with the Tape and Reel option. 2. Sample units and customer units are only provided in Bulk format. Tape and Reel options are not currently available. 3. Contact your Microchip sales office if interested in the WLCSP package. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices:
- Microchip products meet the specifications contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.
- Microchip is willing to work with any customer who is concerned about the integrity of its code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. ATSHA206A © 2021 Microchip Technology Inc. Summary Datasheet DS40002175C-page 19
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