ATF-541M4 BOARDCOM | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Features
- High linearity performance
- Single Supply Enhancement Mode Technology[1]
- Very low noise figure
- Excellent uniformity in product specifications
- 800 micron gate width
- Miniature leadless package 1.4 mm x 1.2 mm x 0.7 mm
- Tape‑and‑Reel packaging option available Specifications 2 GHz; 3 V, 60 mA (Typ.)
- 35.8 dBm output 3rd order intercept
- 21.4 dBm output power at 1 dB gain compression
- 0.5 dB noise figure
- 17.5 dB associated gain
Applications
- Low Noise Amplifier and Driver Amplifier for Cellular/ PCS and WCDMA Base Stations
- LNA and Driver Amplifier for WLAN, WLL/RLL and MMDS applications
- General purpose discrete E‑PHEMT for ultra low noise applications in the 450 MHz to 10 GHz frequency range Note: 1. Enhancement mode technology requires positive Vgs, thereby eliminating the need for the negative gate voltage associated with conventional depletion mode devices. MiniPak 1.4 mm x 1.2 mm Package Pin Connections and Package Marking Note: Top View. Package marking provides orientation, product identifica‑ tion and date code. “R” = Device Type Code “x” = Date code character. A different character is assigned for each month and year. Source Pin 3 Gate Pin 2 Source Pin 1 Drain Pin 4 Rx Rx
Symbol Parameter and Test Condition Units Min. Typ. Max.
- Measurements obtained using production test board described in Figure 5.
50 Ohm
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Gain, P1dB, OIP3, and OIP3 measurements. This circuit represents a trade-off between an opti - mal noise match, maximum OIP3 match and associated impedance matching circuit losses. Circuit losses have been de-embedded from actual measurements. Symbol Parameter and Test Condition Units Min. Typ. Max.
- F min and associated gain at minimum noise figure (Ga) values are based on a set of 16 noise figure measurements made at 16 different im‑
section for more information.
- P1dB and OIP3 measurements made in an InterContinental Microwave (ICM) test fixture with double stub tuners and bias tees. The input was
tuned for minimum noise figure and the output was tuned for maximum OIP3.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From
these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 16. MSG/MAG and |S21|2 vs.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From
these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 17. MSG/MAG and |S21|2 vs.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From
these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 18. MSG/MAG and |S21|2 vs.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From
these measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 19. MSG/MAG and |S21|2 vs.
S and Noise Parameter Measurements The position of the reference planes used for the measurement of both S and Noise Parameter measurements is shown in Figure 20. The reference plane can be described as being at the center of both the gate and drain pads. S and noise parameters are measured with a 50 ohm microstrip test fixture made with a 0.010" thickness alu ‑ minum substrate. Both source leads are connected directly to ground via a 0.010" thickness metal rib which provides a very low inductance path to ground for both source leads. The inductance associated with the ad ‑ dition of printed circuit board plated through holes and source bypass capacitors must be added to the computer circuit simulation to prop‑ erly model the effect of grounding the source leads in a typical amplifier design. Gate Pin 2 Source Pin 3 Drain Pin 4 Source Pin 1 Reference Plane Microstrip Transmission Lines Sx Figure 20. Noise Parameter Applications Information The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these measurements, a true Fmin is calculated. Fmin represents the true minimum noise figure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50Ω, to an impedance repre‑ sented by the reflection coefficient Γo. The designer must design a matching network that will present Γo to the device with minimal associated circuit losses. The noise figure of the com ‑ pleted amplifier is equal to the noise figure of the device plus the losses of the matching network preceding the device. The noise figure of the device is equal to Fmin only when the device is presented with Γo. If the reflection coefficient of the matching network is other than Γo, then the noise figure of the device will be greater than Fmin based on the following equation. NF = Fmin + 4 Rn |Γs – Γo | 2 Where Rn/Zo is the normalized noise resistance, Γo is the optimum reflec ‑ tion coefficient required to produce Fmin and Γs is the reflection coeffi ‑ cient of the source impedance actu ‑ ally presented to the device. The losses of the matching networks are non‑zero and they will also add to the noise figure of the device creating a higher amplifier noise figure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. Γo is typically fairly low at higher frequencies and increases as fre ‑ quency is lowered. Larger gate width devices will typically have a lower Γo as compared to narrower gate width devices. Typically for FETs , the higher Γo usually infers that an impedance much higher than 50Ω is required for the device to produce Fmin. At VHF frequencies and even lower L Band frequencies, the required imped ‑ ance can be in the vicinity of several thousand ohms. Matching to such a high impedance requires very hi ‑Q components in order to minimize cir‑ cuit losses. As an example at 900 MHz, when airwwound coils (Q>100)are used for matching networks, the loss can still be up to 0.25 dB which will add directly to the noise figure of the device. Using muiltilayer molded in ‑ ductors with Qs in the 30 to 50 range results in additional loss over the air‑ wound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB Fmin of the device creating an ampli‑ fier noise figure of nearly 0.65 dB. SMT Assembly The package can be soldered us ‑ ing either lead ‑bearing or lead ‑free alloys (higher peak temperatures). Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g. IR or vapor phase reflow, wave soldering, etc) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the Minipak 1412 package, will reach solder reflow temperatures faster than those with a greater mass. The recommended leaded solder time‑temperature profile is shown in Figure 21. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and compo‑ nents to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp‑up and cool‑down zones are chosen to be low enough to not cause deformation of board or dam ‑ age to components due to thermal shock. The maximum temperature in the reflow zone (Tmax) should not exceed 235°C for leaded solder. These parameters are typical for a surface mount assembly process for the ATF‑541M4. As a general guide ‑ line, the circuit board and compo ‑ nents should only be exposed to the minimum temperatures and times the necessary to achieve a uniform reflow of solder. The recommended lead ‑free reflow profile is shown in Figure 22.
frequency termination for the device. Figure 1. Typical ATF-541M4 LNA with Passive Biasing. of quiescent drain current Id. rent Id will be approximately 60 mA. connected to the gate of the device. VDD is the power supply voltage. Ids is the desired drain current.
Figure 2. Typical ATF-541M4 LNA with Active Biasing. circuit’s operation are as follows. the junction of resistors R1 and R2. example R1=1450Ω and R2 =1050Ω. bias stability. R6 is chosen to be 10 KΩ. R2 is replaced with a 27KΩ resistor.
Figure 3. PCB Pad Print for Minipak 1412. the right to change these models without prior notice. 541M4 enhancement mode PHEMT.
MiniPak Package Outline Drawing
Ordering Information
Part Number No. of Devices Container ATF‑541M4‑TR1 3000 7” Reel ATF‑541M4‑TR2 10000 13” Reel ATF‑541M4‑BLK 100 antistatic bag Solder Pad Dimensions 1.44 (0.058) 1.40 (0.056) Top view Side view Dimensions are in millimeteres (inches) Bottom view 1.20 (0.048) 1.16 (0.046) 0.70 (0.028) 0.58 (0.023) 1.12 (0.045) 1.08 (0.043) 0.82 (0.033) 0.78 (0.031) 0.32 (0.013) 0.28 (0.011) -0.07 (-0.003) -0.03 (-0.001) 0.00 -0.07 (-0.003) -0.03 (-0.001) 0.42 (0.017) 0.38 (0.015) 0.92 (0.037) 0.88 (0.035) 1.32 (0.053) 1.28 (0.051) 0.00 Rx
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited, in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5988-9005EN AV01-0621EN - November 1, 2006 Device Orientation for Outline 4T, MiniPak 1412 Tape Dimensions USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL END VIEW 8 mm 4 mm TOP VIEW Note: Vx represents Package Marking Code. Device orientation is indicated by package marking. Rx Rx Rx Rx P P 0 P 2 F W C D 1 D E A 0 5 MAX. t1 (CARRIER TAPE THICKNESS) T t (COVER TAPE THICKNESS) 5 MAX. B 0 K 0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A 0 B 0 K 0 P D 1 1.40 0.05 1.53 0.05 0.80 0.05 4.00 0.10 0.80 0.05 0.055 0.002 0.064 0.002 0.031 0.002 0.157 0.004 0.031 0.002 CAVITY DIAMETER PITCH POSITION D P 0 E 1.50 0.10 4.00 0.10 1.75 0.10 0.060 0.004 0.157 0.004 0.069 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 - 0.10 0.254 0.02 0.315 + 0.012 - 0.004 0.010 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F P 2 3.50 0.05 2.00 0.05 0.138 0.002 0.079 0.002 DISTANCE WIDTH TAPE THICKNESS C T t 5.40 0.10 0.062 0.001 0.213 0.004 0.0024 0.00004 COVER TAPE A 0 B 0 o