ATF-541M4 HP | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Features
- High linearity performance
- Single Supply Enhancement Mode Technology[1]
- Very low noise figure
- Excellent uniformity in product specifications
- 800 micron gate width
- Miniature leadless package 1.4 mm x 1.2 mm x 0.7 mm
- Tape-and-Reel packaging option available Specifications 2 GHz; 3V, 60 mA (Typ.)
- 35.8 dBm output 3rd order intercept
- 21.4 dBm output power at 1 dB gain compression
- 0.5 dB noise figure
- 17.5 dB associated gain
Applications
- Low Noise Amplifier and Driver Amplifier for Cellular/PCS and WCDMA Base Stations
- LNA and Driver Amplifier for WLAN, WLL/RLL and MMDS
- General purpose discrete E-PHEMT for ultra low noise applications in the 450 MHz to 10 GHz frequency range Note: 1. Enhancement mode technology requires positive Vgs, thereby eliminating the need for the negative gate voltage associated with conventional depletion mode devices. MiniPak 1.4 mm x 1.2 mm Package Pin Connections and Package Marking Note: Top View. Package marking provides orientation, product identification and date code. “R” = Device Type Code “x” = Date code character. A different character is assigned for each month and year. Source Pin 3 Gate Pin 2 Source Pin 1 Drain Pin 4 Rx Rx
- Measurements obtained using production test board described in Figure 5.
50 Ohm
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Gain, P1dB, OIP3, and OIP3 measurements. This circuit represents a embedded from actual measurements.
- Fmin and associated gain at minimum noise figure (Ga) values are based on a set of 16 noise figure measurements made at 16 different impedances
- P1dB and OIP3 measurements made in an InterContinental Microwave (ICM) test fixture with double stub tuners and bias tees. The input was tuned for
minimum noise figure and the output was tuned for maximum OIP3.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 16. MSG/MAG and |S21|2 vs.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 17. MSG/MAG and |S21|2 vs.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 18. MSG/MAG and |S21|2 vs.
- The Fmin values are based on a set of 16 noise figure measurements made at 16 different impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- Refer to the applications section for additional information on the test fixture used for the measurement of the s and noise parameters.
Figure 19. MSG/MAG and |S21|2 vs.
S and Noise Parameter Measurements The position of the reference planes used for the measurement of both S and Noise Parameter measurements is shown in Figure 20. The reference plane can be described as being at the center of both the gate and drain pads. S and noise parameters are measured with a 50 ohm microstrip test fixture made with a 0.010" thickness aluminum substrate. Both source leads are connected directly to ground via a 0.010" thickness metal rib which provides a very low inductance path to ground for both source leads. The induc- tance associated with the addi- tion of printed circuit board plated through holes and source bypass capacitors must be added to the computer circuit simula- tion to properly model the effect of grounding the source leads in a typical amplifier design. Gate Pin 2 Source Pin 3 Drain Pin 4 Source Pin 1 Reference Plane Microstrip Transmission Lines Sx Figure 20. Noise Parameter Applications Information The Fmin values are based on a set of 16 noise figure measure- ments made at 16 different impedances using an ATN NP5 test system. From these measure- ments, a true Fmin is calculated. Fmin represents the true mini- mum noise figure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50Ω, to an impedance represented by the reflection coefficient Γo. The designer must design a matching network that will present Γo to the device with minimal associ- ated circuit losses. The noise figure of the completed amplifier is equal to the noise figure of the device plus the losses of the matching network preceding the device. The noise figure of the device is equal to Fmin only when the device is presented with Γo. If the reflection coeffi- cient of the matching network is other than Γo, then the noise figure of the device will be greater than Fmin based on the following equation. NF = Fmin + 4 Rn |Γs – Γo | 2 Where Rn/Zo is the normalized noise resistance, Γo is the opti- mum reflection coefficient required to produce Fmin and Γs is the reflection coefficient of the source impedance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise figure of the device creating a higher amplifier noise figure. The losses of the matching networks are related to the Q of the compo- nents and associated printed circuit board loss. Γo is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower Γo as compared to nar- rower gate width devices. Typi- cally for FETs , the higher Γo usually infers that an impedance much higher than 50Ω is re- quired for the device to produce Fmin. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such a high impedance requires very hi-Q components in order to minimize circuit losses. As an example at
900 MHz, when airwwound coils
(Q>100)are used for matching networks, the loss can still be up to 0.25 dB which will add di- rectly to the noise figure of the device. Using muiltilayer molded inductors with Qs in the 30 to 50 range results in additional loss over the airwound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB Fmin of the device creating an amplifier noise figure of nearly 0.65 dB. SMT Assembly The package can be soldered using either lead-bearing or lead- free alloys (higher peak tempera- tures). Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g. IR or vapor phase reflow, wave solder- ing, etc) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and ther- mal mass of components. Compo- nents with a low mass, such as the Minipak 1412 package, will reach solder reflow temperatures faster than those with a greater mass. The recommended leaded solder time-temperature profile is shown in Figure 21. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone
a bipolar junction transistor. Figure 2. Typical ATF-541M4 LNA with Active raised by 0.7 volts at the emitter. supply for the drain current. consumed by the bias network. circuit’s operation are as follows. the junction of resistors R1 and R2. to 500 µA at P1dB drive levels. limit gate current to a safe level.
Figure 3. PCB Pad Print for Minipak 1412. improvements, Agilent reserves the right to change these models without prior notice. Technologies sales representative.
MiniPak Package Outline Drawing
Ordering Information
No. of Devices Container ATF-541M4-TR1 3000 7” Reel ATF-541M4-TR2 10000 13” Reel ATF-541M4-BLK 100 antistatic bag 1.44 (0.058) 1.40 (0.056) Top view Side view Dimensions are in millimeteres (inches) Bottom view 1.20 (0.048) 1.16 (0.046) 0.70 (0.028) 0.58 (0.023) 1.12 (0.045) 1.08 (0.043) 0.82 (0.033) 0.78 (0.031) 0.32 (0.013) 0.28 (0.011) -0.07 (-0.003) -0.03 (-0.001) 0.00 -0.07 (-0.003) -0.03 (-0.001) 0.42 (0.017) 0.38 (0.015) 0.92 (0.037) 0.88 (0.035) 1.32 (0.053) 1.28 (0.051) 0.00 Rx Solder Pad Dimensions
Note: Vx represents Package Marking Code. Device orientation is indicated by package marking. Rx Rx Rx Rx P F W C D E 5° MAX. t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 5° MAX.
DESCRIPTION
SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER P 1.40 ± 0.05 1.53 ± 0.05 0.80 ± 0.05 4.00 ± 0.10 0.80 ± 0.05 0.055 ± 0.002 0.064 ± 0.002 0.031 ± 0.002 0.157 ± 0.004 0.031 ± 0.002 CAVITY DIAMETER PITCH POSITION D E 1.50 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 0.060 ± 0.004 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 - 0.10 0.254 ± 0.02 0.315 + 0.012 - 0.004 0.010 ± 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.40 ± 0.10 0.062 ± 0.001 0.213 ± 0.004 0.0024 ± 0.00004 COVER TAPE Device Orientation for Outline 4T, MiniPak 1412 Tape Dimensions For product information and a complete list of Agilent contacts and distributors, please go to our web site. www.agilent.com/semiconductors E-mail: SemiconductorSupport@agilent.com Data subject to change. Copyright © 2003 Agilent Technologies, Inc. Obsoletes 5988-4025EN July 30, 2003 5988-9005EN